LIBRARY IEEE; library trap2; USE IEEE.STD_LOGIC_1164.all; entity traps is generic (bdelay : time := 3 ns); -- board delay port ( -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n : in std_logic; DUT_IRQ_n : in std_logic; -- 3.3V LVCMOS signals - JTAG DUT_EN_JTAG : in std_logic; -- out_rng NI_EN_JTAG : in std_logic_vector(3 downto 0); -- out_rng DUT_TCK : in std_logic; DUT_TMS : in std_logic; DUT_TDI : in std_logic; DUT_TDO : out std_logic; -- LVDS signals - clock and pretrigger outputs DUT_CLK : out std_logic_vector(3 downto 0); DUT_PRE : out std_logic_vector(3 downto 0); -- LVDS signals - NI output port DUT_P4_D : out std_logic_vector(9 downto 0); DUT_P4_STR : out std_logic; DUT_OA_CTR : out std_logic; DUT_P4_CTR : in std_logic; -- LVDS signals - SCSN interface DUT_SER0_IN : out std_logic; DUT_SER0_OUT : in std_logic; DUT_SER1_IN : out std_logic; DUT_SER1_OUT : in std_logic; -- LVCMOS signals DUT_SEBD : inout std_logic_vector( 2 downto 0); -- to the 4 TRAPs -- LVCMOS signals NI_RST_n : in std_logic; NI_IRQ_n : in std_logic; -- 3.3V LVCMOS signals - JTAG NI_TCK_up : in std_logic; NI_TMS_up : in std_logic; NI_TDI_up : in std_logic; NI_TDO_up : out std_logic; NI_TCK_dn : in std_logic; NI_TMS_dn : in std_logic; NI_TDI_dn : in std_logic; NI_TDO_dn : out std_logic; -- LVDS signals NI_CLK_up : in std_logic; NI_CLK_dn : in std_logic; NI_PRE_up : in std_logic; NI_PRE_dn : in std_logic; -- LVDS signals - SCSN interface NI_SER0_IN : out std_logic; NI_SER0_OUT : in std_logic; NI_SER1_IN : out std_logic; NI_SER1_OUT : in std_logic ); end traps; architecture sim of traps is component top_pad port( RST_n : in std_logic; -- LVCMOS IRQ_n : in std_logic; -- LVCMOS TCK : in std_logic; -- JTAG pins LVCMOS TDI : in std_logic; -- LVCMOS TMS : in std_logic; -- LVCMOS TDO : out std_logic; -- LVCMOS SER0_DIN_A : inout std_logic; -- Serial link 0 LVDSIN SER0_DIN_B : inout std_logic; -- Serial link 0 LVDSIN SER0_DOUT_A : inout std_logic; -- LVDSOUT SER0_DOUT_B : inout std_logic; -- LVDSOUT SER1_DIN_A : inout std_logic; -- Serial link 1 LVDSIN SER1_DIN_B : inout std_logic; -- Serial link 1 LVDSIN SER1_DOUT_A : inout std_logic; -- LVDSOUT SER1_DOUT_B : inout std_logic; -- LVDSOUT NI_P0_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P0_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P0_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P0_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P0_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P0_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P0_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P0_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P0_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P0_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P1_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P1_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P1_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P1_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P1_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P1_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P1_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P1_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P1_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P1_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P2_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P2_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P2_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P2_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P2_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P2_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P2_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P2_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P2_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P2_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P3_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P3_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P3_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P3_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P3_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P3_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P3_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P3_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P3_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P3_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P4_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSOUT NI_P4_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSOUT NI_P4_STRB_A : inout std_logic; -- Strobe LVDSOUT NI_P4_STRB_B : inout std_logic; -- Strobe LVDSOUT NI_P4_CTRL_A : inout std_logic; -- Control LVDSIN NI_P4_CTRL_B : inout std_logic; -- Control LVDSIN NI_P_CTRL_A : inout STD_LOGIC; -- ctrl/data swich for opt. transmitter LVDSOUT NI_P_CTRL_B : inout STD_LOGIC; -- LVDSOUT CLK_ADC_IN_A : inout std_logic; -- ADC fast clock (120MHz) LVDSIN CLK_ADC_IN_B : inout std_logic; -- LVDSIN CLK_DIG_IN_A : inout std_logic; -- Digital Clock (120MHz) LVDSIN CLK_DIG_IN_B : inout std_logic; -- (second PLL) LVDSIN PRETRIGin_A : inout std_logic; -- Pretrigger LVDSIN PRETRIGin_B : inout std_logic; -- LVDSIN SEL_CLK : in std_logic_vector(3 downto 0); -- CLK120 divide ratio/Bypass LVCMOS SEBD0 : inout std_logic; -- PIO 0 SEBD1 : inout std_logic; -- PIO 1 SEBD2 : inout std_logic; -- PIO 2 OUT_RNG : in std_logic -- outer padring only LVCMOS ); end component; signal NI0_CLK_A : std_logic; signal NI0_CLK_B : std_logic; signal NI0_PRE_A : std_logic; signal NI0_PRE_B : std_logic; signal NI2_CLK_A : std_logic; signal NI2_CLK_B : std_logic; signal NI2_PRE_A : std_logic; signal NI2_PRE_B : std_logic; signal DUT_CLK_A : std_logic; signal DUT_CLK_B : std_logic; signal DUT_PRE_A : std_logic; signal DUT_PRE_B : std_logic; signal NI_CLK_up_n : std_logic; signal NI_CLK_up_p : std_logic; signal NI_PRE_up_n : std_logic; signal NI_PRE_up_p : std_logic; signal TDO1_up : std_logic; signal NI_CLK_dn_n : std_logic; signal NI_CLK_dn_p : std_logic; signal NI_PRE_dn_n : std_logic; signal NI_PRE_dn_p : std_logic; signal TDO1_dn : std_logic; signal SEL_CLK : std_logic_vector(3 downto 0); signal sc0_dout_a : std_logic_vector(0 to 4); -- 0 is the master signal sc0_dout_b : std_logic_vector(0 to 4); -- 0 is the master signal sc1_dout_a : std_logic_vector(0 to 4); signal sc1_dout_b : std_logic_vector(0 to 4); signal NI_P0_D_A : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P0_D_B : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P0_STRB_A : std_logic; -- Strobe LVDSIN signal NI_P0_STRB_B : std_logic; -- Strobe LVDSIN signal NI_P0_CTRL_A : std_logic; -- Control LVDSOUT signal NI_P0_CTRL_B : std_logic; -- Control LVDSOUT signal NI_P1_D_A : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P1_D_B : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P1_STRB_A : std_logic; -- Strobe LVDSIN signal NI_P1_STRB_B : std_logic; -- Strobe LVDSIN signal NI_P1_CTRL_A : std_logic; -- Control LVDSOUT signal NI_P1_CTRL_B : std_logic; -- Control LVDSOUT signal NI_P2_D_A : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P2_D_B : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P2_STRB_A : std_logic; -- Strobe LVDSIN signal NI_P2_STRB_B : std_logic; -- Strobe LVDSIN signal NI_P2_CTRL_A : std_logic; -- Control LVDSOUT signal NI_P2_CTRL_B : std_logic; -- Control LVDSOUT signal NI_P3_D_A : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P3_D_B : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P3_STRB_A : std_logic; -- Strobe LVDSIN signal NI_P3_STRB_B : std_logic; -- Strobe LVDSIN signal NI_P3_CTRL_A : std_logic; signal NI_P3_CTRL_B : std_logic; signal NI_P0_D_A_d : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P0_D_B_d : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P0_STRB_A_d : std_logic; -- Strobe LVDSIN signal NI_P0_STRB_B_d : std_logic; -- Strobe LVDSIN signal NI_P0_CTRL_A_d : std_logic; -- Control LVDSOUT signal NI_P0_CTRL_B_d : std_logic; -- Control LVDSOUT signal NI_P1_D_A_d : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P1_D_B_d : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P1_STRB_A_d : std_logic; -- Strobe LVDSIN signal NI_P1_STRB_B_d : std_logic; -- Strobe LVDSIN signal NI_P1_CTRL_A_d : std_logic; -- Control LVDSOUT signal NI_P1_CTRL_B_d : std_logic; -- Control LVDSOUT signal NI_P2_D_A_d : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P2_D_B_d : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P2_STRB_A_d : std_logic; -- Strobe LVDSIN signal NI_P2_STRB_B_d : std_logic; -- Strobe LVDSIN signal NI_P2_CTRL_A_d : std_logic; -- Control LVDSOUT signal NI_P2_CTRL_B_d : std_logic; -- Control LVDSOUT signal NI_P3_D_A_d : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P3_D_B_d : std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN signal NI_P3_STRB_A_d : std_logic; -- Strobe LVDSIN signal NI_P3_STRB_B_d : std_logic; -- Strobe LVDSIN signal NI_P3_CTRL_A_d : std_logic; signal NI_P3_CTRL_B_d : std_logic; signal DUT_P4_CTRL_A : std_logic; signal DUT_P4_CTRL_B : std_logic; signal DUT_SER0_DIN_A : std_logic; signal DUT_SER0_DIN_B : std_logic; signal DUT_SER1_DIN_A : std_logic; signal DUT_SER1_DIN_B : std_logic; signal DUT_CLK_i : std_logic_vector(3 downto 0); signal DUT_PRE_i : std_logic_vector(3 downto 0); signal DUT_CLK_A_d : std_logic; signal DUT_CLK_B_d : std_logic; signal DUT_PRE_A_d : std_logic; signal DUT_PRE_B_d : std_logic; signal DUT_SER0_DOUT_A: std_logic; signal DUT_SER1_DOUT_A: std_logic; signal DUT_P_CTRL_A : std_logic; signal DUT_P4_STRB_A : std_logic; signal DUT_P4_D_A : std_logic_vector(9 downto 0); signal NI0_PI0_A : std_logic_vector(9 downto 0); signal NI0_PI1_A : std_logic_vector(9 downto 0); signal NI0_PI2_A : std_logic_vector(9 downto 0); signal NI0_PI3_A : std_logic_vector(9 downto 0); signal NI1_PI0_A : std_logic_vector(9 downto 0); signal NI1_PI1_A : std_logic_vector(9 downto 0); signal NI1_PI2_A : std_logic_vector(9 downto 0); signal NI1_PI3_A : std_logic_vector(9 downto 0); signal NI2_PI0_A : std_logic_vector(9 downto 0); signal NI2_PI1_A : std_logic_vector(9 downto 0); signal NI2_PI2_A : std_logic_vector(9 downto 0); signal NI2_PI3_A : std_logic_vector(9 downto 0); signal NI3_PI0_A : std_logic_vector(9 downto 0); signal NI3_PI1_A : std_logic_vector(9 downto 0); signal NI3_PI2_A : std_logic_vector(9 downto 0); signal NI3_PI3_A : std_logic_vector(9 downto 0); signal NI0_PI0_B : std_logic_vector(9 downto 0); signal NI0_PI1_B : std_logic_vector(9 downto 0); signal NI0_PI2_B : std_logic_vector(9 downto 0); signal NI0_PI3_B : std_logic_vector(9 downto 0); signal NI1_PI0_B : std_logic_vector(9 downto 0); signal NI1_PI1_B : std_logic_vector(9 downto 0); signal NI1_PI2_B : std_logic_vector(9 downto 0); signal NI1_PI3_B : std_logic_vector(9 downto 0); signal NI2_PI0_B : std_logic_vector(9 downto 0); signal NI2_PI1_B : std_logic_vector(9 downto 0); signal NI2_PI2_B : std_logic_vector(9 downto 0); signal NI2_PI3_B : std_logic_vector(9 downto 0); signal NI3_PI0_B : std_logic_vector(9 downto 0); signal NI3_PI1_B : std_logic_vector(9 downto 0); signal NI3_PI2_B : std_logic_vector(9 downto 0); signal NI3_PI3_B : std_logic_vector(9 downto 0); begin DUT_CLK <= transport DUT_CLK_i after bdelay; DUT_PRE <= transport DUT_PRE_i after bdelay; DUT_CLK_A_d <= transport DUT_CLK_A after bdelay; DUT_CLK_B_d <= transport DUT_CLK_B after bdelay; DUT_PRE_A_d <= transport DUT_PRE_A after bdelay; DUT_PRE_B_d <= transport DUT_PRE_B after bdelay; DUT_SER0_DIN_A <= transport DUT_SER0_OUT after bdelay; DUT_SER0_DIN_B <= transport not DUT_SER0_OUT after bdelay; DUT_SER1_DIN_A <= transport DUT_SER1_OUT after bdelay; DUT_SER1_DIN_B <= transport not DUT_SER1_OUT after bdelay; sc0_dout_a(0) <= transport NI_SER0_OUT after bdelay; sc0_dout_b(0) <= transport not NI_SER0_OUT after bdelay; NI_SER0_IN <= transport not sc0_dout_a(4) after bdelay; -- + and - swapped on board! sc1_dout_a(0) <= transport NI_SER1_OUT after bdelay; sc1_dout_b(0) <= transport not NI_SER1_OUT after bdelay; NI_SER1_IN <= transport sc1_dout_a(4) after bdelay; NI_CLK_up_p <= transport NI_CLK_up after bdelay; NI_CLK_up_n <= transport not NI_CLK_up after bdelay; NI_PRE_up_p <= transport NI_PRE_up after bdelay; NI_PRE_up_n <= transport not NI_PRE_up after bdelay; NI_CLK_dn_p <= transport NI_CLK_dn after bdelay; NI_CLK_dn_n <= transport not NI_CLK_dn after bdelay; NI_PRE_dn_p <= transport NI_PRE_dn after bdelay; NI_PRE_dn_n <= transport not NI_PRE_dn after bdelay; NI_P0_D_A_d <= transport NI_P0_D_A after bdelay; NI_P1_D_A_d <= transport NI_P1_D_A after bdelay; NI_P2_D_A_d <= transport NI_P2_D_A after bdelay; NI_P3_D_A_d <= transport NI_P3_D_A after bdelay; NI_P0_D_B_d <= transport NI_P0_D_B after bdelay; NI_P1_D_B_d <= transport NI_P1_D_B after bdelay; NI_P2_D_B_d <= transport NI_P2_D_B after bdelay; NI_P3_D_B_d <= transport NI_P3_D_B after bdelay; NI_P0_STRB_A_d <= transport NI_P0_STRB_A after bdelay; NI_P1_STRB_A_d <= transport NI_P1_STRB_A after bdelay; NI_P2_STRB_A_d <= transport NI_P2_STRB_A after bdelay; NI_P3_STRB_A_d <= transport NI_P3_STRB_A after bdelay; NI_P0_STRB_B_d <= transport NI_P0_STRB_B after bdelay; NI_P1_STRB_B_d <= transport NI_P1_STRB_B after bdelay; NI_P2_STRB_B_d <= transport NI_P2_STRB_B after bdelay; NI_P3_STRB_B_d <= transport NI_P3_STRB_B after bdelay; NI_P0_CTRL_A_d <= transport NI_P0_CTRL_A after bdelay; NI_P1_CTRL_A_d <= transport NI_P1_CTRL_A after bdelay; NI_P2_CTRL_A_d <= transport NI_P2_CTRL_A after bdelay; NI_P3_CTRL_A_d <= transport NI_P3_CTRL_A after bdelay; NI_P0_CTRL_B_d <= transport NI_P0_CTRL_B after bdelay; NI_P1_CTRL_B_d <= transport NI_P1_CTRL_B after bdelay; NI_P2_CTRL_B_d <= transport NI_P2_CTRL_B after bdelay; NI_P3_CTRL_B_d <= transport NI_P3_CTRL_B after bdelay; SEL_CLK <= (others => '1'); DUT_P4_CTRL_A <= transport DUT_P4_CTR after bdelay; DUT_P4_CTRL_B <= transport not DUT_P4_CTR after bdelay; DUT_SER0_IN <= transport DUT_SER0_DOUT_A after bdelay; DUT_SER1_IN <= transport DUT_SER1_DOUT_A after bdelay; DUT_OA_CTR <= transport DUT_P_CTRL_A after bdelay; DUT_P4_STR <= transport DUT_P4_STRB_A after bdelay; DUT_P4_D <= transport DUT_P4_D_A after bdelay; -- this is just to check the jtag simulation, can be removed later -- as on the MCM tester the unused input ports of the NI trap chips are -- not connected. NI0_PI0_A <= "0010001000"; NI0_PI1_A <= "0010001001"; NI0_PI2_A <= "0010001010"; NI0_PI3_A <= "0010001011"; NI1_PI0_A <= "0010011000"; NI1_PI1_A <= "0010011001"; NI1_PI2_A <= "0010011010"; NI1_PI3_A <= "0010011011"; NI2_PI0_A <= "0010101000"; NI2_PI1_A <= "0010101001"; NI2_PI2_A <= "0010101010"; NI2_PI3_A <= "0010101011"; NI3_PI0_A <= "0010111000"; NI3_PI1_A <= "0010111001"; NI3_PI2_A <= "0010111010"; NI3_PI3_A <= "0010111011"; NI0_PI0_B <= not NI0_PI0_A; NI0_PI1_B <= not NI0_PI1_A; NI0_PI2_B <= not NI0_PI2_A; NI0_PI3_B <= not NI0_PI3_A; NI1_PI0_B <= not NI1_PI0_A; NI1_PI1_B <= not NI1_PI1_A; NI1_PI2_B <= not NI1_PI2_A; NI1_PI3_B <= not NI1_PI3_A; NI2_PI0_B <= not NI2_PI0_A; NI2_PI1_B <= not NI2_PI1_A; NI2_PI2_B <= not NI2_PI2_A; NI2_PI3_B <= not NI2_PI3_A; NI3_PI0_B <= not NI3_PI0_A; NI3_PI1_B <= not NI3_PI1_A; NI3_PI2_B <= not NI3_PI2_A; NI3_PI3_B <= not NI3_PI3_A; ni0: top_pad -- U1201 in schematic port map( RST_n => NI_RST_n, IRQ_n => NI_IRQ_n, TCK => NI_TCK_up, TDI => NI_TDI_up, TMS => NI_TMS_up, TDO => TDO1_up, SER0_DIN_A => sc0_dout_a(0), SER0_DIN_B => sc0_dout_b(0), SER0_DOUT_A => sc0_dout_a(1), SER0_DOUT_B => sc0_dout_b(1), SER1_DIN_A => sc1_dout_a(3), SER1_DIN_B => sc1_dout_b(3), SER1_DOUT_A => sc1_dout_a(4), SER1_DOUT_B => sc1_dout_b(4), NI_P0_D_A => NI0_PI0_A, NI_P0_D_B => NI0_PI0_B, NI_P0_STRB_A => '1', NI_P0_STRB_B => '0', NI_P0_CTRL_A => open, NI_P0_CTRL_B => open, NI_P0_CLKout_A => open, NI_P0_CLKout_B => open, NI_P0_PREout_A => open, NI_P0_PREout_B => open, NI_P1_D_A => NI0_PI1_A, NI_P1_D_B => NI0_PI1_B, NI_P1_STRB_A => '1', NI_P1_STRB_B => '0', NI_P1_CTRL_A => open, NI_P1_CTRL_B => open, NI_P1_CLKout_A => open, NI_P1_CLKout_B => open, NI_P1_PREout_A => open, NI_P1_PREout_B => open, NI_P2_D_A => NI0_PI2_A, NI_P2_D_B => NI0_PI2_B, NI_P2_STRB_A => '1', NI_P2_STRB_B => '0', NI_P2_CTRL_A => open, NI_P2_CTRL_B => open, NI_P2_CLKout_A => open, NI_P2_CLKout_B => open, NI_P2_PREout_A => open, NI_P2_PREout_B => open, NI_P3_D_A => NI0_PI3_A, NI_P3_D_B => NI0_PI3_B, NI_P3_STRB_A => '1', NI_P3_STRB_B => '0', NI_P3_CTRL_A => open, NI_P3_CTRL_B => open, NI_P3_CLKout_A => NI0_CLK_A, NI_P3_CLKout_B => NI0_CLK_B, NI_P3_PREout_A => NI0_PRE_A, NI_P3_PREout_B => NI0_PRE_B, NI_P4_D_A => NI_P0_D_A, NI_P4_D_B => NI_P0_D_B, NI_P4_STRB_A => NI_P0_STRB_A, NI_P4_STRB_B => NI_P0_STRB_B, NI_P4_CTRL_A => NI_P0_CTRL_A, NI_P4_CTRL_B => NI_P0_CTRL_B, NI_P_CTRL_A => open, NI_P_CTRL_B => open, CLK_ADC_IN_A => NI_CLK_up_p, CLK_ADC_IN_B => NI_CLK_up_n, CLK_DIG_IN_A => open, CLK_DIG_IN_B => open, PRETRIGin_A => NI_PRE_up_p, PRETRIGin_B => NI_PRE_up_n, SEL_CLK => SEL_CLK, SEBD0 => open, SEBD1 => open, SEBD2 => open, OUT_RNG => NI_EN_JTAG(0) ); ni1: top_pad -- U1301 in schematic port map( RST_n => NI_RST_n, IRQ_n => NI_IRQ_n, TCK => NI_TCK_up, TDI => TDO1_up, TMS => NI_TMS_up, TDO => NI_TDO_up, SER0_DIN_A => sc0_dout_a(1), SER0_DIN_B => sc0_dout_b(1), SER0_DOUT_A => sc0_dout_a(2), SER0_DOUT_B => sc0_dout_b(2), SER1_DIN_A => sc1_dout_a(2), SER1_DIN_B => sc1_dout_b(2), SER1_DOUT_A => sc1_dout_a(3), SER1_DOUT_B => sc1_dout_b(3), NI_P0_D_A => NI1_PI0_A, NI_P0_D_B => NI1_PI0_B, NI_P0_STRB_A => '0', NI_P0_STRB_B => '1', NI_P0_CTRL_A => open, NI_P0_CTRL_B => open, NI_P0_CLKout_A => open, NI_P0_CLKout_B => open, NI_P0_PREout_A => open, NI_P0_PREout_B => open, NI_P1_D_A => NI1_PI1_A, NI_P1_D_B => NI1_PI1_B, NI_P1_STRB_A => '0', NI_P1_STRB_B => '1', NI_P1_CTRL_A => open, NI_P1_CTRL_B => open, NI_P1_CLKout_A => open, NI_P1_CLKout_B => open, NI_P1_PREout_A => open, NI_P1_PREout_B => open, NI_P2_D_A => NI1_PI2_A, NI_P2_D_B => NI1_PI2_B, NI_P2_STRB_A => '0', NI_P2_STRB_B => '1', NI_P2_CTRL_A => open, NI_P2_CTRL_B => open, NI_P2_CLKout_A => open, NI_P2_CLKout_B => open, NI_P2_PREout_A => open, NI_P2_PREout_B => open, NI_P3_D_A => NI1_PI3_A, NI_P3_D_B => NI1_PI3_B, NI_P3_STRB_A => '0', NI_P3_STRB_B => '1', NI_P3_CTRL_A => open, NI_P3_CTRL_B => open, NI_P3_CLKout_A => open, NI_P3_CLKout_B => open, NI_P3_PREout_A => open, NI_P3_PREout_B => open, NI_P4_D_A => NI_P1_D_A, NI_P4_D_B => NI_P1_D_B, NI_P4_STRB_A => NI_P1_STRB_A, NI_P4_STRB_B => NI_P1_STRB_B, NI_P4_CTRL_A => NI_P1_CTRL_A, NI_P4_CTRL_B => NI_P1_CTRL_B, NI_P_CTRL_A => open, NI_P_CTRL_B => open, CLK_ADC_IN_A => NI0_CLK_A, CLK_ADC_IN_B => NI0_CLK_B, CLK_DIG_IN_A => open, CLK_DIG_IN_B => open, PRETRIGin_A => NI0_PRE_A, PRETRIGin_B => NI0_PRE_B, SEL_CLK => SEL_CLK, SEBD0 => open, SEBD1 => open, SEBD2 => open, OUT_RNG => NI_EN_JTAG(1) ); ni2: top_pad -- U1401 in schematic port map( RST_n => NI_RST_n, IRQ_n => NI_IRQ_n, TCK => NI_TCK_dn, TDI => NI_TDI_dn, TMS => NI_TMS_dn, TDO => TDO1_dn, SER0_DIN_A => sc0_dout_a(2), SER0_DIN_B => sc0_dout_b(2), SER0_DOUT_A => sc0_dout_a(3), SER0_DOUT_B => sc0_dout_b(3), SER1_DIN_A => sc1_dout_a(1), SER1_DIN_B => sc1_dout_b(1), SER1_DOUT_A => sc1_dout_a(2), SER1_DOUT_B => sc1_dout_b(2), NI_P0_D_A => NI2_PI0_A, NI_P0_D_B => NI2_PI0_B, NI_P0_STRB_A => '1', NI_P0_STRB_B => '0', NI_P0_CTRL_A => open, NI_P0_CTRL_B => open, NI_P0_CLKout_A => open, NI_P0_CLKout_B => open, NI_P0_PREout_A => open, NI_P0_PREout_B => open, NI_P1_D_A => NI2_PI1_A, NI_P1_D_B => NI2_PI1_B, NI_P1_STRB_A => '1', NI_P1_STRB_B => '0', NI_P1_CTRL_A => open, NI_P1_CTRL_B => open, NI_P1_CLKout_A => NI2_CLK_A, NI_P1_CLKout_B => NI2_CLK_B, NI_P1_PREout_A => NI2_PRE_A, NI_P1_PREout_B => NI2_PRE_B, NI_P2_D_A => NI2_PI2_A, NI_P2_D_B => NI2_PI2_B, NI_P2_STRB_A => '1', NI_P2_STRB_B => '0', NI_P2_CTRL_A => open, NI_P2_CTRL_B => open, NI_P2_CLKout_A => open, NI_P2_CLKout_B => open, NI_P2_PREout_A => open, NI_P2_PREout_B => open, NI_P3_D_A => NI2_PI3_A, NI_P3_D_B => NI2_PI3_B, NI_P3_STRB_A => '1', NI_P3_STRB_B => '0', NI_P3_CTRL_A => open, NI_P3_CTRL_B => open, NI_P3_CLKout_A => open, NI_P3_CLKout_B => open, NI_P3_PREout_A => open, NI_P3_PREout_B => open, NI_P4_D_A => NI_P2_D_A, NI_P4_D_B => NI_P2_D_B, NI_P4_STRB_A => NI_P2_STRB_A, NI_P4_STRB_B => NI_P2_STRB_B, NI_P4_CTRL_A => NI_P2_CTRL_A, NI_P4_CTRL_B => NI_P2_CTRL_B, NI_P_CTRL_A => open, NI_P_CTRL_B => open, CLK_ADC_IN_A => NI_CLK_dn_p, CLK_ADC_IN_B => NI_CLK_dn_n, CLK_DIG_IN_A => open, CLK_DIG_IN_B => open, PRETRIGin_A => NI_PRE_dn_p, PRETRIGin_B => NI_PRE_dn_n, SEL_CLK => SEL_CLK, SEBD0 => open, SEBD1 => open, SEBD2 => open, OUT_RNG => NI_EN_JTAG(2) ); ni3: top_pad -- U1501 in schematic port map( RST_n => NI_RST_n, IRQ_n => NI_IRQ_n, TCK => NI_TCK_dn, TDI => TDO1_dn, TMS => NI_TMS_dn, TDO => NI_TDO_dn, SER0_DIN_A => sc0_dout_a(3), SER0_DIN_B => sc0_dout_b(3), SER0_DOUT_A => sc0_dout_a(4), SER0_DOUT_B => sc0_dout_b(4), SER1_DIN_A => sc1_dout_a(0), SER1_DIN_B => sc1_dout_b(0), SER1_DOUT_A => sc1_dout_a(1), SER1_DOUT_B => sc1_dout_b(1), NI_P0_D_A => NI3_PI0_A, NI_P0_D_B => NI3_PI0_B, NI_P0_STRB_A => '0', NI_P0_STRB_B => '1', NI_P0_CTRL_A => open, NI_P0_CTRL_B => open, NI_P0_CLKout_A => DUT_CLK_A, NI_P0_CLKout_B => DUT_CLK_B, NI_P0_PREout_A => DUT_PRE_A, NI_P0_PREout_B => DUT_PRE_B, NI_P1_D_A => NI3_PI1_A, NI_P1_D_B => NI3_PI1_B, NI_P1_STRB_A => '0', NI_P1_STRB_B => '1', NI_P1_CTRL_A => open, NI_P1_CTRL_B => open, NI_P1_CLKout_A => open, NI_P1_CLKout_B => open, NI_P1_PREout_A => open, NI_P1_PREout_B => open, NI_P2_D_A => NI3_PI2_A, NI_P2_D_B => NI3_PI2_B, NI_P2_STRB_A => '0', NI_P2_STRB_B => '1', NI_P2_CTRL_A => open, NI_P2_CTRL_B => open, NI_P2_CLKout_A => open, NI_P2_CLKout_B => open, NI_P2_PREout_A => open, NI_P2_PREout_B => open, NI_P3_D_A => NI3_PI3_A, NI_P3_D_B => NI3_PI3_B, NI_P3_STRB_A => '0', NI_P3_STRB_B => '1', NI_P3_CTRL_A => open, NI_P3_CTRL_B => open, NI_P3_CLKout_A => open, NI_P3_CLKout_B => open, NI_P3_PREout_A => open, NI_P3_PREout_B => open, NI_P4_D_A => NI_P3_D_A, NI_P4_D_B => NI_P3_D_B, NI_P4_STRB_A => NI_P3_STRB_A, NI_P4_STRB_B => NI_P3_STRB_B, NI_P4_CTRL_A => NI_P3_CTRL_A, NI_P4_CTRL_B => NI_P3_CTRL_B, NI_P_CTRL_A => open, NI_P_CTRL_B => open, CLK_ADC_IN_A => NI2_CLK_A, CLK_ADC_IN_B => NI2_CLK_B, CLK_DIG_IN_A => open, CLK_DIG_IN_B => open, PRETRIGin_A => NI2_PRE_A, PRETRIGin_B => NI2_PRE_B, SEL_CLK => SEL_CLK, SEBD0 => open, SEBD1 => open, SEBD2 => open, OUT_RNG => NI_EN_JTAG(3) ); dut: top_pad port map( RST_n => DUT_RST_n, IRQ_n => DUT_IRQ_n, TCK => DUT_TCK, TDI => DUT_TDI, TMS => DUT_TMS, TDO => DUT_TDO, SER0_DIN_A => DUT_SER0_DIN_A, SER0_DIN_B => DUT_SER0_DIN_B, SER0_DOUT_A => DUT_SER0_DOUT_A, SER0_DOUT_B => open, SER1_DIN_A => DUT_SER1_DIN_A, SER1_DIN_B => DUT_SER1_DIN_B, SER1_DOUT_A => DUT_SER1_DOUT_A, SER1_DOUT_B => open, NI_P0_D_A => NI_P0_D_A_d, NI_P0_D_B => NI_P0_D_B_d, NI_P0_STRB_A => NI_P0_STRB_A_d, NI_P0_STRB_B => NI_P0_STRB_B_d, NI_P0_CTRL_A => NI_P0_CTRL_A, NI_P0_CTRL_B => NI_P0_CTRL_B, NI_P0_CLKout_A => DUT_CLK_i(0), NI_P0_CLKout_B => open, NI_P0_PREout_A => DUT_PRE_i(0), NI_P0_PREout_B => open, NI_P1_D_A => NI_P1_D_A_d, NI_P1_D_B => NI_P1_D_B_d, NI_P1_STRB_A => NI_P1_STRB_A_d, NI_P1_STRB_B => NI_P1_STRB_B_d, NI_P1_CTRL_A => NI_P1_CTRL_A, NI_P1_CTRL_B => NI_P1_CTRL_B, NI_P1_CLKout_A => DUT_CLK_i(1), NI_P1_CLKout_B => open, NI_P1_PREout_A => DUT_PRE_i(1), NI_P1_PREout_B => open, NI_P2_D_A => NI_P2_D_A_d, NI_P2_D_B => NI_P2_D_B_d, NI_P2_STRB_A => NI_P2_STRB_A_d, NI_P2_STRB_B => NI_P2_STRB_B_d, NI_P2_CTRL_A => NI_P2_CTRL_A, NI_P2_CTRL_B => NI_P2_CTRL_B, NI_P2_CLKout_A => DUT_CLK_i(2), NI_P2_CLKout_B => open, NI_P2_PREout_A => DUT_PRE_i(2), NI_P2_PREout_B => open, NI_P3_D_A => NI_P3_D_A_d, NI_P3_D_B => NI_P3_D_B_d, NI_P3_STRB_A => NI_P3_STRB_A_d, NI_P3_STRB_B => NI_P3_STRB_B_d, NI_P3_CTRL_A => NI_P3_CTRL_A, NI_P3_CTRL_B => NI_P3_CTRL_B, NI_P3_CLKout_A => DUT_CLK_i(3), NI_P3_CLKout_B => open, NI_P3_PREout_A => DUT_PRE_i(3), NI_P3_PREout_B => open, NI_P4_D_A => DUT_P4_D_A, NI_P4_D_B => open, NI_P4_STRB_A => DUT_P4_STRB_A, NI_P4_STRB_B => open, NI_P4_CTRL_A => DUT_P4_CTRL_A, NI_P4_CTRL_B => DUT_P4_CTRL_B, NI_P_CTRL_A => DUT_P_CTRL_A, NI_P_CTRL_B => open, CLK_ADC_IN_A => DUT_CLK_A_d, CLK_ADC_IN_B => DUT_CLK_B_d, CLK_DIG_IN_A => open, CLK_DIG_IN_B => open, PRETRIGin_A => DUT_PRE_A_d, PRETRIGin_B => DUT_PRE_B_d, SEL_CLK => SEL_CLK, SEBD0 => DUT_SEBD(0), SEBD1 => DUT_SEBD(1), SEBD2 => DUT_SEBD(2), OUT_RNG => DUT_EN_JTAG ); DUT_SEBD <= "HHH"; end;