LIBRARY IEEE; library trap2; USE IEEE.STD_LOGIC_1164.all; entity trap is generic (bdelay : time := 3 ns); -- board delay port ( -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n : in std_logic; -- LVDS signals - clock and pretrigger outputs DUT_CLK : in std_logic; DUT_PRE : in std_logic; -- LVDS signals - NI output port DUT_P4_D : out std_logic_vector(9 downto 0); DUT_P4_STR : out std_logic; DUT_P4_CTR : in std_logic; -- LVDS signals - SCSN interface DUT_SER0_IN : out std_logic; DUT_SER0_OUT : in std_logic; DUT_SER1_IN : out std_logic; DUT_SER1_OUT : in std_logic; SEBD : inout std_logic_vector(2 downto 0); PA_SCLK : out std_logic; PA_SDAT : out std_logic; PA_SSTR : out std_logic ); end trap; architecture sim of trap is component top_pad port( RST_n : in std_logic; -- LVCMOS IRQ_n : in std_logic; -- LVCMOS TCK : in std_logic; -- JTAG pins LVCMOS TDI : in std_logic; -- LVCMOS TMS : in std_logic; -- LVCMOS TDO : out std_logic; -- LVCMOS SER0_DIN_A : inout std_logic; -- Serial link 0 LVDSIN SER0_DIN_B : inout std_logic; -- Serial link 0 LVDSIN SER0_DOUT_A : inout std_logic; -- LVDSOUT SER0_DOUT_B : inout std_logic; -- LVDSOUT SER1_DIN_A : inout std_logic; -- Serial link 1 LVDSIN SER1_DIN_B : inout std_logic; -- Serial link 1 LVDSIN SER1_DOUT_A : inout std_logic; -- LVDSOUT SER1_DOUT_B : inout std_logic; -- LVDSOUT NI_P0_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P0_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P0_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P0_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P0_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P0_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P0_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P0_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P0_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P0_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P1_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P1_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P1_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P1_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P1_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P1_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P1_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P1_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P1_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P1_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P2_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P2_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P2_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P2_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P2_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P2_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P2_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P2_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P2_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P2_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P3_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P3_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P3_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P3_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P3_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P3_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P3_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P3_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P3_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P3_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P4_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSOUT NI_P4_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSOUT NI_P4_STRB_A : inout std_logic; -- Strobe LVDSOUT NI_P4_STRB_B : inout std_logic; -- Strobe LVDSOUT NI_P4_CTRL_A : inout std_logic; -- Control LVDSIN NI_P4_CTRL_B : inout std_logic; -- Control LVDSIN NI_P_CTRL_A : inout STD_LOGIC; -- ctrl/data swich for opt. transmitter LVDSOUT NI_P_CTRL_B : inout STD_LOGIC; -- LVDSOUT CLK_ADC_IN_A : inout std_logic; -- ADC fast clock (120MHz) LVDSIN CLK_ADC_IN_B : inout std_logic; -- LVDSIN CLK_DIG_IN_A : inout std_logic; -- Digital Clock (120MHz) LVDSIN CLK_DIG_IN_B : inout std_logic; -- (second PLL) LVDSIN PRETRIGin_A : inout std_logic; -- Pretrigger LVDSIN PRETRIGin_B : inout std_logic; -- LVDSIN SEL_CLK : in std_logic_vector(3 downto 0); -- CLK120 divide ratio/Bypass LVCMOS SEBD0 : inout std_logic; -- PIO 0 SEBD1 : inout std_logic; -- PIO 1 SEBD2 : inout std_logic; -- PIO 2 OUT_RNG : in std_logic -- outer padring only LVCMOS ); end component; signal SEL_CLK : std_logic_vector(3 downto 0); signal DUT_P4_CTRL_A : std_logic; signal DUT_P4_CTRL_B : std_logic; signal DUT_SER0_DIN_A : std_logic; signal DUT_SER0_DIN_B : std_logic; signal DUT_SER1_DIN_A : std_logic; signal DUT_SER1_DIN_B : std_logic; signal DUT_CLK_A_d : std_logic; signal DUT_CLK_B_d : std_logic; signal DUT_PRE_A_d : std_logic; signal DUT_PRE_B_d : std_logic; signal DUT_SER0_DOUT_A: std_logic; signal DUT_SER1_DOUT_A: std_logic; signal DUT_P4_STRB_A : std_logic; signal DUT_P4_D_A : std_logic_vector(9 downto 0); begin DUT_CLK_A_d <= transport DUT_CLK after bdelay; DUT_CLK_B_d <= transport not DUT_CLK after bdelay; DUT_PRE_A_d <= transport DUT_PRE after bdelay; DUT_PRE_B_d <= transport not DUT_PRE after bdelay; DUT_SER0_DIN_A <= transport DUT_SER0_OUT after bdelay; DUT_SER0_DIN_B <= transport not DUT_SER0_OUT after bdelay; DUT_SER1_DIN_A <= transport DUT_SER1_OUT after bdelay; DUT_SER1_DIN_B <= transport not DUT_SER1_OUT after bdelay; SEL_CLK <= (others => 'H'); DUT_P4_CTRL_A <= transport DUT_P4_CTR after bdelay; DUT_P4_CTRL_B <= transport not DUT_P4_CTR after bdelay; DUT_SER0_IN <= transport DUT_SER0_DOUT_A after bdelay; DUT_SER1_IN <= transport DUT_SER1_DOUT_A after bdelay; DUT_P4_STR <= transport DUT_P4_STRB_A after bdelay; DUT_P4_D <= transport DUT_P4_D_A after bdelay; dut: top_pad port map( RST_n => DUT_RST_n, IRQ_n => 'H', TCK => 'H', TDI => 'H', TMS => 'H', TDO => open, SER0_DIN_A => DUT_SER0_DIN_A, SER0_DIN_B => DUT_SER0_DIN_B, SER0_DOUT_A => DUT_SER0_DOUT_A, SER0_DOUT_B => open, SER1_DIN_A => DUT_SER1_DIN_A, SER1_DIN_B => DUT_SER1_DIN_B, SER1_DOUT_A => DUT_SER1_DOUT_A, SER1_DOUT_B => open, NI_P0_D_A => open, NI_P0_D_B => open, NI_P0_STRB_A => open, NI_P0_STRB_B => open, NI_P0_CTRL_A => open, NI_P0_CTRL_B => open, NI_P0_CLKout_A => open, NI_P0_CLKout_B => open, NI_P0_PREout_A => open, NI_P0_PREout_B => open, NI_P1_D_A => open, NI_P1_D_B => open, NI_P1_STRB_A => open, NI_P1_STRB_B => open, NI_P1_CTRL_A => open, NI_P1_CTRL_B => open, NI_P1_CLKout_A => open, NI_P1_CLKout_B => open, NI_P1_PREout_A => open, NI_P1_PREout_B => open, NI_P2_D_A => open, NI_P2_D_B => open, NI_P2_STRB_A => open, NI_P2_STRB_B => open, NI_P2_CTRL_A => open, NI_P2_CTRL_B => open, NI_P2_CLKout_A => open, NI_P2_CLKout_B => open, NI_P2_PREout_A => open, NI_P2_PREout_B => open, NI_P3_D_A => open, NI_P3_D_B => open, NI_P3_STRB_A => open, NI_P3_STRB_B => open, NI_P3_CTRL_A => open, NI_P3_CTRL_B => open, NI_P3_CLKout_A => open, NI_P3_CLKout_B => open, NI_P3_PREout_A => open, NI_P3_PREout_B => open, NI_P4_D_A => DUT_P4_D_A, NI_P4_D_B => open, NI_P4_STRB_A => DUT_P4_STRB_A, NI_P4_STRB_B => open, NI_P4_CTRL_A => DUT_P4_CTRL_A, NI_P4_CTRL_B => DUT_P4_CTRL_B, NI_P_CTRL_A => open, NI_P_CTRL_B => open, CLK_ADC_IN_A => DUT_CLK_A_d, CLK_ADC_IN_B => DUT_CLK_B_d, CLK_DIG_IN_A => open, CLK_DIG_IN_B => open, PRETRIGin_A => DUT_PRE_A_d, PRETRIGin_B => DUT_PRE_B_d, SEL_CLK => SEL_CLK, SEBD0 => SEBD(0), SEBD1 => SEBD(1), SEBD2 => SEBD(2), OUT_RNG => 'H' ); PA_SCLK <= '0'; PA_SDAT <= '0'; PA_SSTR <= '0'; end;