LIBRARY IEEE; library fpga1w,fpga2w; USE IEEE.STD_LOGIC_1164.all; entity top_wtb is generic( period_time : time := 10 ns; -- or 8.32 ns bdelay : time := 3 ns -- board delay ); end top_wtb; architecture struct of top_wtb is component trap is generic (bdelay : time := 3 ns); -- board delay port ( -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n : in std_logic; -- LVDS signals - clock and pretrigger outputs DUT_CLK : in std_logic; DUT_PRE : in std_logic; -- LVDS signals - NI output port DUT_P4_D : out std_logic_vector(9 downto 0); DUT_P4_STR : out std_logic; DUT_P4_CTR : in std_logic; -- LVDS signals - SCSN interface DUT_SER0_IN : out std_logic; DUT_SER0_OUT : in std_logic; DUT_SER1_IN : out std_logic; DUT_SER1_OUT : in std_logic; SEBD : inout std_logic_vector(2 downto 0); PA_SCLK : out std_logic; PA_SDAT : out std_logic; PA_SSTR : out std_logic ); end component; component adcs_dacs is port ( VMCM_Shdwn_a : in std_logic; VMCM_Shdwn_d : in std_logic; PW_INCn : in std_logic_vector(3 downto 0); PW_UDn : in std_logic_vector(3 downto 0); PW_CSn : in std_logic_vector(3 downto 0); MSply_ADC_nCS : in std_logic; MSply_ADC_INTn : out std_logic; MSply_ADC_nCSStrt : in std_logic; MSply_ADC_SDI : in std_logic; MSply_ADC_SDO : out std_logic; MSply_ADC_SCLK : in std_logic; -- DDS for the 3 ADC channels AD9854 DDS_FSK : in std_logic; DDS_ShKey : in std_logic; DDS_CSn : in std_logic; DDS_SCLK : in std_logic; DDS_UDCLK : in std_logic; DDS_SDI : in std_logic; DDS_SDO : out std_logic; -- ?? DDS_IORST : in std_logic; DDS_MRST : in std_logic; DDS_MCLK : in std_logic; -- PASA ADC ADS5221 PAADC_D : out std_logic_vector(11 downto 0); PAADC_OVR : out std_logic; PAADC_CLK : in std_logic; PAADC_Msel : in std_logic; PAADC_STDP : in std_logic; PAADC_MuxnRS : in std_logic; PAADC_MuxA : in std_logic_vector( 1 downto 0); -- PASA DACs AD9744 PasaDAC1_CLK : in std_logic; PasaDAC2_CLK : in std_logic; PasaDAC_Sleep : in std_logic; PasaDAC_D : in std_logic_vector(13 downto 0); -- Slow DAC 2xTLV5630 SlowDAC1_SCLK : in std_logic; SlowDAC2_SCLK : in std_logic; SlowDAC1_LDACn : in std_logic; SlowDAC2_LDACn : in std_logic; SlowDAC_Din : in std_logic; SlowDAC1_FS : in std_logic; SlowDAC2_FS : in std_logic; -- SC ADC TLV2548 SC_ADC_SDO : out std_logic; SC_ADC_INTn : out std_logic; SC_ADC_nCSStrt : in std_logic; SC_ADC_SCLK : in std_logic; SC_ADC_SDI : in std_logic; SC_ADC_nCS : in std_logic ); end component; component ser_int -- the serial master generic ( wait_delay : integer := 100; init_delay : integer := 4095 ); port ( reset_n : in std_logic; clk : in std_logic; ready : in std_logic; ser0din : in std_logic; ser0dout : out std_logic; PRE : out std_logic); end component; ---------------------------------------------------- -- top_pad signals ---------------------------------------------------- signal clk_gen : STD_LOGIC := '0'; signal rst_n : STD_LOGIC := '1'; signal pretrig : std_logic; -- FPGA 1 -- ADCs and DACs signal VMCM_Shdwn_a : std_logic; signal VMCM_Shdwn_d : std_logic; signal MSply_ADC_nCS : std_logic; signal MSply_ADC_INTn : std_logic; signal MSply_ADC_nCSStrt : std_logic; signal MSply_ADC_SDI : std_logic; signal MSply_ADC_SDO : std_logic; signal MSply_ADC_SCLK : std_logic; -- DDS for the 3 ADC channels AD9854 signal DDS_FSK : std_logic; signal DDS_ShKey : std_logic; signal DDS_CSn : std_logic; signal DDS_SCLK : std_logic; signal DDS_UDCLK : std_logic; signal DDS_SDI : std_logic; signal DDS_SDO : std_logic; -- ?? signal DDS_IORST : std_logic; signal DDS_MRST : std_logic; signal DDS_MCLK : std_logic; -- PASA ADC ADS5221 signal PAADC_D : std_logic_vector(11 downto 0); signal PAADC_OVR : std_logic; signal PAADC_CLK : std_logic; signal PAADC_Msel : std_logic; signal PAADC_STDP : std_logic; signal PAADC_MuxnRS : std_logic; signal PAADC_MuxA : std_logic_vector(1 downto 0); -- PASA DACs AD9744 signal PasaDAC1_CLK : std_logic; signal PasaDAC2_CLK : std_logic; signal PasaDAC_Sleep : std_logic; signal PasaDAC_D : std_logic_vector(13 downto 0); -- Slow DAC 2xTLV5630 signal SlowDAC1_SCLK : std_logic; signal SlowDAC2_SCLK : std_logic; signal SlowDAC1_LDACn : std_logic; signal SlowDAC2_LDACn : std_logic; signal SlowDAC_Din : std_logic; signal SlowDAC1_FS : std_logic; signal SlowDAC2_FS : std_logic; -- SC ADC TLV2548 signal SC_ADC_SDO : std_logic; signal SC_ADC_INTn : std_logic; signal SC_ADC_nCSStrt : std_logic; signal SC_ADC_SCLK : std_logic; signal SC_ADC_SDI : std_logic; signal SC_ADC_nCS : std_logic; -- FPGA 2 signal DUT_RST_n : std_logic; -- LVDS signals - clock and pretrigger outputs signal DUT_CLK : std_logic; signal DUT_PRE : std_logic; signal DUT_CLK_d : std_logic; signal DUT_PRE_d : std_logic; -- LVDS signals - NI output port signal dummy10bit : std_logic_vector(9 downto 0); signal DUT_P4_D : std_logic_vector(9 downto 0); signal DUT_P4_STR : std_logic; --signal DUT_OA_CTR : std_logic; signal DUT_P4_CTR : std_logic; signal DUT_P4_D_d : std_logic_vector(9 downto 0); signal DUT_P4_STR_d : std_logic; --signal DUT_OA_CTR_d : std_logic; signal DUT_P4_CTR_d : std_logic; -- LVDS signals - SCSN interface signal DUT_SER0_IN : std_logic; signal DUT_SER0_OUT : std_logic; signal DUT_SER1_IN : std_logic; signal DUT_SER1_OUT : std_logic; signal DUT_SER0_IN_d : std_logic; signal DUT_SER0_OUT_d : std_logic; signal DUT_SER1_IN_d : std_logic; signal DUT_SER1_OUT_d : std_logic; -- LVCMOS signals signal PW_INCn : std_logic_vector( 3 downto 0); signal PW_UDn : std_logic_vector( 3 downto 0); signal PW_CSn : std_logic_vector( 3 downto 0); -- LVCMOS signals - SCSN interface signal AD_SER0_IN : std_logic; signal AD_SER0_OUT : std_logic; signal AD_SER1_IN : std_logic; signal AD_SER1_OUT : std_logic; signal AD_SER0_IN_d : std_logic; signal AD_SER0_OUT_d : std_logic; signal AD_SER1_IN_d : std_logic; signal AD_SER1_OUT_d : std_logic; -- general purpose synchronization signals signal AD_SYNC_OUT : std_logic_vector(1 downto 0); signal AD_SYNC_IN : std_logic_vector(1 downto 0); signal AD_SYNC_OUT_d : std_logic_vector(1 downto 0); signal AD_SYNC_IN_d : std_logic_vector(1 downto 0); signal dummy4bit : std_logic_vector(3 downto 0); -- LVDS signals - SCSN interface signal PC_SER0_IN : std_logic; signal PC_SER0_OUT : std_logic; signal PC_SER1_IN : std_logic; signal PC_SER1_OUT : std_logic; signal PC_SER0_IN_d : std_logic; signal PC_SER0_OUT_d : std_logic; signal clk_fpga2 : std_logic; signal Logic0 : std_logic; --signal DUT_rst_fpga_n : std_logic; signal SEBD : std_logic_vector(2 downto 0); signal maxIO : std_logic_vector(7 downto 0); signal maxAD : std_logic_vector(2 downto 0); signal PA_SCLK : std_logic; signal PA_SDAT : std_logic; signal PA_SSTR : std_logic; signal TCK : std_logic; signal TMS : std_logic; signal TDI : std_logic; signal state_jtag : std_logic_vector( 3 downto 0); component max7310 IS PORT ( SCL : IN std_logic := 'U'; SDA : INOUT std_logic := 'U'; AD0 : IN std_logic := 'U'; AD1 : IN std_logic := 'U'; AD2 : IN std_logic := 'U'; IO0 : INOUT std_logic := 'U'; IO1 : INOUT std_logic := 'U'; IO2 : INOUT std_logic := 'U'; IO3 : INOUT std_logic := 'U'; IO4 : INOUT std_logic := 'U'; IO5 : INOUT std_logic := 'U'; IO6 : INOUT std_logic := 'U'; IO7 : INOUT std_logic := 'U'; RESETNeg : IN std_logic := 'U' ); end component; component jtag_sm is port ( -- JTAG signals TCK : in std_logic; TMS : in std_logic; TRST : in std_logic; -- read back s_capt_dr : out std_logic; s_capt_ir : out std_logic; s_shft_dr : out std_logic; s_shft_ir : out std_logic; state : out std_logic_vector( 3 downto 0) ); end component; begin TCK <= SEBD(1); TMS <= SEBD(2); TDI <= SEBD(0); jtg: jtag_sm port map( -- JTAG signals TCK => TCK, TMS => TMS, TRST => '1', -- read back s_capt_dr => open, s_capt_ir => open, s_shft_dr => open, s_shft_ir => open, state => state_jtag ); SEBD <= (others => 'H'); -- pull ups maxIO <= (3 => '0', 7 => '0', others => 'H'); -- pull ups maxAD <= (others => '0'); -- GND max: max7310 PORT map( SCL => SEBD(0), SDA => SEBD(1), AD0 => maxAD(0), AD1 => maxAD(1), AD2 => maxAD(2), IO0 => maxIO(0), IO1 => maxIO(1), IO2 => maxIO(2), IO3 => maxIO(3), IO4 => maxIO(4), IO5 => maxIO(5), IO6 => maxIO(6), IO7 => maxIO(7), RESETNeg => SEBD(2) ); clk_gen <= not clk_gen after 2*period_time; Logic0 <= '0'; PC_SER1_IN <= '0'; -- fpga1 DUT_SER0_OUT_d <= transport DUT_SER0_OUT after bdelay; DUT_SER0_IN_d <= transport DUT_SER0_IN after bdelay; DUT_SER1_OUT_d <= transport not DUT_SER1_OUT after bdelay; -- this signal is inverted in the connector DUT_SER1_IN_d <= transport DUT_SER1_IN after bdelay; AD_SER0_OUT_d <= transport AD_SER0_OUT after bdelay; AD_SER1_OUT_d <= transport AD_SER1_OUT after bdelay; AD_SER0_IN_d <= transport AD_SER0_IN after bdelay; AD_SER1_IN_d <= transport AD_SER1_IN after bdelay; PC_SER0_OUT_d <= transport PC_SER0_OUT after bdelay; PC_SER0_IN_d <= transport PC_SER0_IN after bdelay; AD_SYNC_OUT_d <= transport AD_SYNC_OUT after bdelay; AD_SYNC_IN_d <= transport AD_SYNC_IN after bdelay; DUT_P4_D_d <= transport not DUT_P4_D after bdelay; -- this signal is inverted in the connector DUT_P4_STR_d <= transport DUT_P4_STR after bdelay; -- DUT_OA_CTR_d <= transport DUT_OA_CTR after bdelay; DUT_P4_CTR_d <= transport DUT_P4_CTR after bdelay; DUT_CLK_d <= transport DUT_CLK after bdelay; DUT_PRE_d <= transport DUT_PRE after bdelay; DUT_rst_n <= 'H'; top_fpga1: entity fpga1w.top generic map(wafer_test => 1) port map( CLK_gen => CLK_gen, WT_STR => DUT_P4_STR_d, WT_P4D => DUT_P4_D_d, WT_CTR => DUT_P4_CTR, PA_SCLK => PA_SCLK, PA_SDAT => PA_SDAT, PA_SSTR => PA_SSTR, WRST_n => DUT_rst_n, -- Link to the other FPGA -- LVCMOS signals - SCSN interface SER0_IN => AD_SER0_OUT_d, SER0_OUT => AD_SER0_IN, SER1_IN => AD_SER1_OUT_d, SER1_OUT => AD_SER1_IN, -- general purpose synchronization signals AD_SYNC_OUT => AD_SYNC_IN, AD_SYNC_IN => AD_SYNC_OUT_d, -- ADCs and DACs VMCM_Shdwn_a => VMCM_Shdwn_a, VMCM_Shdwn_d => VMCM_Shdwn_d, PW_INCn => PW_INCn, PW_UDn => PW_UDn, PW_CSn => PW_CSn, MSply_ADC_nCS => MSply_ADC_nCS, MSply_ADC_INTn => MSply_ADC_INTn, MSply_ADC_nCSStrt => MSply_ADC_nCSStrt, MSply_ADC_SDI => MSply_ADC_SDI, MSply_ADC_SDO => MSply_ADC_SDO, MSply_ADC_SCLK => MSply_ADC_SCLK, -- DDS for the 3 ADC channels AD9854 DDS_FSK => DDS_FSK, DDS_ShKey => DDS_ShKey, DDS_CSn => DDS_CSn, DDS_SCLK => DDS_SCLK, DDS_UDCLK => DDS_UDCLK, DDS_SDI => DDS_SDI, DDS_SDO => DDS_SDO, DDS_IORST => DDS_IORST, DDS_MRST => DDS_MRST, DDS_MCLK => DDS_MCLK, -- PASA ADC ADS5221 PAADC_D => PAADC_D, PAADC_OVR => PAADC_OVR, PAADC_CLK => PAADC_CLK, PAADC_Msel => PAADC_Msel, PAADC_STDP => PAADC_STDP, PAADC_MuxnRS => PAADC_MuxnRS, PAADC_MuxA => PAADC_MuxA, -- PASA DACs AD9744 PasaDAC1_CLK => PasaDAC1_CLK, PasaDAC2_CLK => PasaDAC2_CLK, PasaDAC_Sleep => PasaDAC_Sleep, PasaDAC_D => PasaDAC_D, SlowDAC1_SCLK => SlowDAC1_SCLK, SlowDAC2_SCLK => SlowDAC2_SCLK, SlowDAC1_LDACn => SlowDAC1_LDACn, SlowDAC2_LDACn => SlowDAC2_LDACn, SlowDAC_Din => SlowDAC_Din, SlowDAC1_FS => SlowDAC1_FS, SlowDAC2_FS => SlowDAC2_FS, SC_ADC_SDO => SC_ADC_SDO, SC_ADC_INTn => SC_ADC_INTn, SC_ADC_nCSStrt => SC_ADC_nCSStrt, SC_ADC_SCLK => SC_ADC_SCLK, SC_ADC_SDI => SC_ADC_SDI, SC_ADC_nCS => SC_ADC_nCS ); -- fpga2 dummy4bit <= (others => '-'); dummy10bit <= (others => '-'); top_fpga2: entity fpga2w.top port map( clk_osc_in => clk_gen, clk_osc_out => clk_fpga2, CLK_gen => clk_fpga2, -- the trap in the wafer tester WT_SER0_IN => DUT_SER0_IN_d, WT_SER0_OUT => DUT_SER0_OUT, WT_SER1_IN => DUT_SER1_IN_d, WT_SER1_OUT => DUT_SER1_OUT, WT_CLK => DUT_CLK, WT_PRE => DUT_PRE, -- rst_n => rst_n, -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n => open, DUT_IRQ_n => open, -- 3.3V LVCMOS signals - JTAG DUT_EN_JTAG => open, NI_EN_JTAG => open, DUT_TCK => open, DUT_TMS => open, DUT_TDI => open, DUT_TDO => 'H', -- LVDS signals - clock and pretrigger outputs DUT_CLK => dummy4bit, DUT_PRE => dummy4bit, -- LVDS signals - NI output port DUT_P4_D => dummy10bit, DUT_P4_STR => 'H', DUT_OA_CTR => 'H', DUT_P4_CTR => open, -- LVDS signals - SCSN interface DUT_SER0_IN => 'H', DUT_SER0_OUT => open, DUT_SER1_IN => 'H', DUT_SER1_OUT => open, -- LVCMOS signals DUT_SEBD => open, -- TST_PAD => open, -- to the 4 TRAPs -- LVCMOS signals NI_RST_n => open, NI_IRQ_n => open, -- 3.3V LVCMOS signals - JTAG NI_TCK_up => open, NI_TMS_up => open, NI_TDI_up => open, NI_TDO_up => 'H', NI_TCK_dn => open, NI_TMS_dn => open, NI_TDI_dn => open, NI_TDO_dn => 'H', -- LVDS signals NI_CLK_up => open, NI_CLK_dn => open, NI_PRE_up => open, NI_PRE_dn => open, -- LVDS signals - SCSN interface NI_SER0_IN => 'H', NI_SER0_OUT => open, NI_SER1_IN => 'H', NI_SER1_OUT => open, -- Link to the next FPGA controlling the ADCs/DACs -- LVCMOS signals - SCSN interface AD_SER0_IN => AD_SER0_IN_d, AD_SER0_OUT => AD_SER0_OUT, AD_SER1_IN => AD_SER1_IN_d, AD_SER1_OUT => AD_SER1_OUT, -- general purpose synchronization signals AD_SYNC_OUT => AD_SYNC_OUT, AD_SYNC_IN => AD_SYNC_IN_d, -- Uplink to PC -- LVDS signals - SCSN interface PC_SER0_IN => PC_SER0_IN_d, -- Logic0, -- PC_SER0_OUT => PC_SER0_OUT, -- open, -- -- -- PC_SER1_IN => PC_SER1_IN, -- PC_SER0_IN_d, -- PC_SER1_OUT => PC_SER1_OUT, -- PC_SER0_OUT, -- -- LVDS additional links, not used yet PC_0_IN => Logic0, PC_0_OUT => open, PC_1_IN => pretrig, PC_1_OUT => open ); adc_dac: adcs_dacs port map( VMCM_Shdwn_a => VMCM_Shdwn_a, VMCM_Shdwn_d => VMCM_Shdwn_d, PW_INCn => PW_INCn, PW_UDn => PW_UDn, PW_CSn => PW_CSn, MSply_ADC_nCS => MSply_ADC_nCS, MSply_ADC_INTn => MSply_ADC_INTn, MSply_ADC_nCSStrt => MSply_ADC_nCSStrt, MSply_ADC_SDI => MSply_ADC_SDI, MSply_ADC_SDO => MSply_ADC_SDO, MSply_ADC_SCLK => MSply_ADC_SCLK, -- DDS for the 3 ADC channels AD9854 DDS_FSK => DDS_FSK, DDS_ShKey => DDS_ShKey, DDS_CSn => DDS_CSn, DDS_SCLK => DDS_SCLK, DDS_UDCLK => DDS_UDCLK, DDS_SDI => DDS_SDI, DDS_SDO => DDS_SDO, DDS_IORST => DDS_IORST, DDS_MRST => DDS_MRST, DDS_MCLK => DDS_MCLK, -- PASA ADC ADS5221 PAADC_D => PAADC_D, PAADC_OVR => PAADC_OVR, PAADC_CLK => PAADC_CLK, PAADC_Msel => PAADC_Msel, PAADC_STDP => PAADC_STDP, PAADC_MuxnRS => PAADC_MuxnRS, PAADC_MuxA => PAADC_MuxA, -- PASA DACs AD9744 PasaDAC1_CLK => PasaDAC1_CLK, PasaDAC2_CLK => PasaDAC2_CLK, PasaDAC_Sleep => PasaDAC_Sleep, PasaDAC_D => PasaDAC_D, -- Slow DAC 2xTLV5630 SlowDAC1_SCLK => SlowDAC1_SCLK, SlowDAC2_SCLK => SlowDAC2_SCLK, SlowDAC1_LDACn => SlowDAC1_LDACn, SlowDAC2_LDACn => SlowDAC2_LDACn, SlowDAC_Din => SlowDAC_Din, SlowDAC1_FS => SlowDAC1_FS, SlowDAC2_FS => SlowDAC2_FS, -- SC ADC TLV2548 SC_ADC_SDO => SC_ADC_SDO, SC_ADC_INTn => SC_ADC_INTn, SC_ADC_nCSStrt => SC_ADC_nCSStrt, SC_ADC_SCLK => SC_ADC_SCLK, SC_ADC_SDI => SC_ADC_SDI, SC_ADC_nCS => SC_ADC_nCS ); trapchips: trap port map( -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n => DUT_RST_n, -- LVDS signals - clock and pretrigger outputs DUT_CLK => DUT_CLK_d, DUT_PRE => DUT_PRE_d, -- LVDS signals - NI output port DUT_P4_D => DUT_P4_D, DUT_P4_STR => DUT_P4_STR, DUT_P4_CTR => DUT_P4_CTR_d, -- LVDS signals - SCSN interface DUT_SER0_IN => DUT_SER0_IN, DUT_SER0_OUT => DUT_SER0_OUT_d, DUT_SER1_IN => DUT_SER1_IN, DUT_SER1_OUT => DUT_SER1_OUT_d, SEBD => SEBD, PA_SCLK => PA_SCLK, PA_SDAT => PA_SDAT, PA_SSTR => PA_SSTR ); si: ser_int -- SCSN feed (our master mockup) generic map( wait_delay => 200, init_delay => 5000 ) port map( reset_n => rst_n, clk => DUT_CLK, -- 120MHz ready => '0', ser0din => PC_SER0_OUT_d, ser0dout => PC_SER0_IN, PRE => pretrig ); rst_n <= '0' after 0 ns, '1' after 15 ns; -- '0' after 2500 ns, -- '1' after 3500 ns, -- '0' after 4500 ns, -- '1' after 5500 ns; end;