LIBRARY IEEE; library fpga1,fpga2; USE IEEE.STD_LOGIC_1164.all; entity top_tb is generic( period_time : time := 10 ns; -- or 8.32 ns bdelay : time := 3 ns; -- board delay L0_timec : Integer := 80; L1_timec : Integer := 512+48+24; L2_timec : Integer := 700 ); end top_tb; architecture struct of top_tb is component traps is port ( -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n : in std_logic; DUT_IRQ_n : in std_logic; -- 3.3V LVCMOS signals - JTAG DUT_EN_JTAG : in std_logic; -- out_rng NI_EN_JTAG : in std_logic_vector(3 downto 0); -- out_rng DUT_TCK : in std_logic; DUT_TMS : in std_logic; DUT_TDI : in std_logic; DUT_TDO : out std_logic; -- LVDS signals - clock and pretrigger outputs DUT_CLK : out std_logic_vector(3 downto 0); DUT_PRE : out std_logic_vector(3 downto 0); -- LVDS signals - NI output port DUT_P4_D : out std_logic_vector(9 downto 0); DUT_P4_STR : out std_logic; DUT_OA_CTR : out std_logic; DUT_P4_CTR : in std_logic; -- LVDS signals - SCSN interface DUT_SER0_IN : out std_logic; DUT_SER0_OUT : in std_logic; DUT_SER1_IN : out std_logic; DUT_SER1_OUT : in std_logic; -- LVCMOS signals DUT_SEBD : inout std_logic_vector( 2 downto 0); -- to the 4 TRAPs -- LVCMOS signals NI_RST_n : in std_logic; NI_IRQ_n : in std_logic; -- 3.3V LVCMOS signals - JTAG NI_TCK_up : in std_logic; NI_TMS_up : in std_logic; NI_TDI_up : in std_logic; NI_TDO_up : out std_logic; NI_TCK_dn : in std_logic; NI_TMS_dn : in std_logic; NI_TDI_dn : in std_logic; NI_TDO_dn : out std_logic; -- LVDS signals NI_CLK_up : in std_logic; NI_CLK_dn : in std_logic; NI_PRE_up : in std_logic; NI_PRE_dn : in std_logic; -- LVDS signals - SCSN interface NI_SER0_IN : out std_logic; NI_SER0_OUT : in std_logic; NI_SER1_IN : out std_logic; NI_SER1_OUT : in std_logic ); end component; component adcs_dacs is port ( VMCM_Shdwn_a : in std_logic; VMCM_Shdwn_d : in std_logic; PW_INCn : in std_logic_vector(3 downto 0); PW_UDn : in std_logic_vector(3 downto 0); PW_CSn : in std_logic_vector(3 downto 0); MSply_ADC_nCS : in std_logic; MSply_ADC_INTn : out std_logic; MSply_ADC_nCSStrt : in std_logic; MSply_ADC_SDI : in std_logic; MSply_ADC_SDO : out std_logic; MSply_ADC_SCLK : in std_logic; -- DDS for the 3 ADC channels AD9854 DDS_FSK : in std_logic; DDS_ShKey : in std_logic; DDS_CSn : in std_logic; DDS_SCLK : in std_logic; DDS_UDCLK : in std_logic; DDS_SDI : in std_logic; DDS_SDO : out std_logic; -- ?? DDS_IORST : in std_logic; DDS_MRST : in std_logic; DDS_MCLK : in std_logic; -- PASA ADC ADS5221 PAADC_D : out std_logic_vector(11 downto 0); PAADC_OVR : out std_logic; PAADC_CLK : in std_logic; PAADC_Msel : in std_logic; PAADC_STDP : in std_logic; PAADC_MuxnRS : in std_logic; PAADC_MuxA : in std_logic_vector( 1 downto 0); -- PASA DACs AD9744 PasaDAC1_CLK : in std_logic; PasaDAC2_CLK : in std_logic; PasaDAC_Sleep : in std_logic; PasaDAC_D : in std_logic_vector(13 downto 0); -- Slow DAC 2xTLV5630 SlowDAC1_SCLK : in std_logic; SlowDAC2_SCLK : in std_logic; SlowDAC1_LDACn : in std_logic; SlowDAC2_LDACn : in std_logic; SlowDAC_Din : in std_logic; SlowDAC1_FS : in std_logic; SlowDAC2_FS : in std_logic; -- SC ADC TLV2548 SC_ADC_SDO : out std_logic; SC_ADC_INTn : out std_logic; SC_ADC_nCSStrt : in std_logic; SC_ADC_SCLK : in std_logic; SC_ADC_SDI : in std_logic; SC_ADC_nCS : in std_logic ); end component; component ser_int -- the serial master generic ( wait_delay : integer := 100; init_delay : integer := 4095 ); port ( reset_n : in std_logic; clk : in std_logic; ready : in std_logic; ser0din : in std_logic; ser0dout : out std_logic; PRE : out std_logic); end component; ---------------------------------------------------- -- top_pad signals ---------------------------------------------------- signal clk_gen : STD_LOGIC := '0'; signal rst_n : STD_LOGIC := '1'; signal pretrig : std_logic; -- FPGA 1 -- ADCs and DACs signal VMCM_Shdwn_a : std_logic; signal VMCM_Shdwn_d : std_logic; signal MSply_ADC_nCS : std_logic; signal MSply_ADC_INTn : std_logic; signal MSply_ADC_nCSStrt : std_logic; signal MSply_ADC_SDI : std_logic; signal MSply_ADC_SDO : std_logic; signal MSply_ADC_SCLK : std_logic; -- DDS for the 3 ADC channels AD9854 signal DDS_FSK : std_logic; signal DDS_ShKey : std_logic; signal DDS_CSn : std_logic; signal DDS_SCLK : std_logic; signal DDS_UDCLK : std_logic; signal DDS_SDI : std_logic; signal DDS_SDO : std_logic; -- ?? signal DDS_IORST : std_logic; signal DDS_MRST : std_logic; signal DDS_MCLK : std_logic; -- PASA ADC ADS5221 signal PAADC_D : std_logic_vector(11 downto 0); signal PAADC_OVR : std_logic; signal PAADC_CLK : std_logic; signal PAADC_Msel : std_logic; signal PAADC_STDP : std_logic; signal PAADC_MuxnRS : std_logic; signal PAADC_MuxA : std_logic_vector(1 downto 0); -- PASA DACs AD9744 signal PasaDAC1_CLK : std_logic; signal PasaDAC2_CLK : std_logic; signal PasaDAC_Sleep : std_logic; signal PasaDAC_D : std_logic_vector(13 downto 0); -- Slow DAC 2xTLV5630 signal SlowDAC1_SCLK : std_logic; signal SlowDAC2_SCLK : std_logic; signal SlowDAC1_LDACn : std_logic; signal SlowDAC2_LDACn : std_logic; signal SlowDAC_Din : std_logic; signal SlowDAC1_FS : std_logic; signal SlowDAC2_FS : std_logic; -- SC ADC TLV2548 signal SC_ADC_SDO : std_logic; signal SC_ADC_INTn : std_logic; signal SC_ADC_nCSStrt : std_logic; signal SC_ADC_SCLK : std_logic; signal SC_ADC_SDI : std_logic; signal SC_ADC_nCS : std_logic; -- FPGA 2 signal DUT_RST_n : std_logic; signal DUT_IRQ_n : std_logic; -- 3.3V LVCMOS signals - JTAG signal DUT_EN_JTAG : std_logic; -- out_rng signal NI_EN_JTAG : std_logic_vector(3 downto 0); -- out_rng signal DUT_TCK : std_logic; signal DUT_TMS : std_logic; signal DUT_TDI : std_logic; signal DUT_TDO : std_logic; -- LVDS signals - clock and pretrigger outputs signal DUT_CLK : std_logic_vector(3 downto 0); signal DUT_PRE : std_logic_vector(3 downto 0); signal DUT_CLK_d : std_logic_vector(3 downto 0); signal DUT_PRE_d : std_logic_vector(3 downto 0); -- LVDS signals - NI output port signal DUT_P4_D : std_logic_vector(9 downto 0); signal DUT_P4_STR : std_logic; signal DUT_OA_CTR : std_logic; signal DUT_P4_CTR : std_logic; signal DUT_P4_D_d : std_logic_vector(9 downto 0); signal DUT_P4_STR_d : std_logic; signal DUT_OA_CTR_d : std_logic; signal DUT_P4_CTR_d : std_logic; -- LVDS signals - SCSN interface signal DUT_SER0_IN : std_logic; signal DUT_SER0_OUT : std_logic; signal DUT_SER1_IN : std_logic; signal DUT_SER1_OUT : std_logic; signal DUT_SER0_IN_d : std_logic; signal DUT_SER0_OUT_d : std_logic; signal DUT_SER1_IN_d : std_logic; signal DUT_SER1_OUT_d : std_logic; -- LVCMOS signals signal DUT_SEBD : std_logic_vector( 2 downto 0); signal TST_PAD : std_logic_vector( 3 downto 0); signal PW_INCn : std_logic_vector( 3 downto 0); signal PW_UDn : std_logic_vector( 3 downto 0); signal PW_CSn : std_logic_vector( 3 downto 0); -- LVCMOS signals signal NI_RST_n : std_logic; signal NI_IRQ_n : std_logic; -- 3.3V LVCMOS signals - JTAG signal NI_TCK_up : std_logic; signal NI_TMS_up : std_logic; signal NI_TDI_up : std_logic; signal NI_TDO_up : std_logic; signal NI_TCK_dn : std_logic; signal NI_TMS_dn : std_logic; signal NI_TDI_dn : std_logic; signal NI_TDO_dn : std_logic; -- LVDS signals signal NI_CLK_up : std_logic; signal NI_CLK_dn : std_logic; signal NI_PRE_up : std_logic; signal NI_PRE_dn : std_logic; -- LVDS signals - SCSN interface signal NI_SER0_IN : std_logic; signal NI_SER0_OUT : std_logic; signal NI_SER1_IN : std_logic; signal NI_SER1_OUT : std_logic; signal NI_SER0_IN_d : std_logic; signal NI_SER0_OUT_d : std_logic; signal NI_SER1_IN_d : std_logic; signal NI_SER1_OUT_d : std_logic; -- LVCMOS signals - SCSN interface signal AD_SER0_IN : std_logic; signal AD_SER0_OUT : std_logic; signal AD_SER1_IN : std_logic; signal AD_SER1_OUT : std_logic; signal AD_SER0_IN_d : std_logic; signal AD_SER0_OUT_d : std_logic; signal AD_SER1_IN_d : std_logic; signal AD_SER1_OUT_d : std_logic; -- general purpose synchronization signals signal AD_SYNC_OUT : std_logic_vector(1 downto 0); signal AD_SYNC_IN : std_logic_vector(1 downto 0); signal AD_SYNC_OUT_d : std_logic_vector(1 downto 0); signal AD_SYNC_IN_d : std_logic_vector(1 downto 0); -- LVDS signals - SCSN interface signal PC_SER0_IN : std_logic; signal PC_SER0_OUT : std_logic; signal PC_SER1_IN : std_logic; signal PC_SER1_OUT : std_logic; signal PC_SER0_IN_d : std_logic; signal PC_SER0_OUT_d : std_logic; -- LVDS additional links, not used yet signal PC_0_IN : std_logic; signal PC_0_OUT : std_logic; signal PC_1_IN : std_logic; signal PC_1_OUT : std_logic; signal clk_fpga2 : std_logic; signal Logic0 : std_logic; signal DUT_rst_fpga_n : std_logic; signal NI_rst_fpga_n : std_logic; signal WT_P4D : std_logic_vector(9 downto 0); begin clk_gen <= not clk_gen after 2*period_time; Logic0 <= '0'; -- fpga1 DUT_SER0_OUT_d <= transport DUT_SER0_OUT after bdelay; DUT_SER0_IN_d <= transport DUT_SER0_IN after bdelay; DUT_SER1_OUT_d <= transport DUT_SER1_OUT after bdelay; DUT_SER1_IN_d <= transport DUT_SER1_IN after bdelay; AD_SER0_OUT_d <= transport AD_SER0_OUT after bdelay; AD_SER1_OUT_d <= transport AD_SER0_OUT after bdelay; AD_SER0_IN_d <= transport AD_SER0_IN after bdelay; AD_SER1_IN_d <= transport AD_SER0_IN after bdelay; PC_SER0_OUT_d <= transport PC_SER0_OUT after bdelay; PC_SER0_IN_d <= transport PC_SER0_IN after bdelay; NI_SER0_OUT_d <= transport NI_SER0_OUT after bdelay; NI_SER1_OUT_d <= transport NI_SER1_OUT after bdelay; NI_SER0_IN_d <= transport NI_SER0_IN after bdelay; NI_SER1_IN_d <= transport NI_SER1_IN after bdelay; AD_SYNC_OUT_d <= transport AD_SYNC_OUT after bdelay; AD_SYNC_IN_d <= transport AD_SYNC_IN after bdelay; DUT_P4_D_d <= transport DUT_P4_D after bdelay; DUT_P4_STR_d <= transport DUT_P4_STR after bdelay; DUT_OA_CTR_d <= transport DUT_OA_CTR after bdelay; DUT_P4_CTR_d <= transport DUT_P4_CTR after bdelay; DUT_CLK_d <= transport DUT_CLK after bdelay; DUT_PRE_d <= transport DUT_PRE after bdelay; DUT_rst_n <= rst_n and DUT_rst_fpga_n; NI_rst_n <= rst_n and NI_rst_fpga_n; DUT_rst_fpga_n <= 'H'; DUT_IRQ_n <= 'H'; WT_P4D <= (others => '0'); top_fpga1: entity fpga1.top generic map(wafer_test => 0) port map( CLK_gen => CLK_gen, -- rst_n => rst_n, WT_STR => '0', WT_P4D => WT_P4D, WT_CTR => open, -- Link to the other FPGA -- LVCMOS signals - SCSN interface SER0_IN => AD_SER0_OUT_d, SER0_OUT => AD_SER0_IN, SER1_IN => AD_SER1_OUT_d, SER1_OUT => AD_SER1_IN, -- general purpose synchronization signals AD_SYNC_OUT => AD_SYNC_IN, AD_SYNC_IN => AD_SYNC_OUT_d, -- ADCs and DACs VMCM_Shdwn_a => VMCM_Shdwn_a, VMCM_Shdwn_d => VMCM_Shdwn_d, PW_INCn => PW_INCn, PW_UDn => PW_UDn, PW_CSn => PW_CSn, MSply_ADC_nCS => MSply_ADC_nCS, MSply_ADC_INTn => MSply_ADC_INTn, MSply_ADC_nCSStrt => MSply_ADC_nCSStrt, MSply_ADC_SDI => MSply_ADC_SDI, MSply_ADC_SDO => MSply_ADC_SDO, MSply_ADC_SCLK => MSply_ADC_SCLK, -- DDS for the 3 ADC channels AD9854 DDS_FSK => DDS_FSK, DDS_ShKey => DDS_ShKey, DDS_CSn => DDS_CSn, DDS_SCLK => DDS_SCLK, DDS_UDCLK => DDS_UDCLK, DDS_SDI => DDS_SDI, DDS_SDO => DDS_SDO, DDS_IORST => DDS_IORST, DDS_MRST => DDS_MRST, DDS_MCLK => DDS_MCLK, -- PASA ADC ADS5221 PAADC_D => PAADC_D, PAADC_OVR => PAADC_OVR, PAADC_CLK => PAADC_CLK, PAADC_Msel => PAADC_Msel, PAADC_STDP => PAADC_STDP, PAADC_MuxnRS => PAADC_MuxnRS, PAADC_MuxA => PAADC_MuxA, -- PASA DACs AD9744 PasaDAC1_CLK => PasaDAC1_CLK, PasaDAC2_CLK => PasaDAC2_CLK, PasaDAC_Sleep => PasaDAC_Sleep, PasaDAC_D => PasaDAC_D, SlowDAC1_SCLK => SlowDAC1_SCLK, SlowDAC2_SCLK => SlowDAC2_SCLK, SlowDAC1_LDACn => SlowDAC1_LDACn, SlowDAC2_LDACn => SlowDAC2_LDACn, SlowDAC_Din => SlowDAC_Din, SlowDAC1_FS => SlowDAC1_FS, SlowDAC2_FS => SlowDAC2_FS, SC_ADC_SDO => SC_ADC_SDO, SC_ADC_INTn => SC_ADC_INTn, SC_ADC_nCSStrt => SC_ADC_nCSStrt, SC_ADC_SCLK => SC_ADC_SCLK, SC_ADC_SDI => SC_ADC_SDI, SC_ADC_nCS => SC_ADC_nCS ); -- fpga2 TST_PAD <= "1001"; top_fpga2: entity fpga2.top port map( clk_osc_in => clk_gen, clk_osc_out => clk_fpga2, CLK_gen => clk_fpga2, -- rst_n => rst_n, -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n => DUT_RST_fpga_n, DUT_IRQ_n => DUT_IRQ_n, -- 3.3V LVCMOS signals - JTAG DUT_EN_JTAG => DUT_EN_JTAG, NI_EN_JTAG => NI_EN_JTAG, DUT_TCK => DUT_TCK, DUT_TMS => DUT_TMS, DUT_TDI => DUT_TDI, DUT_TDO => DUT_TDO, -- LVDS signals - clock and pretrigger outputs DUT_CLK => DUT_CLK, DUT_PRE => DUT_PRE, -- LVDS signals - NI output port DUT_P4_D => DUT_P4_D_d, DUT_P4_STR => DUT_P4_STR_d, DUT_OA_CTR => DUT_OA_CTR_d, DUT_P4_CTR => DUT_P4_CTR, -- LVDS signals - SCSN interface DUT_SER0_IN => DUT_SER0_IN_d, DUT_SER0_OUT => DUT_SER0_OUT, DUT_SER1_IN => DUT_SER1_IN_d, DUT_SER1_OUT => DUT_SER1_OUT, -- LVCMOS signals DUT_SEBD => DUT_SEBD, TST_PAD => TST_PAD, -- to the 4 TRAPs -- LVCMOS signals NI_RST_n => NI_RST_fpga_n, NI_IRQ_n => NI_IRQ_n, -- 3.3V LVCMOS signals - JTAG NI_TCK_up => NI_TCK_up, NI_TMS_up => NI_TMS_up, NI_TDI_up => NI_TDI_up, NI_TDO_up => NI_TDO_up, NI_TCK_dn => NI_TCK_dn, NI_TMS_dn => NI_TMS_dn, NI_TDI_dn => NI_TDI_dn, NI_TDO_dn => NI_TDO_dn, -- LVDS signals NI_CLK_up => NI_CLK_up, NI_CLK_dn => NI_CLK_dn, NI_PRE_up => NI_PRE_up, NI_PRE_dn => NI_PRE_dn, -- LVDS signals - SCSN interface NI_SER0_IN => NI_SER0_IN_d, NI_SER0_OUT => NI_SER0_OUT, NI_SER1_IN => NI_SER1_IN_d, NI_SER1_OUT => NI_SER1_OUT, -- Link to the next FPGA controlling the ADCs/DACs -- LVCMOS signals - SCSN interface AD_SER0_IN => AD_SER0_IN_d, AD_SER0_OUT => AD_SER0_OUT, AD_SER1_IN => AD_SER1_IN_d, AD_SER1_OUT => AD_SER1_OUT, -- general purpose synchronization signals AD_SYNC_OUT => AD_SYNC_OUT, AD_SYNC_IN => AD_SYNC_IN_d, -- Uplink to PC -- LVDS signals - SCSN interface PC_SER0_IN => PC_SER0_IN_d, -- Logic0, -- PC_SER0_OUT => PC_SER0_OUT, -- open, -- -- -- PC_SER1_IN => Logic0, -- PC_SER0_IN_d, -- PC_SER1_OUT => open, -- PC_SER0_OUT, -- -- LVDS additional links, not used yet PC_0_IN => pretrig, PC_0_OUT => open, PC_1_IN => Logic0, PC_1_OUT => open ); adc_dac: adcs_dacs port map( VMCM_Shdwn_a => VMCM_Shdwn_a, VMCM_Shdwn_d => VMCM_Shdwn_d, PW_INCn => PW_INCn, PW_UDn => PW_UDn, PW_CSn => PW_CSn, MSply_ADC_nCS => MSply_ADC_nCS, MSply_ADC_INTn => MSply_ADC_INTn, MSply_ADC_nCSStrt => MSply_ADC_nCSStrt, MSply_ADC_SDI => MSply_ADC_SDI, MSply_ADC_SDO => MSply_ADC_SDO, MSply_ADC_SCLK => MSply_ADC_SCLK, -- DDS for the 3 ADC channels AD9854 DDS_FSK => DDS_FSK, DDS_ShKey => DDS_ShKey, DDS_CSn => DDS_CSn, DDS_SCLK => DDS_SCLK, DDS_UDCLK => DDS_UDCLK, DDS_SDI => DDS_SDI, DDS_SDO => DDS_SDO, DDS_IORST => DDS_IORST, DDS_MRST => DDS_MRST, DDS_MCLK => DDS_MCLK, -- PASA ADC ADS5221 PAADC_D => PAADC_D, PAADC_OVR => PAADC_OVR, PAADC_CLK => PAADC_CLK, PAADC_Msel => PAADC_Msel, PAADC_STDP => PAADC_STDP, PAADC_MuxnRS => PAADC_MuxnRS, PAADC_MuxA => PAADC_MuxA, -- PASA DACs AD9744 PasaDAC1_CLK => PasaDAC1_CLK, PasaDAC2_CLK => PasaDAC2_CLK, PasaDAC_Sleep => PasaDAC_Sleep, PasaDAC_D => PasaDAC_D, -- Slow DAC 2xTLV5630 SlowDAC1_SCLK => SlowDAC1_SCLK, SlowDAC2_SCLK => SlowDAC2_SCLK, SlowDAC1_LDACn => SlowDAC1_LDACn, SlowDAC2_LDACn => SlowDAC2_LDACn, SlowDAC_Din => SlowDAC_Din, SlowDAC1_FS => SlowDAC1_FS, SlowDAC2_FS => SlowDAC2_FS, -- SC ADC TLV2548 SC_ADC_SDO => SC_ADC_SDO, SC_ADC_INTn => SC_ADC_INTn, SC_ADC_nCSStrt => SC_ADC_nCSStrt, SC_ADC_SCLK => SC_ADC_SCLK, SC_ADC_SDI => SC_ADC_SDI, SC_ADC_nCS => SC_ADC_nCS ); trapchips: traps port map( -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n => DUT_RST_n, DUT_IRQ_n => DUT_IRQ_n, -- 3.3V LVCMOS signals - JTAG DUT_EN_JTAG => DUT_EN_JTAG, NI_EN_JTAG => NI_EN_JTAG, DUT_TCK => DUT_TCK, DUT_TMS => DUT_TMS, DUT_TDI => DUT_TDI, DUT_TDO => DUT_TDO, -- LVDS signals - clock and pretrigger outputs DUT_CLK => DUT_CLK, DUT_PRE => DUT_PRE, -- LVDS signals - NI output port DUT_P4_D => DUT_P4_D, DUT_P4_STR => DUT_P4_STR, DUT_OA_CTR => DUT_OA_CTR, DUT_P4_CTR => DUT_P4_CTR, -- LVDS signals - SCSN interface DUT_SER0_IN => DUT_SER0_IN, DUT_SER0_OUT => DUT_SER0_OUT, DUT_SER1_IN => DUT_SER1_IN, DUT_SER1_OUT => DUT_SER1_OUT, -- LVCMOS signals DUT_SEBD => DUT_SEBD, -- to the 4 TRAPs -- LVCMOS signals NI_RST_n => NI_RST_n, NI_IRQ_n => NI_IRQ_n, -- 3.3V LVCMOS signals - JTAG NI_TCK_up => NI_TCK_up, NI_TMS_up => NI_TMS_up, NI_TDI_up => NI_TDI_up, NI_TDO_up => NI_TDO_up, NI_TCK_dn => NI_TCK_dn, NI_TMS_dn => NI_TMS_dn, NI_TDI_dn => NI_TDI_dn, NI_TDO_dn => NI_TDO_dn, -- LVDS signals NI_CLK_up => NI_CLK_up, NI_CLK_dn => NI_CLK_dn, NI_PRE_up => NI_PRE_up, NI_PRE_dn => NI_PRE_dn, -- LVDS signals - SCSN interface NI_SER0_IN => NI_SER0_IN, NI_SER0_OUT => NI_SER0_OUT, NI_SER1_IN => NI_SER1_IN, NI_SER1_OUT => NI_SER1_OUT ); si: ser_int -- SCSN feed (our master mockup) generic map( wait_delay => 200, init_delay => 5000 ) port map( reset_n => rst_n, clk => NI_CLK_up, -- 120MHz ready => '0', ser0din => PC_SER0_OUT_d, ser0dout => PC_SER0_IN, PRE => pretrig ); rst_n <= '0' after 0 ns, '1' after 15 ns; -- '0' after 2500 ns, -- '1' after 3500 ns, -- '0' after 4500 ns, -- '1' after 5500 ns; end;