library ieee; --library trap2; use std.textio.all; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.std_logic_unsigned.all; -- Serial interface simulation -- last modified: 12:30 / 09 Oct 2003 / F.Rettig entity ser_int_mast is port ( reset_n : in std_logic; clk : in std_logic; d0_we : in std_logic; d0_send_start : in std_logic; addr0_s : in std_logic_vector(15 downto 0); data0_s : in std_logic_vector(31 downto 0); command0_s : in std_logic_vector( 3 downto 0); mcmaddr0_s : in std_logic_vector( 6 downto 0); d1_we : in std_logic; d1_send_start : in std_logic; addr1_s : in std_logic_vector(15 downto 0); data1_s : in std_logic_vector(31 downto 0); command1_s : in std_logic_vector( 3 downto 0); mcmaddr1_s : in std_logic_vector( 6 downto 0); d0_received : out std_logic; d0_recieve_error : out std_logic; addr0_r : out std_logic_vector(15 downto 0); data0_r : out std_logic_vector(31 downto 0); command0_r : out std_logic_vector( 3 downto 0); mcmaddr0_r : out std_logic_vector( 6 downto 0); mcmhop0_r : out std_logic_vector( 7 downto 0); d0_buffer_ready : out std_logic; d1_recieved : out std_logic; d1_recieve_error : out std_logic; addr1_r : out std_logic_vector(15 downto 0); data1_r : out std_logic_vector(31 downto 0); command1_r : out std_logic_vector( 3 downto 0); mcmaddr1_r : out std_logic_vector( 6 downto 0); mcmhop1_r : out std_logic_vector( 7 downto 0); d1_buffer_ready : out std_logic; ser0din : in std_logic; ser0dout : out std_logic; ser1din : in std_logic; ser1dout : out std_logic ); end ser_int_mast; architecture a of ser_int_mast is -------------------------------------------------- -- internal signals -------------------------------------------------- signal d0_data_to_send : std_logic_vector(68 downto 0); signal d0_revieved_data : std_logic_vector(68 downto 0); signal d0_recv_buffer_half : std_logic; signal d1_data_to_send : std_logic_vector(68 downto 0); signal d1_revieved_data : std_logic_vector(68 downto 0); signal d1_recv_buffer_half : std_logic; signal bridge : std_logic; COMPONENT mcm_nw_dll is generic (timing_count_range : integer := 7; timing_recv_on : integer := 2; stuff_length : integer := 4; timing_sleep_length : integer := 63; BUFSIZ : integer := 69; COUNTER : integer := 7); port( -- Signals from/to phyiscal layer : serial data d0_fr_pl : in std_logic; d0_to_pl : out std_logic; d1_fr_pl : in std_logic; d1_to_pl : out std_logic; -- Signals to Network Layer (recv) d0_to_nwl : out std_logic_vector(BUFSIZ-1 downto 0); s0_to_nwl : out std_logic ; buf0_half : out std_logic ; buf0_err : out std_logic ; d1_to_nwl : out std_logic_vector(BUFSIZ-1 downto 0); s1_to_nwl : out std_logic ; buf1_half : out std_logic ; buf1_err : out std_logic ; -- Signals from Network Layer (send) d0_fr_nwl : in std_logic_vector(BUFSIZ-1 downto 0); d0_we : in std_logic; d0_send : in std_logic; d0_buffer_ready : out std_logic; d1_fr_nwl : in std_logic_vector(BUFSIZ-1 downto 0); d1_we : in std_logic; d1_send : in std_logic; d1_buffer_ready : out std_logic; -- X-bar data paths bridge : in std_logic; reset_n : in std_logic; clk_buf : in std_logic; clk : in std_logic ); END COMPONENT; begin nw_dll: mcm_nw_dll generic map( timing_count_range => 4, -- must be >2; default : 7 timing_recv_on => 1, -- < timing_count_range - 3; -- default : 2 stuff_length => 7, -- default : 4 timing_sleep_length=> 63) -- default : 144 port map( -- ring 0 d0_fr_pl => ser0din , d0_to_pl => ser0dout, buf0_half => d0_recv_buffer_half, s0_to_nwl => d0_received, buf0_err => d0_recieve_error, d0_to_nwl => d0_revieved_data, d0_fr_nwl => d0_data_to_send, d0_we => d0_we, d0_send => d0_send_start, d0_buffer_ready => d0_buffer_ready, -- ring 1 d1_fr_pl => ser1din , d1_to_pl => ser1dout, buf1_half => d1_recv_buffer_half, s1_to_nwl => d1_recieved, buf1_err => d1_recieve_error, d1_to_nwl => d1_revieved_data, d1_fr_nwl => d1_data_to_send, d1_we => d1_we, d1_send => d1_send_start, d1_buffer_ready => d1_buffer_ready, bridge => bridge, reset_n => reset_n, clk_buf => clk, clk => clk ); bridge <= '0'; -- ser1din <= '0'; -- d1_data_to_send <= (others => '0'); -- d1_we <= '0'; -- d1_send_start <= '0'; -- d1_we <= '0'; -- data1_s <= (others => '0'); -- addr1_s <= (others => '0'); -- command1_s <= (others => '0'); -- mcmaddr1_s <= (0=>'1', others => '0'); gen0: for i in 0 to 31 generate d0_data_to_send(31-i) <= data0_s(i); d1_data_to_send(31-i) <= data1_s(i); data0_r(i) <= d0_revieved_data(31-i); data1_r(i) <= d1_revieved_data(31-i); end generate; gen1: for i in 0 to 15 generate d0_data_to_send(48-i) <= addr0_s(i); d1_data_to_send(48-i) <= addr1_s(i); addr0_r(i) <= d0_revieved_data(48-i); addr1_r(i) <= d1_revieved_data(48-i); end generate; gen2: for i in 0 to 3 generate d0_data_to_send(52-i) <= command0_s(i); d1_data_to_send(52-i) <= command1_s(i); command0_r(i) <= d0_revieved_data(52-i); command1_r(i) <= d1_revieved_data(52-i); end generate; gen3: for i in 0 to 6 generate d0_data_to_send(68-i) <= mcmaddr0_s(i); d1_data_to_send(68-i) <= mcmaddr1_s(i); mcmaddr0_r(i) <= d0_revieved_data(68-i); mcmaddr1_r(i) <= d1_revieved_data(68-i); end generate; gen4: for i in 0 to 7 generate mcmhop0_r(i) <= d0_revieved_data(60-i); mcmhop1_r(i) <= d1_revieved_data(60-i); end generate; d0_data_to_send(32) <= '0'; d1_data_to_send(32) <= '0'; d0_data_to_send(61) <= '1'; d1_data_to_send(61) <= '1'; d0_data_to_send(60 downto 53) <= (others => '0'); d1_data_to_send(60 downto 53) <= (others => '0'); end;