library ieee; --library trap2; use std.textio.all; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.std_logic_unsigned.all; -- Serial interface simulation -- last modified: 12:30 / 09 Oct 2003 / F.Rettig entity ser_int is generic ( wait_delay : integer := 100; init_delay : integer := 4095 ); port ( reset_n : in std_logic; clk : in std_logic; ready : in std_logic; ser0din : in std_logic; ser0dout : out std_logic; pre : out std_logic ); end ser_int; architecture a of ser_int is -------------------------------------------------- -- internal signals -------------------------------------------------- signal ser1dout, ser1din : std_logic; signal next_frame : std_logic; file ser_inp : text OPEN READ_MODE is "./DATA/sc_send.dat"; file ser_out : text OPEN WRITE_MODE is "./DATA/sc_recv.dat"; TYPE send_state_type IS (idle, wait_state, read_file, check_read, start_send, wait_finish, enddata ); signal current_state0, next_state0 : send_state_type; signal d0_received,d0_recieve_error,d0_we, d0_send_start,d0_buffer_ready : std_logic; signal d1_recieved,d1_recieve_error,d1_we, d1_send_start,d1_buffer_ready : std_logic; constant fifo_depth : Integer := 4; type data_mat is array(0 to fifo_depth-1) of std_logic_vector(31 downto 0); type addr_mat is array(0 to fifo_depth-1) of std_logic_vector(15 downto 0); signal wpointer, rpointer : Integer range 0 to fifo_depth-1; signal data0h : data_mat; signal addr0h : addr_mat; signal re_fifo, we_fifo : std_logic; signal data0_s,data1_s : std_logic_vector(31 downto 0); signal data0_s_old : std_logic_vector(31 downto 0); signal addr0_s_old : std_logic_vector(15 downto 0); signal addr0_s,addr1_s : std_logic_vector(15 downto 0); signal command0_s,command1_s : std_logic_vector(3 downto 0); signal mcmaddr0_s,mcmaddr1_s : std_logic_vector(6 downto 0); signal data0_r : std_logic_vector(31 downto 0); signal addr0_r : std_logic_vector(15 downto 0); signal command0_r : std_logic_vector(3 downto 0); signal mcmaddr0_r : std_logic_vector(6 downto 0); signal wait_dly : integer; signal wait_reset : integer; signal wait_delay_plus : integer := 0; signal reset_out_n : std_logic; signal PESel : std_logic; signal PEFunc : std_logic_vector(2 downto 0); signal end_mark : boolean; signal ready_old : std_logic; signal ready_new : std_logic; signal stop_wait : std_logic; -------------------------------------------------- -- components -------------------------------------------------- component ser_int_mast is port ( reset_n : in std_logic; clk : in std_logic; d0_we : in std_logic; d0_send_start : in std_logic; addr0_s : in std_logic_vector(15 downto 0); data0_s : in std_logic_vector(31 downto 0); command0_s : in std_logic_vector( 3 downto 0); mcmaddr0_s : in std_logic_vector( 6 downto 0); d1_we : in std_logic; d1_send_start : in std_logic; addr1_s : in std_logic_vector(15 downto 0); data1_s : in std_logic_vector(31 downto 0); command1_s : in std_logic_vector( 3 downto 0); mcmaddr1_s : in std_logic_vector( 6 downto 0); d0_received : out std_logic; d0_recieve_error : out std_logic; addr0_r : out std_logic_vector(15 downto 0); data0_r : out std_logic_vector(31 downto 0); command0_r : out std_logic_vector( 3 downto 0); mcmaddr0_r : out std_logic_vector( 6 downto 0); mcmhop0_r : out std_logic_vector( 7 downto 0); d0_buffer_ready : out std_logic; d1_recieved : out std_logic; d1_recieve_error : out std_logic; addr1_r : out std_logic_vector(15 downto 0); data1_r : out std_logic_vector(31 downto 0); command1_r : out std_logic_vector( 3 downto 0); mcmaddr1_r : out std_logic_vector( 6 downto 0); mcmhop1_r : out std_logic_vector( 7 downto 0); d1_buffer_ready : out std_logic; ser0din : in std_logic; ser0dout : out std_logic; ser1din : in std_logic; ser1dout : out std_logic ); end component; COMPONENT pre_enc_sim IS PORT( CLK : IN STD_LOGIC; -- fast clock 120MHz RSTn : IN STD_LOGIC; -- global reset (active low) WR : IN STD_LOGIC; -- write clock WE : IN STD_LOGIC; FUNC : IN STD_LOGIC_VECTOR(2 downto 0); -- PRE : OUT STD_LOGIC -- pre-trigger input ); END COMPONENT; begin mcmm: ser_int_mast port map( reset_n => reset_n, clk => clk, d0_we => d0_we, d0_send_start => d0_send_start, addr0_s => addr0_s, data0_s => data0_s, command0_s => command0_s, mcmaddr0_s => mcmaddr0_s, d1_we => d1_we, d1_send_start => d1_send_start, addr1_s => addr1_s, data1_s => data1_s, command1_s => command1_s, mcmaddr1_s => mcmaddr1_s, d0_received => d0_received, d0_recieve_error => d0_recieve_error, addr0_r => addr0_r, data0_r => data0_r, command0_r => command0_r, mcmaddr0_r => mcmaddr0_r, mcmhop0_r => open, d0_buffer_ready => d0_buffer_ready, d1_recieved => open, d1_recieve_error => open, addr1_r => open, data1_r => open, command1_r => open, mcmaddr1_r => open, mcmhop1_r => open, d1_buffer_ready => open, ser0din => ser0din, ser0dout => ser0dout, ser1din => ser1din, ser1dout => ser1dout ); -------------------------------------------------- -- async assignments -------------------------------------------------- ser1din <= '0'; d1_we <= '0'; d1_send_start <= '0'; d1_we <= '0'; data1_s <= (others => '0'); addr1_s <= (others => '0'); command1_s <= (others => '0'); mcmaddr1_s <= (0=>'1', others => '0'); -------------------------------------------------- -- processes -------------------------------------------------- -- reset generation rst: PROCESS(clk, reset_n) BEGIN if reset_n = '0' then reset_out_n <= '0'; wait_reset <= init_delay; elsif (clk'event and clk = '1') then if wait_reset > 0 then wait_reset <= wait_reset - 1; else reset_out_n <= '1'; end if; end if; END PROCESS; -- Current <= NextState - Assignment pc: PROCESS(clk, reset_out_n) BEGIN if reset_out_n = '0' then current_state0 <= idle; elsif ( clk'event and clk = '1') then current_state0 <= next_state0; end if; END PROCESS; end_mark <= true when current_state0 = enddata else false; -- Selection of NextState ns_gen: PROCESS(current_state0, d0_buffer_ready, wait_dly, wait_delay_plus) BEGIN next_state0 <= current_state0; CASE current_state0 IS WHEN idle => if ENDFILE(ser_inp) then next_state0 <= enddata; else next_state0 <= read_file; end if; WHEN read_file => next_state0 <= check_read; WHEN check_read => if (d0_we = '1') then next_state0 <= start_send; elsif ENDFILE(ser_inp) then next_state0 <= idle; elsif (wait_delay_plus>0) then next_state0 <= wait_state; else next_state0 <= read_file; end if; WHEN start_send => if (d0_buffer_ready = '0') then next_state0 <= wait_finish; end if; WHEN wait_finish => if (d0_buffer_ready = '1') then next_state0 <= wait_state; end if; WHEN wait_state => if (wait_dly = 0) then next_state0 <= idle; end if; WHEN enddata => NULL; WHEN OTHERS => NULL; END CASE; END PROCESS; -- Generation of wait_dly wd_gen: PROCESS(clk, current_state0) variable ready_pos : std_logic; BEGIN if (clk'event and clk = '1') then ready_new <= ready; ready_old <= ready_new; if ready_new='1' and ready_old='0' then stop_wait <= '1'; elsif current_state0 = check_read then stop_wait <= '0'; end if; CASE current_state0 IS WHEN wait_state => if stop_wait='1' then wait_dly <= 0; elsif (wait_dly > 0) then wait_dly <= wait_dly-1; end if; WHEN OTHERS => wait_dly <= wait_delay + wait_delay_plus*120; END CASE; end if; END PROCESS; -- send: PROCESS(current_state0) variable LN, NL, SAVE_LN : Line; variable success : boolean; variable cmd : integer; variable addr : integer; variable data : integer; variable slaveno : integer; variable func : integer; BEGIN PESel <= '0'; CASE current_state0 IS WHEN read_file => d0_send_start <= '0'; wait_delay_plus <= 0; READLINE(ser_inp, LN); -- Read line from file SAVE_LN := LN; -- Keep copy of line READ(LN, cmd, success); -- read first value from line, should be command code if success= false then -- comment found WRITELINE(ser_out, SAVE_LN); d0_we <= '0'; else -- command found if (cmd = 12) then -- pretrigger pseudo command found READ(LN, func); READ(LN, func); PESel <= '1'; PEFunc <= conv_std_logic_vector(func, 3); NL := new string'(""); WRITE (NL, cmd); WRITE (NL,' '); WRITE (NL, 0); WRITE (NL,' '); WRITE (NL, func); WRITELINE(ser_out, NL); d0_we <= '0'; elsif (cmd = 8) then -- wait READ(LN, func); READ(LN, func); NL := new string'(""); WRITE (NL, cmd); WRITE (NL,' '); WRITE (NL, 0); WRITE (NL,' '); WRITE (NL, func); WRITELINE(ser_out, NL); wait_delay_plus <= func; d0_we <= '0'; else READ(LN, addr); READ(LN, data); command0_s <= conv_std_logic_vector(cmd, 4); addr0_s <= conv_std_logic_vector(addr, 16); data0_s <= conv_std_logic_vector(data, 32); READ(LN, slaveno, success); if success then mcmaddr0_s <= conv_std_logic_vector(slaveno, 7); else mcmaddr0_s <= (0=>'1', others => '0'); end if; d0_we <= '1'; end if; end if; WHEN start_send => d0_send_start <= '1'; d0_we <= '0'; WHEN OTHERS => d0_send_start <= '0'; d0_we <= '0'; END CASE; END PROCESS; we_fifo <= d0_we; process(we_fifo, reset_n) begin if reset_n = '0' then wpointer <= 0; elsif we_fifo'event and we_fifo='1' then data0h(wpointer) <= data0_s; addr0h(wpointer) <= addr0_s; if wpointer clk, RSTn => reset_n, WR => clk, WE => PESel, FUNC => PEFunc, PRE => PRE ); end;