LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;


-- Pre-trigger encoder
-- last modified: 16:01 / 08 May 2003 / V.Angelov


ENTITY pre_enc_sim IS
PORT(
                CLK             : IN  STD_LOGIC; -- fast clock 120MHz
                RSTn            : IN  STD_LOGIC; -- global reset (active low)
                WR              : IN  STD_LOGIC; -- write clock
                WE              : IN  STD_LOGIC;
                FUNC            : IN  STD_LOGIC_VECTOR(2 downto 0); --
                PRE             : OUT STD_LOGIC -- pre-trigger input
        );
END pre_enc_sim;


architecture a of pre_enc_sim is


type sm is (idle, send);


signal send_sm : sm;
signal counter : Integer range 0 to 3;
signal bitcnt  : Integer range 0 to 7;
signal FUNC_s : STD_LOGIC_VECTOR(2 downto 0);
signal WE_s   : std_logic;
signal WE_c   : std_logic;
signal done_n : std_logic;
signal shiftd : std_logic_vector(6 downto 0);


begin
        process(WR, done_n)
        begin
                if done_n='0' then WE_s <= '0'; FUNC_s <= "000";
                elsif WR'event and WR='1' then
                   if WE='1' then
                      WE_s <= '1';
                      if WE_s='0' then FUNC_s <= FUNC; end if;
                   end if;
                end if;
        end process;


        process(CLK, RSTn)
        begin
                if RSTn='0' then
                        send_sm <= idle;
                        counter <=  3;
                        done_n  <= '0';
                        WE_c    <= '0';
                        bitcnt  <= shiftd'high;
                        shiftd  <= "0000000";
                elsif clk'event and clk='1' then
                        done_n <= '0';
                        WE_c <= WE_s;
                        case send_sm is
                                when idle =>
                                      counter <= 2;
                                      bitcnt  <= shiftd'high;
                                      done_n <= '1';
                                      if WE_c='1' then
                                         case FUNC_s is
                                           when "001"  => shiftd  <= "1000000";
                                           when "010"  => shiftd  <= "1100000";
                                           when "011"  => shiftd  <= "1110000";
                                           when "100"  => shiftd  <= "1111000";
                                           when "101"  => shiftd  <= "1111001";
                                           when "110"  => shiftd  <= "1111010";
                                           when "111"  => shiftd  <= "1111011";
                                           when others => shiftd  <= "0000000";
                                         end case;
                                         send_sm <= send;
                                      end if;
                                when send   => if counter /=0 then counter <= counter - 1;
                                                              else counter <= 2; end if;
                                               if counter = 0 then
                                                        shiftd <= shiftd(shiftd'high-1 downto 0) & '0';
                                                        if bitcnt = 0 then send_sm <= idle; done_n <= '0';
                                                                      else bitcnt  <= bitcnt - 1;
                                                        end if;
                                               end if;
                        end case;
                end if;
        end process;


        PRE <= shiftd(shiftd'high);


end;