LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY PLL4 IS
  PORT (
         REF     : IN  std_logic; -- Input clock
         FB      : IN  std_logic; -- Feedback from a delayed place on the chip
         BYPASS  : IN  std_logic; -- pass thru mode enable
         RESET   : IN  std_logic; -- Reset not
         LOCK    : OUT std_logic; -- PLL is in lock
         PLLOUT  : OUT std_logic  -- PLL clock out
       );
END PLL4;

ARCHITECTURE a OF PLL4 IS

SIGNAL rclk    : std_logic;
SIGNAL fclk    : std_logic;
SIGNAL bypassi : std_logic;
SIGNAL reseti  : std_logic;
SIGNAL locki   : std_logic;
SIGNAL clk     : std_logic;

SIGNAL clko    : std_logic := '0' ;
SIGNAL lockii  : std_logic := '0' ;

SIGNAL clk1 : std_logic;
SIGNAL clk2 : std_logic;
SIGNAL clk3 : std_logic;
SIGNAL clk4 : std_logic;

SIGNAL enabled : std_logic := '0' ;

signal rclk_en : std_logic := '0';

procedure buf(signal datain:in std_logic;
             signal dataout:out std_logic) is
begin
  dataout<=datain;
end;

procedure buf_tim(signal datain:in std_logic;
                del:time;
                signal dataout:out std_logic) is
begin
  dataout<=datain after del;
end;

BEGIN
  buf(REF,rclk);
  buf(FB,fclk);
  buf(BYPASS,bypassi);
  buf(RESET,reseti);
  buf(locki,LOCK);
  buf(clk,PLLOUT);

  buf_tim(clko, 0 ps, clk1) ;
  buf_tim(clk1, 0 ps, clk2) ;
  buf_tim(clk2, 0 ps, clk3) ;
  buf_tim(clk3, 0 ps, clk4) ;


  clk  <= rclk WHEN ( bypassi = '1' ) ELSE
          '0'  WHEN ( reseti  = '1' ) ELSE
           clk4;

  locki <= '0' WHEN ( bypassi = '1' ) ELSE
           '0' WHEN ( reseti  = '1' ) ELSE
            lockii;

process
  VARIABLE  time_unstable     : time ;
begin
        wait until rclk'event;
        if rclk /= '1' and rclk /= '0' then time_unstable := NOW; end if;
        wait for 1 ns;
--        if NOW-time_unstable > 6 ns then rclk_en <= not rclk; else rclk_en <= '0'; end if;
end process;
  rclk_en <= '1' after 9 ns;

fperiod: PROCESS

  VARIABLE last_posedge : time := 0 ps ;
  VARIABLE enabled :std_logic;
  VARIABLE high_time, low_time, period :time := 0 ns;
  BEGIN
  wait until rclk_en'event and rclk_en='1';
  WAIT UNTIL rclk'EVENT and rclk = '1';
  last_posedge := NOW ;
  WAIT UNTIL rclk'EVENT and rclk = '1';
  period := NOW - last_posedge ;
  high_time := period * 1 * 100000 / 2 / 400000 ;
  low_time  := period * 1 * 100000 / 2 / 400000 ;

  enabled   := '1' ;
  lockii    <= '1' ;

    LOOP
      clko <= '1';
      wait for high_time;
      clko <= '0';
      wait for low_time ;
    END LOOP ;

END PROCESS;

END a;