LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY pll120 IS
        PORT
        (
                inclk0          : IN STD_LOGIC  := '0';
                areset          : IN STD_LOGIC  := '0';
                c0              : OUT STD_LOGIC ;
                e0              : OUT STD_LOGIC
        );
END pll120;


ARCHITECTURE a OF pll120 IS

component PLL4 IS
  PORT (
         REF     : IN  std_logic; -- Input clock
         FB      : IN  std_logic; -- Feedback from a delayed place on the chip
         BYPASS  : IN  std_logic; -- pass thru mode enable
         RESET   : IN  std_logic; -- Reset not
         LOCK    : OUT std_logic; -- PLL is in lock
         PLLOUT  : OUT std_logic  -- PLL clock out
       );
END component;

signal clk : std_logic;

begin

pll: PLL4
  PORT map(
         REF     => inclk0,
         FB      => inclk0,
         BYPASS  => '0',
         RESET   => areset,
         LOCK    => open,
         PLLOUT  => clk
       );
    c0 <= clk;
    e0 <= clk;

end;