-------------------------------------------------------------------------------
-- Title      : ni_port_stim
-- Project    : Network Interface (NI) for the ALICE TRD TRAP2
-------------------------------------------------------------------------------
-- File       : ni_port_stim.vhd
-- Author     : Rolf Schneider  <rolf.schneider@kip.uni-heidelberg.de>
-- Company    : University Heidelberg - KIP
-- Last update: 2003-04-15
-- Platform   : Synopsys - v2003.03
-------------------------------------------------------------------------------
-- Description: Reads the input stimuli for local & global I/O signals
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/04/14  1.0      schneide        Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;

----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
entity ni_port_stim is
  generic (
    filename    : string := "DATA/port_stim_tr.txt";       -- stimulus filename
    start       : integer := 5;                            -- start time
    period_time : time    := 10 ns;
    width       : integer := 10);                          -- port width
  port (
    start_n        : in  STD_LOGIC;
    p_strobe_in_0  : out STD_LOGIC;
    p_d_in_0       : out STD_LOGIC_VECTOR(width-1 downto 0);
    p_strobe_in_1  : out STD_LOGIC;
    p_d_in_1       : out STD_LOGIC_VECTOR(width-1 downto 0);
    p_strobe_in_2  : out STD_LOGIC;
    p_d_in_2       : out STD_LOGIC_VECTOR(width-1 downto 0);
    p_strobe_in_3  : out STD_LOGIC;
    p_d_in_3       : out STD_LOGIC_VECTOR(width-1 downto 0);
    p_ctrl_in      : out STD_LOGIC);
end ni_port_stim;

----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture v of ni_port_stim is

  -- CONSTANTS -------------------------------------------------------------------------------------
  file port_stim       : text open read_mode is filename;

  -- STRUCTURE -------------------------------------------------------------------------------------
begin

  read_port_stim: process
    variable lin : line;
    variable good : boolean;
    variable s0, s1, s2, s3 : std_logic;
    variable d0, d1, d2, d3 : std_logic_vector(9 downto 0);
    variable ci : std_logic;
    variable count : integer := 0;
  begin
    p_strobe_in_0 <= '1'; p_d_in_0 <= (others => 'X');
    p_strobe_in_1 <= '1'; p_d_in_1 <= (others => 'X');
    p_strobe_in_2 <= '1'; p_d_in_2 <= (others => 'X');
    p_strobe_in_3 <= '1'; p_d_in_3 <= (others => 'X');
    p_ctrl_in <= '1';
--    wait for period_time * start;
    wait until start_n'event and start_n='0';
    while (endfile(port_stim) = false and count < 12) loop
      readline(port_stim, lin);
      read(lin, s0, good);
      if s0 = '1' or s0 = '0' then
        count := count + 1;
                       read(lin, d0);
        read(lin, s1); read(lin, d1);
        read(lin, s2); read(lin, d2);
        read(lin, s3); read(lin, d3);
        read(lin, ci);
        p_d_in_0 <= d0;
        p_d_in_1 <= d1;
        p_d_in_2 <= d2;
        p_d_in_3 <= d3;
        p_ctrl_in <= ci;
        wait for period_time/2 - 1 ns;
        p_strobe_in_0 <= s0;
        p_strobe_in_1 <= s1;
        p_strobe_in_2 <= s2;
        p_strobe_in_3 <= s3;
        wait for 1 ns;
      end if;
    end loop;

    wait until start_n'event and start_n='0';
    while (endfile(port_stim) = false and count < 99) loop
      readline(port_stim, lin);
      read(lin, s0, good);
      if s0 = '1' or s0 = '0' then
        count := count + 1;
                       read(lin, d0);
        read(lin, s1); read(lin, d1);
        read(lin, s2); read(lin, d2);
        read(lin, s3); read(lin, d3);
        read(lin, ci);
        p_d_in_0 <= d0;
        p_d_in_1 <= d1;
        p_d_in_2 <= d2;
        p_d_in_3 <= d3;
        p_ctrl_in <= ci;
        wait for period_time/2 - 1 ns;
        p_strobe_in_0 <= s0;
        p_strobe_in_1 <= s1;
        p_strobe_in_2 <= s2;
        p_strobe_in_3 <= s3;
        wait for 1 ns;
      end if;
    end loop;
--    wait;
  end process;

end v;

----------------------------------------------------------------------------------------------------
-- CONFIGURATION
----------------------------------------------------------------------------------------------------
-- pragma translate_off
configuration ni_port_stim_CFG of ni_port_stim is
  for v
  end for; -- v
end ni_port_stim_CFG;
-- pragma translate_on