LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity adcs_dacs is
    port (
           VMCM_Shdwn_a               : in    std_logic;
           VMCM_Shdwn_d               : in    std_logic;
           PW_INCn                    : in    std_logic_vector(3 downto 0);
           PW_UDn                     : in    std_logic_vector(3 downto 0);
           PW_CSn                     : in    std_logic_vector(3 downto 0);

           MSply_ADC_nCS              : in    std_logic;
           MSply_ADC_INTn             : out   std_logic;
           MSply_ADC_nCSStrt          : in    std_logic;
           MSply_ADC_SDI              : in    std_logic;
           MSply_ADC_SDO              : out   std_logic;
           MSply_ADC_SCLK             : in    std_logic;
           -- DDS for the 3 ADC channels AD9854
           DDS_FSK                    : in    std_logic;
           DDS_ShKey                  : in    std_logic;
           DDS_CSn                    : in    std_logic;
           DDS_SCLK                   : in    std_logic;
           DDS_UDCLK                  : in    std_logic;
           DDS_SDI                    : in    std_logic;
           DDS_SDO                    : out   std_logic; -- ??
           DDS_IORST                  : in    std_logic;
           DDS_MRST                   : in    std_logic;
           DDS_MCLK                   : in    std_logic;
           -- PASA ADC ADS5221
           PAADC_D                    : out   std_logic_vector(11 downto 0);
           PAADC_OVR                  : out   std_logic;
           PAADC_CLK                  : in    std_logic;
           PAADC_Msel                 : in    std_logic;
           PAADC_STDP                 : in    std_logic;

           PAADC_MuxnRS               : in    std_logic;
           PAADC_MuxA                 : in    std_logic_vector( 1 downto 0);
           -- PASA DACs AD9744
           PasaDAC1_CLK               : in    std_logic;
           PasaDAC2_CLK               : in    std_logic;
           PasaDAC_Sleep              : in    std_logic;
           PasaDAC_D                  : in    std_logic_vector(13 downto 0);
           -- Slow DAC 2xTLV5630
           SlowDAC1_SCLK              : in    std_logic;
           SlowDAC2_SCLK              : in    std_logic;
           SlowDAC1_LDACn             : in    std_logic;
           SlowDAC2_LDACn             : in    std_logic;
           SlowDAC_Din                : in    std_logic;
           SlowDAC1_FS                : in    std_logic;
           SlowDAC2_FS                : in    std_logic;
           -- SC ADC TLV2548
           SC_ADC_SDO                 : out   std_logic;
           SC_ADC_INTn                : out   std_logic;
           SC_ADC_nCSStrt             : in    std_logic;
           SC_ADC_SCLK                : in    std_logic;
           SC_ADC_SDI                 : in    std_logic;
           SC_ADC_nCS                 : in    std_logic
           );
end adcs_dacs;

--------------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------------
architecture sim of adcs_dacs is

signal paadc : std_logic_vector(10 downto 0);
signal dds_sr, dds_dr : std_logic_vector(15 downto 0);
signal dds_ir         : std_logic_vector( 7 downto 0);
signal dds_bitcnt     : Integer range 0 to 7;
signal dds_bytecnt    : Integer range 0 to 7;


begin
        -- PASA ADC ADS5221
        process(PAADC_CLK, PAADC_MuxnRS)
        begin
            if PAADC_MuxnRS='0' then
                paadc     <= (others => '0');
                PAADC_D   <= (others => '0');
                PAADC_OVR <= '0';
            elsif PAADC_CLK'event and PAADC_CLK='1' then
                paadc <= paadc + 1;
                PAADC_D <= PAADC_MuxA & paadc(9 downto 0);
                PAADC_OVR <= paadc(paadc'high);
            end if;
        end process;

        MSply_ADC_INTn  <= '1';
        MSply_ADC_SDO   <= '0';
        -- DDS for the 3 ADC channels AD9854

        process(DDS_SCLK, DDS_MRST, DDS_IORST)
        begin
            if DDS_MRST = '1' or DDS_IORST = '1' then
                dds_bytecnt <= 0;
                dds_bitcnt  <= 0;
            elsif DDS_SCLK'event and DDS_SCLK='1' then
                if dds_bitcnt < 7 then dds_bitcnt <= dds_bitcnt + 1;
                                  else dds_bitcnt <= 0; end if;
                if dds_bitcnt = 7 then dds_bytecnt <= dds_bytecnt + 1; end if;
                if dds_bytecnt < 1 then dds_ir <= dds_ir(6 downto 0) & DDS_SDI; end if;
                if dds_bytecnt > 0 and dds_ir(7)='0' then dds_dr <= dds_dr(14 downto 0) & DDS_SDI; end if;
                if dds_bytecnt = 0 and dds_bitcnt = 7 and dds_ir(6)='1' then dds_sr <= dds_dr; end if;
                if dds_bytecnt > 0 and dds_ir(7)='1' then dds_sr <= dds_sr(14 downto 0) & '0'; end if;

            end if;
        end process;

        process(DDS_SCLK)
        begin
            if DDS_SCLK'event and DDS_SCLK='0' then
                DDS_SDO <= dds_sr(15);
            end if;
        end process;

        -- SC ADC TLV2548
        SC_ADC_SDO      <= '0';
        SC_ADC_INTn     <= '1';
end;