fsim :
	vsim -quiet -t 1ns 'work.top_tb(struct)' -do 'wave_func.do'

fsimw :
	vsim -quiet -t 1ns 'work.top_wtb(struct)' -do 'wave_wfunc.do'

altera :
	rm -rf altera_mf
	vlib altera_mf
	vmap altera_mf_components altera_mf
	vcom -quiet -work altera_mf_components -93 ../SRC_ALTERA/altera_mf_components.vhd
	vcom -quiet -work altera_mf_components -93 ../SRC_ALTERA/altera_mf.vhd
	rm -rf lpm
	vlib lpm
	vmap lpm_components lpm
	vcom -quiet -work lpm_components -93 ../SRC_ALTERA/220pack.vhd
	vcom -quiet -work lpm_components -93 ../SRC_ALTERA/220model.vhd

top_tb : create_work
	vmap trap2 ../../../SHARE/functional
# compile simulation model for some ADCs and DACs
# dummy
	vcom -quiet -work work -93 -explicit ./SRC/adcs_dacs.vhd

# scsn serial master
	SCRIPTS/cser_int

# compile the top of all TRAP chips
#	vcom -quiet -work work -93 -explicit ./SRC/ni_port_stim.vhd
	vcom -quiet -work work -93 -explicit ./SRC/trap.vhd
	vcom -quiet -work work -93 -explicit ./SRC/traps.vhd

	vcom -quiet -work work -93 -explicit ./SRC/max7310.vhd
	vcom -quiet -work work -93 -explicit ./SRC/jtag_sm.vhd
# compile top testbench
	vcom -quiet -work work -93 -explicit ./SRC/top_tb.vhd
	vcom -quiet -work work -93 -explicit ./SRC/top_wtb.vhd

fmf:
	rm -rf fmf
	vlib fmf
	vcom -quiet -work fmf -93 -explicit ./SRC/conversions.vhd
	vcom -quiet -work fmf -93 -explicit ./SRC/gen_utils.vhd

fpga1:
	rm -rf fpga1
	SCRIPTS/cfpga1
	
fpga2:
	rm -rf fpga2
	SCRIPTS/cfpga2

fpga1w:
	rm -rf fpga1w
	SCRIPTS/cfpga1w
	
fpga2w:
	rm -rf fpga2w
	SCRIPTS/cfpga2w

compile: altera fpga1 fpga2 fpga1w fpga2w fmf top_tb

create_work :
	rm -rf work
	vlib work

inc :
	inc2dat -n -i DATA/test.inc > DATA/sc_send.dat

tjtg:
	tcc DATA/tjtag.tcs > DATA/sc_send.dat

tdpot:
	tcc DATA/tdpot.tcs > DATA/sc_send.dat

tsrings:
	tcc DATA/tsrings.tcs > DATA/sc_send.dat

clean :
	rm -rf transcript vsim.wlf work fpga1 fpga2 altera_mf lpm fpga1w fpga2w fmf

#.PHONY :  altera top_tb fpga1 fpga2 create_work fsim inc clean tjtg tdpot tsrings fpga1w fpga2w