const fpga2 = 1;
const fpga1 = 2;
const dut   = 2;
const ni0   = 3;
const ni1   = 4;
const ni2   = 5;
const ni3   = 6;
// base address of the JTAG master
const jtg_up  = 0x4100;
const jtg_dn  = 0x4200;
const jtg_dut = 0x4300;
// offset relative to the base address of the JTAG master
const tms_wr  = 0x00A0;
const jtg_sm  = 0x0080;
const jtg_cnf = 0x00C0; // speed(1..0) enable(3..2)
// conf reg scsn switch
const scsn_sw = 0x4400;
const tst_pads = 0x4490;
const dig_pot =  0x50C0;
const pwr_ena =  0x5080;

// scsn ring fpga2+fpga1
write fpga2, scsn_sw, 1;
reset;
nop;
expect fpga2, tst_pads, 1001b;
write fpga1, pwr_ena, 01b;
write fpga1, pwr_ena, 10b;
write fpga1, pwr_ena, 11b;
write fpga1, pwr_ena, 00b;
expect fpga2, tst_pads, 1001b;
wait 600
expect fpga2, tst_pads, 1001b;
write fpga1, dig_pot, 0x60403020;
wait 600
expect fpga2, tst_pads, 1001b;
write fpga1, dig_pot, 0x20304050;