******************************************************* Cell: toplevel View: default Library: work ******************************************************* Total accumulated area : Number of BUFGP : 13 Number of Dffs or Latches : 6602 Number of Function Generators : 48936 Number of IBUF : 113 Number of MUX CARRYs : 6980 Number of MUXF5 : 3083 Number of MUXF6 : 72 Number of OBUF : 60 Number of accumulated instances : 45731 Number of ports : 186 Number of nets : 5086 Number of instances : 1066 Number of references to this view : 0 Cell Library References Total Area BUFGP xcv2p 13 x 1 13 BUFGP FD xcv2p 9 x 1 9 Dffs or Latches FDCE xcv2p 324 x 1 324 Dffs or Latches GND xcv2p 1 x 1 1 GND IBUF xcv2p 113 x 1 113 IBUF LUT1 xcv2p 8 x 1 8 Function Generators LUT2 xcv2p 9 x 1 9 Function Generators LUT3 xcv2p 67 x 1 67 Function Generators LUT4 xcv2p 199 x 1 199 Function Generators MUXF5 xcv2p 22 x 1 22 MUXF5 OBUF xcv2p 60 x 1 60 OBUF RAM64X1D xcv2p 126 x 8 1008 Function Generators VCC xcv2p 1 x 1 1 VCC input_0 work 1 x 1 1 GND 1 1 VCC 6 6 MUXF7 12 12 MUXF6 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 cg_fifo_dc 207 207 Dffs or Latches 38 38 MUXF5 373 373 Function Generators 264 264 gates input_1 work 1 x 1 1 GND 1 1 VCC 5 5 MUXF7 16 16 MUXF6 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 cg_fifo_dc 207 207 Dffs or Latches 42 42 MUXF5 377 377 Function Generators 268 268 gates input_2 work 1 x 1 1 GND 1 1 VCC 8 8 MUXF7 17 17 MUXF6 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 cg_fifo_dc 207 207 Dffs or Latches 43 43 MUXF5 372 372 Function Generators 263 263 gates input_3 work 1 x 1 1 GND 1 1 VCC 6 6 MUXF7 15 15 MUXF6 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 cg_fifo_dc 207 207 Dffs or Latches 39 39 MUXF5 367 367 Function Generators 258 258 gates input_4 work 1 x 1 1 GND 1 1 VCC 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 4 4 MUXF6 2 2 cg_fifo_dc 207 207 Dffs or Latches 30 30 MUXF5 397 397 Function Generators 288 288 gates input_5 work 1 x 1 1 VCC 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 5 5 MUXF6 2 2 GND 2 2 cg_fifo_dc 207 207 Dffs or Latches 30 30 MUXF5 386 386 Function Generators 277 277 gates matching_logic_1_12 work 3 x 793 2379 gates 1 3 GND 1 3 VCC 18 54 MUXF5 10 30 XORCY 500 1500 MUX CARRYs 804 2412 Function Generators matching_logic_2_8 work 3 x 793 2379 gates 1 3 GND 1 3 VCC 16 48 MUXF5 10 30 XORCY 500 1500 MUX CARRYs 799 2397 Function Generators matching_logic_3_0 work 3 x 792 2376 gates 1 3 GND 1 3 VCC 16 48 MUXF5 10 30 XORCY 500 1500 MUX CARRYs 801 2403 Function Generators matching_memory work 9 x 93 837 gates 1 9 GND 1 9 VCC 3 27 MUXF5 19 171 Dffs or Latches 6 54 MUX CARRYs 406 3654 Function Generators matching_memory work 45 x 99 4455 gates 1 45 GND 1 45 VCC 3 135 MUXF5 19 855 Dffs or Latches 6 270 MUX CARRYs 518 23310 Function Generators reconst work 1 x 1 1 VCC 1 1 GND 1 1 MUXF6 549 549 Dffs or Latches 193 193 MUX CARRYs 198 198 XORCY 1 1 cg_divide 6 6 Block Multipliers 73 73 MUXF5 684 684 Function Generators 641 641 gates seed_merger work 3 x 189 567 gates 1 3 VCC 1 3 GND 56 168 MUXF5 30 90 Dffs or Latches 21 63 MUX CARRYs 503 1509 Function Generators sorter_8 work 18 x 418 7524 gates 1 18 GND 121 2178 MUXF5 155 2790 Dffs or Latches 80 1440 MUX CARRYs 420 7560 Function Generators uniquifier_42 work 1 x 46 46 gates 1 1 VCC 1 1 GND 3 3 MUXF5 87 87 Dffs or Latches 4 4 XORCY 23 23 MUX CARRYs 46 46 Function Generators uniquifier_52 work 3 x 46 138 gates 1 3 VCC 1 3 GND 3 9 MUXF5 107 321 Dffs or Latches 4 12 XORCY 23 69 MUX CARRYs 46 138 Function Generators uniquifier_53 work 1 x 46 46 gates 1 1 VCC 1 1 GND 3 3 MUXF5 109 109 Dffs or Latches 4 4 XORCY 23 23 MUX CARRYs 46 46 Function Generators zch_merger work 1 x 238 238 gates 1 1 VCC 1 1 GND 3 3 MUXF5 30 30 Dffs or Latches 26 26 XORCY 52 52 MUX CARRYs 552 552 Function Generators 3 3 Block Multipliers zch_resorter work 1 x 96 96 gates 1 1 GND 1 1 VCC 1 1 MUXF5 25 25 Dffs or Latches 11 11 MUX CARRYs 305 305 Function Generators zch_table_0_0 work 1 x 17 17 gates 20 20 Function Generators 5 5 MUXF5 zch_table_0_1 work 1 x 22 22 gates 25 25 Function Generators 3 3 MUXF5 zch_table_0_2 work 1 x 17 17 gates 20 20 Function Generators 5 5 MUXF5 zch_table_1_0 work 1 x 19 19 gates 22 22 Function Generators 1 1 MUXF6 5 5 MUXF5 zch_table_1_1 work 1 x 20 20 gates 23 23 Function Generators 1 1 GND 7 7 MUXF5 zch_table_1_2 work 1 x 24 24 gates 27 27 Function Generators 5 5 MUXF5 zch_table_2_0 work 1 x 12 12 gates 15 15 Function Generators zch_table_3_0 work 1 x 19 19 gates 22 22 Function Generators 5 5 MUXF5 zch_table_3_1 work 1 x 20 20 gates 23 23 Function Generators 6 6 MUXF5 zch_table_3_2 work 1 x 19 19 gates 22 22 Function Generators 6 6 MUXF5 zch_table_4_0 work 1 x 19 19 gates 22 22 Function Generators 6 6 MUXF5 zch_table_4_1 work 1 x 21 21 gates 24 24 Function Generators 1 1 VCC 8 8 MUXF5 zch_table_4_2 work 1 x 19 19 gates 22 22 Function Generators 1 1 GND 8 8 MUXF5 zch_table_5_0 work 1 x 21 21 gates 24 24 Function Generators 1 1 MUXF6 7 7 MUXF5 zch_table_5_1 work 1 x 20 20 gates 23 23 Function Generators 7 7 MUXF5 zch_table_5_2 work 1 x 20 20 gates 23 23 Function Generators 6 6 MUXF5 ******************************************************* Cell: input_5 View: default_unfold_2871 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 386 Number of MUX CARRYs : 47 Number of MUXF5 : 30 Number of MUXF6 : 5 Number of accumulated instances : 639 Number of ports : 81 Number of nets : 372 Number of instances : 223 Number of references to this view : 1 Cell Library References Total Area FD xcv2p 26 x 1 26 Dffs or Latches FDC xcv2p 1 x 1 1 Dffs or Latches FDCE xcv2p 6 x 1 6 Dffs or Latches FDR xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 3 x 1 3 Function Generators LUT1_L xcv2p 19 x 1 19 Function Generators LUT2 xcv2p 12 x 1 12 Function Generators LUT2_L xcv2p 33 x 1 33 Function Generators LUT3 xcv2p 2 x 1 2 Function Generators LUT4 xcv2p 4 x 1 4 Function Generators MULT18X18 xcv2p 2 x 1 2 Block Multipliers MUXCY_L xcv2p 47 x 1 47 MUX CARRYs RAM64X1D xcv2p 13 x 8 104 Function Generators VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 48 x 1 48 XORCY buffer_merger work 1 x 52 52 gates 53 53 Function Generators 2 2 MUXF5 3 3 Dffs or Latches 2 2 cg_fifo_dc inputcontrol work 2 x 43 86 gates 43 86 Function Generators 2 4 MUXF5 85 170 Dffs or Latches yt_lut_5 work 1 x 67 67 gates 70 70 Function Generators 1 1 GND 5 5 MUXF6 24 24 MUXF5 ******************************************************* Cell: inputcontrol View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 85 Number of Function Generators : 43 Number of MUXF5 : 2 Number of accumulated instances : 130 Number of ports : 45 Number of nets : 142 Number of instances : 130 Number of references to this view : 12 Cell Library References Total Area FDC xcv2p 43 x 1 43 Dffs or Latches FDCE xcv2p 1 x 1 1 Dffs or Latches FDCE_1 xcv2p 33 x 1 33 Dffs or Latches FDC_1 xcv2p 8 x 1 8 Dffs or Latches LUT1 xcv2p 2 x 1 2 Function Generators LUT2 xcv2p 31 x 1 31 Function Generators LUT3 xcv2p 2 x 1 2 Function Generators LUT4 xcv2p 8 x 1 8 Function Generators MUXF5 xcv2p 2 x 1 2 MUXF5 ******************************************************* Cell: buffer_merger View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 3 Number of Function Generators : 53 Number of MUXF5 : 2 Number of accumulated instances : 60 Number of ports : 105 Number of nets : 195 Number of instances : 60 Number of references to this view : 6 Cell Library References Total Area FDC xcv2p 3 x 1 3 Dffs or Latches LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 4 x 1 4 Function Generators LUT3 xcv2p 3 x 1 3 Function Generators LUT4 xcv2p 43 x 1 43 Function Generators MUXF5 xcv2p 2 x 1 2 MUXF5 cg_fifo_dc work 2 x 1 2 cg_fifo_dc ******************************************************* Cell: cg_fifo_dc View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of ports : 71 Number of nets : 0 Number of instances : 0 Number of references to this view : 3 ******************************************************* Cell: yt_lut_5 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 70 Number of MUXF5 : 24 Number of MUXF6 : 5 Number of accumulated instances : 100 Number of ports : 18 Number of nets : 107 Number of instances : 100 Number of references to this view : 1 Cell Library References Total Area GND xcv2p 1 x 1 1 GND LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 8 x 1 8 Function Generators LUT4 xcv2p 56 x 1 56 Function Generators MUXF5 xcv2p 24 x 1 24 MUXF5 MUXF6 xcv2p 5 x 1 5 MUXF6 ******************************************************* Cell: input_4 View: default_unfold_2870 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 397 Number of MUX CARRYs : 47 Number of MUXF5 : 30 Number of MUXF6 : 4 Number of accumulated instances : 648 Number of ports : 81 Number of nets : 371 Number of instances : 223 Number of references to this view : 1 Cell Library References Total Area FD xcv2p 26 x 1 26 Dffs or Latches FDC xcv2p 1 x 1 1 Dffs or Latches FDCE xcv2p 6 x 1 6 Dffs or Latches FDR xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 3 x 1 3 Function Generators LUT1_L xcv2p 19 x 1 19 Function Generators LUT2 xcv2p 12 x 1 12 Function Generators LUT2_L xcv2p 33 x 1 33 Function Generators LUT3 xcv2p 2 x 1 2 Function Generators LUT4 xcv2p 4 x 1 4 Function Generators MULT18X18 xcv2p 2 x 1 2 Block Multipliers MUXCY_L xcv2p 47 x 1 47 MUX CARRYs RAM64X1D xcv2p 13 x 8 104 Function Generators VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 48 x 1 48 XORCY buffer_merger work 1 x 52 52 gates 53 53 Function Generators 2 2 MUXF5 3 3 Dffs or Latches 2 2 cg_fifo_dc inputcontrol work 2 x 43 86 gates 43 86 Function Generators 2 4 MUXF5 85 170 Dffs or Latches yt_lut_4 work 1 x 78 78 gates 81 81 Function Generators 4 4 MUXF6 24 24 MUXF5 ******************************************************* Cell: yt_lut_4 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 81 Number of MUXF5 : 24 Number of MUXF6 : 4 Number of accumulated instances : 109 Number of ports : 18 Number of nets : 116 Number of instances : 109 Number of references to this view : 1 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 5 x 1 5 Function Generators LUT3 xcv2p 16 x 1 16 Function Generators LUT4 xcv2p 57 x 1 57 Function Generators MUXF5 xcv2p 24 x 1 24 MUXF5 MUXF6 xcv2p 4 x 1 4 MUXF6 ******************************************************* Cell: input_3 View: default_unfold_2869 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 367 Number of MUX CARRYs : 47 Number of MUXF5 : 39 Number of MUXF6 : 15 Number of accumulated instances : 644 Number of ports : 81 Number of nets : 463 Number of instances : 327 Number of references to this view : 1 Cell Library References Total Area FD xcv2p 26 x 1 26 Dffs or Latches FDC xcv2p 1 x 1 1 Dffs or Latches FDCE xcv2p 6 x 1 6 Dffs or Latches FDR xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 6 x 1 6 Function Generators LUT1_L xcv2p 19 x 1 19 Function Generators LUT2 xcv2p 13 x 1 13 Function Generators LUT2_L xcv2p 33 x 1 33 Function Generators LUT3 xcv2p 4 x 1 4 Function Generators LUT4 xcv2p 49 x 1 49 Function Generators MULT18X18 xcv2p 2 x 1 2 Block Multipliers MUXCY_L xcv2p 47 x 1 47 MUX CARRYs MUXF5 xcv2p 33 x 1 33 MUXF5 MUXF6 xcv2p 15 x 1 15 MUXF6 MUXF7 xcv2p 6 x 1 6 MUXF7 RAM64X1D xcv2p 13 x 8 104 Function Generators VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 48 x 1 48 XORCY buffer_merger work 1 x 52 52 gates 53 53 Function Generators 2 2 MUXF5 3 3 Dffs or Latches 2 2 cg_fifo_dc inputcontrol work 2 x 43 86 gates 43 86 Function Generators 2 4 MUXF5 85 170 Dffs or Latches ******************************************************* Cell: input_2 View: default_unfold_2868 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 372 Number of MUX CARRYs : 47 Number of MUXF5 : 43 Number of MUXF6 : 17 Number of accumulated instances : 657 Number of ports : 81 Number of nets : 476 Number of instances : 340 Number of references to this view : 1 Cell Library References Total Area FD xcv2p 26 x 1 26 Dffs or Latches FDC xcv2p 1 x 1 1 Dffs or Latches FDCE xcv2p 6 x 1 6 Dffs or Latches FDR xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 6 x 1 6 Function Generators LUT1_L xcv2p 19 x 1 19 Function Generators LUT2 xcv2p 12 x 1 12 Function Generators LUT2_L xcv2p 33 x 1 33 Function Generators LUT3 xcv2p 3 x 1 3 Function Generators LUT4 xcv2p 56 x 1 56 Function Generators MULT18X18 xcv2p 2 x 1 2 Block Multipliers MUXCY_L xcv2p 47 x 1 47 MUX CARRYs MUXF5 xcv2p 37 x 1 37 MUXF5 MUXF6 xcv2p 17 x 1 17 MUXF6 MUXF7 xcv2p 8 x 1 8 MUXF7 RAM64X1D xcv2p 13 x 8 104 Function Generators VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 48 x 1 48 XORCY buffer_merger work 1 x 52 52 gates 53 53 Function Generators 2 2 MUXF5 3 3 Dffs or Latches 2 2 cg_fifo_dc inputcontrol work 2 x 43 86 gates 43 86 Function Generators 2 4 MUXF5 85 170 Dffs or Latches ******************************************************* Cell: input_1 View: default_unfold_2867 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 377 Number of MUX CARRYs : 47 Number of MUXF5 : 42 Number of MUXF6 : 16 Number of accumulated instances : 657 Number of ports : 81 Number of nets : 478 Number of instances : 340 Number of references to this view : 1 Cell Library References Total Area FD xcv2p 26 x 1 26 Dffs or Latches FDC xcv2p 1 x 1 1 Dffs or Latches FDCE xcv2p 6 x 1 6 Dffs or Latches FDR xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 6 x 1 6 Function Generators LUT1_L xcv2p 19 x 1 19 Function Generators LUT2 xcv2p 11 x 1 11 Function Generators LUT2_L xcv2p 33 x 1 33 Function Generators LUT3 xcv2p 8 x 1 8 Function Generators LUT4 xcv2p 57 x 1 57 Function Generators MULT18X18 xcv2p 2 x 1 2 Block Multipliers MUXCY_L xcv2p 47 x 1 47 MUX CARRYs MUXF5 xcv2p 36 x 1 36 MUXF5 MUXF6 xcv2p 16 x 1 16 MUXF6 MUXF7 xcv2p 5 x 1 5 MUXF7 RAM64X1D xcv2p 13 x 8 104 Function Generators VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 48 x 1 48 XORCY buffer_merger work 1 x 52 52 gates 53 53 Function Generators 2 2 MUXF5 3 3 Dffs or Latches 2 2 cg_fifo_dc inputcontrol work 2 x 43 86 gates 43 86 Function Generators 2 4 MUXF5 85 170 Dffs or Latches ******************************************************* Cell: input_0 View: default_unfold_2866 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 373 Number of MUX CARRYs : 47 Number of MUXF5 : 38 Number of MUXF6 : 12 Number of accumulated instances : 646 Number of ports : 81 Number of nets : 468 Number of instances : 329 Number of references to this view : 1 Cell Library References Total Area FD xcv2p 26 x 1 26 Dffs or Latches FDC xcv2p 1 x 1 1 Dffs or Latches FDCE xcv2p 6 x 1 6 Dffs or Latches FDR xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 6 x 1 6 Function Generators LUT1_L xcv2p 19 x 1 19 Function Generators LUT2 xcv2p 11 x 1 11 Function Generators LUT2_L xcv2p 33 x 1 33 Function Generators LUT3 xcv2p 11 x 1 11 Function Generators LUT4 xcv2p 50 x 1 50 Function Generators MULT18X18 xcv2p 2 x 1 2 Block Multipliers MUXCY_L xcv2p 47 x 1 47 MUX CARRYs MUXF5 xcv2p 32 x 1 32 MUXF5 MUXF6 xcv2p 12 x 1 12 MUXF6 MUXF7 xcv2p 6 x 1 6 MUXF7 RAM64X1D xcv2p 13 x 8 104 Function Generators VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 48 x 1 48 XORCY buffer_merger work 1 x 52 52 gates 53 53 Function Generators 2 2 MUXF5 3 3 Dffs or Latches 2 2 cg_fifo_dc inputcontrol work 2 x 43 86 gates 43 86 Function Generators 2 4 MUXF5 85 170 Dffs or Latches ******************************************************* Cell: reconst View: default_unfold_2185 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 549 Number of Function Generators : 684 Number of MUX CARRYs : 193 Number of MUXF5 : 73 Number of MUXF6 : 1 Number of accumulated instances : 1707 Number of ports : 268 Number of nets : 1929 Number of instances : 1669 Number of references to this view : 1 Cell Library References Total Area FD xcv2p 406 x 1 406 Dffs or Latches FDC xcv2p 140 x 1 140 Dffs or Latches FDR xcv2p 2 x 1 2 Dffs or Latches FDS xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 5 x 1 5 Function Generators LUT1_L xcv2p 114 x 1 114 Function Generators LUT2 xcv2p 18 x 1 18 Function Generators LUT2_L xcv2p 90 x 1 90 Function Generators LUT3 xcv2p 81 x 1 81 Function Generators LUT4 xcv2p 308 x 1 308 Function Generators MULT18X18 xcv2p 6 x 1 6 Block Multipliers MUXCY_L xcv2p 193 x 1 193 MUX CARRYs MUXF5 xcv2p 60 x 1 60 MUXF5 MUXF6 xcv2p 1 x 1 1 MUXF6 SRLC16 xcv2p 42 x 1 42 Function Generators VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 198 x 1 198 XORCY acoeff_lut_2 work 1 x 26 26 gates 26 26 Function Generators 13 13 MUXF5 cg_divide work 1 x 1 1 cg_divide ******************************************************* Cell: acoeff_lut_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 26 Number of MUXF5 : 13 Number of accumulated instances : 39 Number of ports : 18 Number of nets : 44 Number of instances : 39 Number of references to this view : 1 Cell Library References Total Area LUT3 xcv2p 3 x 1 3 Function Generators LUT4 xcv2p 23 x 1 23 Function Generators MUXF5 xcv2p 13 x 1 13 MUXF5 ******************************************************* Cell: cg_divide View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of ports : 75 Number of nets : 0 Number of instances : 0 Number of references to this view : 2 ******************************************************* Cell: zch_table_5_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 23 Number of MUXF5 : 6 Number of accumulated instances : 29 Number of ports : 10 Number of nets : 36 Number of instances : 29 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 4 x 1 4 Function Generators LUT4 xcv2p 16 x 1 16 Function Generators MUXF5 xcv2p 6 x 1 6 MUXF5 ******************************************************* Cell: sorter_8 View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 155 Number of Function Generators : 420 Number of MUX CARRYs : 80 Number of MUXF5 : 121 Number of accumulated instances : 777 Number of ports : 42 Number of nets : 799 Number of instances : 777 Number of references to this view : 36 Cell Library References Total Area FDCE xcv2p 11 x 1 11 Dffs or Latches FDPE xcv2p 144 x 1 144 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 5 x 1 5 Function Generators LUT2 xcv2p 124 x 1 124 Function Generators LUT2_L xcv2p 80 x 1 80 Function Generators LUT3 xcv2p 118 x 1 118 Function Generators LUT4 xcv2p 93 x 1 93 Function Generators MUXCY xcv2p 8 x 1 8 MUX CARRYs MUXCY_L xcv2p 72 x 1 72 MUX CARRYs MUXF5 xcv2p 121 x 1 121 MUXF5 ******************************************************* Cell: zch_table_5_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 23 Number of MUXF5 : 7 Number of accumulated instances : 30 Number of ports : 10 Number of nets : 37 Number of instances : 30 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 3 x 1 3 Function Generators LUT4 xcv2p 17 x 1 17 Function Generators MUXF5 xcv2p 7 x 1 7 MUXF5 ******************************************************* Cell: zch_table_5_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 24 Number of MUXF5 : 7 Number of MUXF6 : 1 Number of accumulated instances : 32 Number of ports : 10 Number of nets : 39 Number of instances : 32 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 2 x 1 2 Function Generators LUT3 xcv2p 1 x 1 1 Function Generators LUT4 xcv2p 18 x 1 18 Function Generators MUXF5 xcv2p 7 x 1 7 MUXF5 MUXF6 xcv2p 1 x 1 1 MUXF6 ******************************************************* Cell: zch_table_4_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 8 Number of accumulated instances : 31 Number of ports : 10 Number of nets : 38 Number of instances : 31 Number of references to this view : 2 Cell Library References Total Area GND xcv2p 1 x 1 1 GND LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 3 x 1 3 Function Generators LUT4 xcv2p 16 x 1 16 Function Generators MUXF5 xcv2p 8 x 1 8 MUXF5 ******************************************************* Cell: zch_table_4_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 24 Number of MUXF5 : 8 Number of accumulated instances : 33 Number of ports : 10 Number of nets : 40 Number of instances : 33 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 1 x 1 1 Function Generators LUT3 xcv2p 5 x 1 5 Function Generators LUT4 xcv2p 15 x 1 15 Function Generators MUXF5 xcv2p 8 x 1 8 MUXF5 VCC xcv2p 1 x 1 1 VCC ******************************************************* Cell: zch_table_4_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 6 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 1 x 1 1 Function Generators LUT3 xcv2p 1 x 1 1 Function Generators LUT4 xcv2p 17 x 1 17 Function Generators MUXF5 xcv2p 6 x 1 6 MUXF5 ******************************************************* Cell: zch_table_3_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 6 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 4 x 1 4 Function Generators LUT4 xcv2p 15 x 1 15 Function Generators MUXF5 xcv2p 6 x 1 6 MUXF5 ******************************************************* Cell: zch_table_3_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 23 Number of MUXF5 : 6 Number of accumulated instances : 29 Number of ports : 10 Number of nets : 36 Number of instances : 29 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 1 x 1 1 Function Generators LUT4 xcv2p 16 x 1 16 Function Generators MUXF5 xcv2p 6 x 1 6 MUXF5 ******************************************************* Cell: zch_table_3_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 5 Number of accumulated instances : 27 Number of ports : 10 Number of nets : 34 Number of instances : 27 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 3 x 1 3 Function Generators LUT4 xcv2p 16 x 1 16 Function Generators MUXF5 xcv2p 5 x 1 5 MUXF5 ******************************************************* Cell: zch_table_2_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 15 Number of accumulated instances : 15 Number of ports : 10 Number of nets : 22 Number of instances : 15 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 3 x 1 3 Function Generators LUT4 xcv2p 9 x 1 9 Function Generators ******************************************************* Cell: zch_table_1_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 27 Number of MUXF5 : 5 Number of accumulated instances : 32 Number of ports : 10 Number of nets : 39 Number of instances : 32 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 2 x 1 2 Function Generators LUT3 xcv2p 5 x 1 5 Function Generators LUT4 xcv2p 17 x 1 17 Function Generators MUXF5 xcv2p 5 x 1 5 MUXF5 ******************************************************* Cell: zch_table_1_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 23 Number of MUXF5 : 7 Number of accumulated instances : 31 Number of ports : 10 Number of nets : 38 Number of instances : 31 Number of references to this view : 2 Cell Library References Total Area GND xcv2p 1 x 1 1 GND LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 5 x 1 5 Function Generators LUT4 xcv2p 15 x 1 15 Function Generators MUXF5 xcv2p 7 x 1 7 MUXF5 ******************************************************* Cell: zch_table_1_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 5 Number of MUXF6 : 1 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 2 x 1 2 Function Generators LUT4 xcv2p 17 x 1 17 Function Generators MUXF5 xcv2p 5 x 1 5 MUXF5 MUXF6 xcv2p 1 x 1 1 MUXF6 ******************************************************* Cell: zch_table_0_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 20 Number of MUXF5 : 5 Number of accumulated instances : 25 Number of ports : 10 Number of nets : 32 Number of instances : 25 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 5 x 1 5 Function Generators LUT4 xcv2p 12 x 1 12 Function Generators MUXF5 xcv2p 5 x 1 5 MUXF5 ******************************************************* Cell: zch_table_0_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 25 Number of MUXF5 : 3 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 5 x 1 5 Function Generators LUT4 xcv2p 17 x 1 17 Function Generators MUXF5 xcv2p 3 x 1 3 MUXF5 ******************************************************* Cell: zch_table_0_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 20 Number of MUXF5 : 5 Number of accumulated instances : 25 Number of ports : 10 Number of nets : 32 Number of instances : 25 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2p 3 x 1 3 Function Generators LUT3 xcv2p 2 x 1 2 Function Generators LUT4 xcv2p 15 x 1 15 Function Generators MUXF5 xcv2p 5 x 1 5 MUXF5 ******************************************************* Cell: matching_memory View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 19 Number of Function Generators : 518 Number of MUX CARRYs : 6 Number of MUXF5 : 3 Number of accumulated instances : 184 Number of ports : 87 Number of nets : 223 Number of instances : 184 Number of references to this view : 60 Cell Library References Total Area FDP xcv2p 12 x 1 12 Dffs or Latches FDPE xcv2p 6 x 1 6 Dffs or Latches FDR xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 19 x 1 19 Function Generators LUT3 xcv2p 18 x 1 18 Function Generators LUT4 xcv2p 56 x 1 56 Function Generators LUT4_L xcv2p 6 x 1 6 Function Generators MUXCY xcv2p 2 x 1 2 MUX CARRYs MUXCY_L xcv2p 4 x 1 4 MUX CARRYs MUXF5 xcv2p 3 x 1 3 MUXF5 RAM64X1D xcv2p 52 x 8 416 Function Generators VCC xcv2p 1 x 1 1 VCC ******************************************************* Cell: matching_memory View: default_unfold_2672 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 19 Number of Function Generators : 406 Number of MUX CARRYs : 6 Number of MUXF5 : 3 Number of accumulated instances : 163 Number of ports : 87 Number of nets : 201 Number of instances : 163 Number of references to this view : 12 Cell Library References Total Area FDP xcv2p 12 x 1 12 Dffs or Latches FDPE xcv2p 6 x 1 6 Dffs or Latches FDR xcv2p 1 x 1 1 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 2 x 1 2 Function Generators LUT2 xcv2p 18 x 1 18 Function Generators LUT3 xcv2p 12 x 1 12 Function Generators LUT4 xcv2p 56 x 1 56 Function Generators LUT4_L xcv2p 6 x 1 6 Function Generators MUXCY xcv2p 2 x 1 2 MUX CARRYs MUXCY_L xcv2p 4 x 1 4 MUX CARRYs MUXF5 xcv2p 3 x 1 3 MUXF5 RAM64X1D xcv2p 39 x 8 312 Function Generators VCC xcv2p 1 x 1 1 VCC ******************************************************* Cell: matching_logic_3_0 View: default_unfold_2202 Library: work ******************************************************* Total accumulated area : Number of Function Generators : 801 Number of MUX CARRYs : 500 Number of MUXF5 : 16 Number of accumulated instances : 1329 Number of ports : 265 Number of nets : 1562 Number of instances : 1329 Number of references to this view : 4 Cell Library References Total Area GND xcv2p 1 x 1 1 GND LUT1 xcv2p 24 x 1 24 Function Generators LUT1_L xcv2p 6 x 1 6 Function Generators LUT2 xcv2p 59 x 1 59 Function Generators LUT2_L xcv2p 493 x 1 493 Function Generators LUT3 xcv2p 42 x 1 42 Function Generators LUT4 xcv2p 174 x 1 174 Function Generators LUT4_L xcv2p 3 x 1 3 Function Generators MUXCY xcv2p 58 x 1 58 MUX CARRYs MUXCY_L xcv2p 442 x 1 442 MUX CARRYs MUXF5 xcv2p 16 x 1 16 MUXF5 VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 10 x 1 10 XORCY ******************************************************* Cell: matching_logic_2_8 View: default_unfold_2209 Library: work ******************************************************* Total accumulated area : Number of Function Generators : 799 Number of MUX CARRYs : 500 Number of MUXF5 : 16 Number of accumulated instances : 1327 Number of ports : 265 Number of nets : 1560 Number of instances : 1327 Number of references to this view : 4 Cell Library References Total Area GND xcv2p 1 x 1 1 GND LUT1 xcv2p 25 x 1 25 Function Generators LUT1_L xcv2p 5 x 1 5 Function Generators LUT2 xcv2p 58 x 1 58 Function Generators LUT2_L xcv2p 493 x 1 493 Function Generators LUT3 xcv2p 43 x 1 43 Function Generators LUT4 xcv2p 171 x 1 171 Function Generators LUT4_L xcv2p 4 x 1 4 Function Generators MUXCY xcv2p 58 x 1 58 MUX CARRYs MUXCY_L xcv2p 442 x 1 442 MUX CARRYs MUXF5 xcv2p 16 x 1 16 MUXF5 VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 10 x 1 10 XORCY ******************************************************* Cell: matching_logic_1_12 View: default_unfold_2219 Library: work ******************************************************* Total accumulated area : Number of Function Generators : 804 Number of MUX CARRYs : 500 Number of MUXF5 : 18 Number of accumulated instances : 1334 Number of ports : 265 Number of nets : 1567 Number of instances : 1334 Number of references to this view : 4 Cell Library References Total Area GND xcv2p 1 x 1 1 GND LUT1 xcv2p 24 x 1 24 Function Generators LUT1_L xcv2p 6 x 1 6 Function Generators LUT2 xcv2p 60 x 1 60 Function Generators LUT2_L xcv2p 493 x 1 493 Function Generators LUT3 xcv2p 42 x 1 42 Function Generators LUT4 xcv2p 176 x 1 176 Function Generators LUT4_L xcv2p 3 x 1 3 Function Generators MUXCY xcv2p 58 x 1 58 MUX CARRYs MUXCY_L xcv2p 442 x 1 442 MUX CARRYs MUXF5 xcv2p 18 x 1 18 MUXF5 VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 10 x 1 10 XORCY ******************************************************* Cell: seed_merger View: default_unfold_2616 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 30 Number of Function Generators : 503 Number of MUX CARRYs : 21 Number of MUXF5 : 56 Number of accumulated instances : 456 Number of ports : 219 Number of nets : 618 Number of instances : 456 Number of references to this view : 6 Cell Library References Total Area FDC xcv2p 12 x 1 12 Dffs or Latches FDCE xcv2p 18 x 1 18 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 5 x 1 5 Function Generators LUT2 xcv2p 20 x 1 20 Function Generators LUT2_L xcv2p 21 x 1 21 Function Generators LUT3 xcv2p 123 x 1 123 Function Generators LUT4 xcv2p 22 x 1 22 Function Generators MUXCY xcv2p 3 x 1 3 MUX CARRYs MUXCY_L xcv2p 18 x 1 18 MUX CARRYs MUXF5 xcv2p 56 x 1 56 MUXF5 RAM16X1D xcv2p 156 x 2 312 Function Generators VCC xcv2p 1 x 1 1 VCC ******************************************************* Cell: uniquifier_52 View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 107 Number of Function Generators : 46 Number of MUX CARRYs : 23 Number of MUXF5 : 3 Number of accumulated instances : 185 Number of ports : 110 Number of nets : 241 Number of instances : 185 Number of references to this view : 6 Cell Library References Total Area FD xcv2p 53 x 1 53 Dffs or Latches FDC xcv2p 2 x 1 2 Dffs or Latches FDE xcv2p 52 x 1 52 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 1 x 1 1 Function Generators LUT1_L xcv2p 2 x 1 2 Function Generators LUT2_L xcv2p 2 x 1 2 Function Generators LUT3 xcv2p 12 x 1 12 Function Generators LUT4 xcv2p 10 x 1 10 Function Generators LUT4_L xcv2p 19 x 1 19 Function Generators MUXCY xcv2p 8 x 1 8 MUX CARRYs MUXCY_L xcv2p 15 x 1 15 MUX CARRYs MUXF5 xcv2p 3 x 1 3 MUXF5 VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 4 x 1 4 XORCY ******************************************************* Cell: zch_merger View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 30 Number of Function Generators : 552 Number of MUX CARRYs : 52 Number of MUXF5 : 3 Number of accumulated instances : 512 Number of ports : 220 Number of nets : 689 Number of instances : 512 Number of references to this view : 2 Cell Library References Total Area FD xcv2p 3 x 1 3 Dffs or Latches FDCE xcv2p 9 x 1 9 Dffs or Latches FDR xcv2p 9 x 1 9 Dffs or Latches FDRE xcv2p 9 x 1 9 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 12 x 1 12 Function Generators LUT1_L xcv2p 29 x 1 29 Function Generators LUT2 xcv2p 15 x 1 15 Function Generators LUT2_L xcv2p 21 x 1 21 Function Generators LUT3 xcv2p 124 x 1 124 Function Generators LUT4 xcv2p 33 x 1 33 Function Generators LUT4_L xcv2p 6 x 1 6 Function Generators MULT18X18 xcv2p 3 x 1 3 Block Multipliers MUXCY xcv2p 9 x 1 9 MUX CARRYs MUXCY_L xcv2p 43 x 1 43 MUX CARRYs MUXF5 xcv2p 3 x 1 3 MUXF5 RAM16X1D xcv2p 156 x 2 312 Function Generators VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 26 x 1 26 XORCY ******************************************************* Cell: uniquifier_53 View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 109 Number of Function Generators : 46 Number of MUX CARRYs : 23 Number of MUXF5 : 3 Number of accumulated instances : 187 Number of ports : 112 Number of nets : 244 Number of instances : 187 Number of references to this view : 2 Cell Library References Total Area FD xcv2p 54 x 1 54 Dffs or Latches FDC xcv2p 2 x 1 2 Dffs or Latches FDE xcv2p 53 x 1 53 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 1 x 1 1 Function Generators LUT1_L xcv2p 2 x 1 2 Function Generators LUT2_L xcv2p 2 x 1 2 Function Generators LUT3 xcv2p 12 x 1 12 Function Generators LUT4 xcv2p 10 x 1 10 Function Generators LUT4_L xcv2p 19 x 1 19 Function Generators MUXCY xcv2p 8 x 1 8 MUX CARRYs MUXCY_L xcv2p 15 x 1 15 MUX CARRYs MUXF5 xcv2p 3 x 1 3 MUXF5 VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 4 x 1 4 XORCY ******************************************************* Cell: zch_resorter View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 25 Number of Function Generators : 305 Number of MUX CARRYs : 11 Number of MUXF5 : 1 Number of accumulated instances : 240 Number of ports : 102 Number of nets : 298 Number of instances : 240 Number of references to this view : 2 Cell Library References Total Area FDC xcv2p 9 x 1 9 Dffs or Latches FDCE xcv2p 16 x 1 16 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 3 x 1 3 Function Generators LUT2 xcv2p 21 x 1 21 Function Generators LUT2_L xcv2p 7 x 1 7 Function Generators LUT3 xcv2p 50 x 1 50 Function Generators LUT4 xcv2p 12 x 1 12 Function Generators LUT4_L xcv2p 4 x 1 4 Function Generators MUXCY xcv2p 3 x 1 3 MUX CARRYs MUXCY_L xcv2p 8 x 1 8 MUX CARRYs MUXF5 xcv2p 1 x 1 1 MUXF5 RAM16X1D xcv2p 104 x 2 208 Function Generators VCC xcv2p 1 x 1 1 VCC ******************************************************* Cell: uniquifier_42 View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 87 Number of Function Generators : 46 Number of MUX CARRYs : 23 Number of MUXF5 : 3 Number of accumulated instances : 165 Number of ports : 90 Number of nets : 211 Number of instances : 165 Number of references to this view : 2 Cell Library References Total Area FD xcv2p 43 x 1 43 Dffs or Latches FDC xcv2p 2 x 1 2 Dffs or Latches FDE xcv2p 42 x 1 42 Dffs or Latches GND xcv2p 1 x 1 1 GND LUT1 xcv2p 1 x 1 1 Function Generators LUT1_L xcv2p 2 x 1 2 Function Generators LUT2_L xcv2p 2 x 1 2 Function Generators LUT3 xcv2p 12 x 1 12 Function Generators LUT4 xcv2p 10 x 1 10 Function Generators LUT4_L xcv2p 19 x 1 19 Function Generators MUXCY xcv2p 8 x 1 8 MUX CARRYs MUXCY_L xcv2p 15 x 1 15 MUX CARRYs MUXF5 xcv2p 3 x 1 3 MUXF5 VCC xcv2p 1 x 1 1 VCC XORCY xcv2p 4 x 1 4 XORCY Number of global buffers used: 13 *********************************************** Device Utilization for 2VP70ff1517 *********************************************** Resource Used Avail Utilization ----------------------------------------------- IOs 173 964 17.95% Global Buffers 13 16 81.25% Function Generators 48936 66176 73.95% CLB Slices 24468 33088 73.95% Dffs or Latches 6602 69068 9.56% Block RAMs 0 328 0.00% Block Multipliers 21 328 6.40% ----------------------------------------------- Using wire table: xcv2p-2-7_wc Clock Frequency Report Clock : Frequency ------------------------------------ clk : 29.1 MHz clk1_in(5) : 130.8 MHz clk1_in(4) : 130.8 MHz clk1_in(3) : 130.8 MHz clk1_in(2) : 130.8 MHz clk1_in(1) : 130.8 MHz clk1_in(0) : 130.8 MHz clk0_in(5) : 130.8 MHz clk0_in(4) : 130.8 MHz clk0_in(3) : 130.8 MHz clk0_in(2) : 130.8 MHz clk0_in(1) : 130.8 MHz clk0_in(0) : 130.8 MHz Slack Table at End Points End points Slack Arrival Required rise fall rise fall match_gen1_1_match_gen2_2_match_inst_gen_5_matching_memory1/reg_reg_b(3)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/reg_reg_b(5)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/reg_reg_b(4)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/reg_reg_b(3)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_0_match_gen2_2_match_inst_gen_0_matching_memory1/reg_reg_b(4)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/reg_reg_b(1)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_1_match_gen2_2_match_inst_gen_5_matching_memory1/reg_reg_b(4)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_b(3)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_1_match_gen2_1_match_inst_gen_3_matching_memory1/reg_reg_b(3)/D : -9.33 34.10 34.10 24.77 24.77 match_gen1_1_match_gen2_1_match_inst_gen_3_matching_memory1/reg_reg_b(4)/D : -9.33 34.10 34.10 24.77 24.77 Critical Path Report Critical path #1, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_2_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_2_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/NOT_modgen_sub_4280_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_sub_4280_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_2_match_gen2_1_match_inst_matching_logic1/cmp_b_ll_a(5)/O LUT4 1.19 12.29 up 0.90 match_gen1_2_match_gen2_1_match_inst_matching_logic1/nx787/O LUT4 0.89 13.18 up 0.60 track_post_match(6)(5)/O LUT3 1.19 14.37 up 0.90 match_gen1_2_match_gen2_1_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.29 15.75 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.41 17.66 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix2_ix22/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix2_ix26/O XORCY 1.41 19.86 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/nx847/O LUT4 0.89 22.22 up 0.60 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix873/O MUXF5 1.28 23.50 up 1.00 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix874/O MUXF5 2.47 25.97 up 1.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/nx1284/O LUT4 1.09 27.06 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/a(0)_dup_380/O LUT4 1.09 28.15 up 0.80 match_gen1_2_match_gen2_1_match_inst_inc(3)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_2_match_gen2_1_match_inst_gen_3_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_2_match_gen2_1_match_inst_gen_3_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_2_match_gen2_1_match_inst_gen_3_matching_memory1/nx1296/O LUT4 0.89 33.21 up 0.60 match_gen1_2_match_gen2_1_match_inst_gen_3_matching_memory1/nx126/O LUT3 0.89 34.10 up 0.60 match_gen1_2_match_gen2_1_match_inst_gen_3_matching_memory1/reg_reg_b(4)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #2, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_3_match_inst_gen_3_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_1_match_gen2_3_match_inst_gen_3_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/NOT_modgen_sub_3909_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_1_match_gen2_3_match_inst_matching_logic1/modgen_sub_3909_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_1_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_1_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_1_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_1_match_gen2_3_match_inst_matching_logic1/cmp_b_ll_a(5)/O LUT4 1.19 12.29 up 0.90 match_gen1_1_match_gen2_3_match_inst_matching_logic1/nx783/O LUT4 0.89 13.18 up 0.60 track_post_match(5)(5)/O LUT3 1.19 14.37 up 0.90 match_gen1_1_match_gen2_3_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ix0_ix10/LO LUT1_L 0.29 15.75 up 0.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ix0_ix14/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ix0_ix18/O XORCY 1.41 17.66 up 0.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ix2_ix19/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ix2_ix23/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ix2_ix27/O XORCY 1.41 19.86 up 0.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_1_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/nx836/O LUT4 0.89 22.22 up 0.60 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ix862/O MUXF5 1.28 23.50 up 1.00 match_gen1_1_match_gen2_3_match_inst_matching_logic1/ix863/O MUXF5 2.47 25.97 up 1.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/nx1337/O LUT4 1.09 27.06 up 0.80 match_gen1_1_match_gen2_3_match_inst_matching_logic1/a(0)_dup_399/O LUT4 1.09 28.15 up 0.80 match_gen1_1_match_gen2_3_match_inst_inc(0)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_1_match_gen2_3_match_inst_gen_0_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_1_match_gen2_3_match_inst_gen_0_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_1_match_gen2_3_match_inst_gen_0_matching_memory1/nx1302/O LUT4 0.89 33.21 up 0.60 match_gen1_1_match_gen2_3_match_inst_gen_0_matching_memory1/nx132/O LUT3 0.89 34.10 up 0.60 match_gen1_1_match_gen2_3_match_inst_gen_0_matching_memory1/reg_reg_b(1)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #3, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_2_match_gen2_2_match_inst_gen_2_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_2_match_gen2_2_match_inst_gen_2_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/NOT_modgen_sub_4094_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_2_match_gen2_2_match_inst_matching_logic1/modgen_sub_4094_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/modgen_gt_4113_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_2_match_gen2_2_match_inst_matching_logic1/modgen_gt_4113_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_2_match_gen2_2_match_inst_matching_logic1/modgen_gt_4113_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_2_match_gen2_2_match_inst_matching_logic1/modgen_gt_4113_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_2_match_gen2_2_match_inst_matching_logic1/cmp_b_ll_a(5)/O LUT4 1.19 12.29 up 0.90 match_gen1_2_match_gen2_2_match_inst_matching_logic1/nx785/O LUT4 0.89 13.18 up 0.60 track_post_match(7)(5)/O LUT3 1.19 14.37 up 0.90 match_gen1_2_match_gen2_2_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ix0_ix10/LO LUT4_L 0.29 15.75 up 0.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ix0_ix14/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ix0_ix18/O XORCY 1.41 17.66 up 0.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ix2_ix19/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ix2_ix23/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ix2_ix27/O XORCY 1.41 19.86 up 0.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/modgen_add_4239_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_2_match_gen2_2_match_inst_matching_logic1/modgen_add_4239_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/nx837/O LUT4 0.89 22.22 up 0.60 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ix863/O MUXF5 1.28 23.50 up 1.00 match_gen1_2_match_gen2_2_match_inst_matching_logic1/ix864/O MUXF5 2.47 25.97 up 1.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/nx1340/O LUT4 1.09 27.06 up 0.80 match_gen1_2_match_gen2_2_match_inst_matching_logic1/a(0)_dup_398/O LUT4 1.09 28.15 up 0.80 match_gen1_2_match_gen2_2_match_inst_inc(0)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_2_match_gen2_2_match_inst_gen_0_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_2_match_gen2_2_match_inst_gen_0_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_2_match_gen2_2_match_inst_gen_0_matching_memory1/nx1294/O LUT4 0.89 33.21 up 0.60 match_gen1_2_match_gen2_2_match_inst_gen_0_matching_memory1/nx124/O LUT3 0.89 34.10 up 0.60 match_gen1_2_match_gen2_2_match_inst_gen_0_matching_memory1/reg_reg_b(5)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #4, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_sub_4280_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_sub_4280_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_1_match_gen2_1_match_inst_matching_logic1/cmp_b_ll_a(5)/O LUT4 1.19 12.29 up 0.90 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx787/O LUT4 0.89 13.18 up 0.60 track_post_match(3)(5)/O LUT3 1.19 14.37 up 0.90 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.29 15.75 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.41 17.66 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix22/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix26/O XORCY 1.41 19.86 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx847/O LUT4 0.89 22.22 up 0.60 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix873/O MUXF5 1.28 23.50 up 1.00 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix874/O MUXF5 2.47 25.97 up 1.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1284/O LUT4 1.09 27.06 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_380/O LUT4 1.09 28.15 up 0.80 match_gen1_1_match_gen2_1_match_inst_inc(3)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_1_match_gen2_1_match_inst_gen_3_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_1_match_gen2_1_match_inst_gen_3_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_1_match_gen2_1_match_inst_gen_3_matching_memory1/nx1298/O LUT4 0.89 33.21 up 0.60 match_gen1_1_match_gen2_1_match_inst_gen_3_matching_memory1/nx128/O LUT3 0.89 34.10 up 0.60 match_gen1_1_match_gen2_1_match_inst_gen_3_matching_memory1/reg_reg_b(3)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #5, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/NOT_modgen_sub_4280_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_sub_4280_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4299_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_0_match_gen2_1_match_inst_matching_logic1/cmp_b_ll_a(5)/O LUT4 1.19 12.29 up 0.90 match_gen1_0_match_gen2_1_match_inst_matching_logic1/nx787/O LUT4 0.89 13.18 up 0.60 track_post_match(0)(5)/O LUT3 1.19 14.37 up 0.90 match_gen1_0_match_gen2_1_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.29 15.75 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.41 17.66 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix22/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix26/O XORCY 1.41 19.86 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/nx847/O LUT4 0.89 22.22 up 0.60 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix873/O MUXF5 1.28 23.50 up 1.00 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix874/O MUXF5 2.47 25.97 up 1.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/nx1340/O LUT4 1.09 27.06 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/a(0)_dup_400/O LUT4 1.09 28.15 up 0.80 match_gen1_0_match_gen2_1_match_inst_inc(0)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/nx1298/O LUT4 0.89 33.21 up 0.60 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/nx128/O LUT3 0.89 34.10 up 0.60 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_b(3)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #6, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_0_match_gen2_2_match_inst_gen_2_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_0_match_gen2_2_match_inst_gen_2_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/NOT_modgen_sub_4094_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_0_match_gen2_2_match_inst_matching_logic1/modgen_sub_4094_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/modgen_gt_4113_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_0_match_gen2_2_match_inst_matching_logic1/modgen_gt_4113_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_0_match_gen2_2_match_inst_matching_logic1/modgen_gt_4113_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_0_match_gen2_2_match_inst_matching_logic1/modgen_gt_4113_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_0_match_gen2_2_match_inst_matching_logic1/cmp_b_ll_a(5)/O LUT4 1.19 12.29 up 0.90 match_gen1_0_match_gen2_2_match_inst_matching_logic1/nx785/O LUT4 0.89 13.18 up 0.60 track_post_match(1)(5)/O LUT3 1.19 14.37 up 0.90 match_gen1_0_match_gen2_2_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ix0_ix10/LO LUT4_L 0.29 15.75 up 0.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ix0_ix14/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ix0_ix18/O XORCY 1.41 17.66 up 0.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ix2_ix19/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ix2_ix23/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ix2_ix27/O XORCY 1.41 19.86 up 0.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/modgen_add_4239_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_0_match_gen2_2_match_inst_matching_logic1/modgen_add_4239_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/nx837/O LUT4 0.89 22.22 up 0.60 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ix863/O MUXF5 1.28 23.50 up 1.00 match_gen1_0_match_gen2_2_match_inst_matching_logic1/ix864/O MUXF5 2.47 25.97 up 1.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/nx1340/O LUT4 1.09 27.06 up 0.80 match_gen1_0_match_gen2_2_match_inst_matching_logic1/a(0)_dup_398/O LUT4 1.09 28.15 up 0.80 match_gen1_0_match_gen2_2_match_inst_inc(0)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_0_match_gen2_2_match_inst_gen_0_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_0_match_gen2_2_match_inst_gen_0_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_0_match_gen2_2_match_inst_gen_0_matching_memory1/nx1296/O LUT4 0.89 33.21 up 0.60 match_gen1_0_match_gen2_2_match_inst_gen_0_matching_memory1/nx126/O LUT3 0.89 34.10 up 0.60 match_gen1_0_match_gen2_2_match_inst_gen_0_matching_memory1/reg_reg_b(4)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #7, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_2_match_gen2_3_match_inst_gen_3_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_2_match_gen2_3_match_inst_gen_3_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/NOT_modgen_sub_3909_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_sub_3909_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/cmp_b_ll_a(5)/O LUT4 1.19 12.29 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx783/O LUT4 0.89 13.18 up 0.60 track_post_match(8)(5)/O LUT3 1.19 14.37 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix10/LO LUT1_L 0.29 15.75 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix14/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix18/O XORCY 1.41 17.66 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix19/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix23/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix27/O XORCY 1.41 19.86 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx837/O LUT4 0.89 22.22 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix862/O MUXF5 1.28 23.50 up 1.00 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix863/O MUXF5 2.47 25.97 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx1309/O LUT4 1.09 27.06 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/a(0)_dup_391/O LUT4 1.09 28.15 up 0.80 match_gen1_2_match_gen2_3_match_inst_inc(1)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1296/O LUT4 0.89 33.21 up 0.60 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx126/O LUT3 0.89 34.10 up 0.60 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/reg_reg_b(4)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #8, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_2_match_gen2_3_match_inst_gen_3_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_2_match_gen2_3_match_inst_gen_3_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/NOT_modgen_sub_3909_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_sub_3909_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3953_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3953_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3953_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3953_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/cmp_b_ll_a(4)/O LUT4 1.19 12.29 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx790/O LUT4 0.89 13.18 up 0.60 track_post_match(8)(4)/O LUT3 1.19 14.37 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix10/LO LUT1_L 0.29 15.75 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix14/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix18/O XORCY 1.41 17.66 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix19/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix23/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix27/O XORCY 1.41 19.86 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx836/O LUT4 0.89 22.22 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix862/O MUXF5 1.28 23.50 up 1.00 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix863/O MUXF5 2.47 25.97 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx1309/O LUT4 1.09 27.06 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/a(0)_dup_391/O LUT4 1.09 28.15 up 0.80 match_gen1_2_match_gen2_3_match_inst_inc(1)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1296/O LUT4 0.89 33.21 up 0.60 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx126/O LUT3 0.89 34.10 up 0.60 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/reg_reg_b(4)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #9, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_2_match_gen2_3_match_inst_gen_3_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_2_match_gen2_3_match_inst_gen_3_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/NOT_modgen_sub_3909_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_sub_3909_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3928_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/cmp_b_ll_a(5)/O LUT4 1.19 12.29 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx783/O LUT4 0.89 13.18 up 0.60 track_post_match(8)(5)/O LUT3 1.19 14.37 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix10/LO LUT1_L 0.29 15.75 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix14/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix18/O XORCY 1.41 17.66 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix19/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix23/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix27/O XORCY 1.41 19.86 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx836/O LUT4 0.89 22.22 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix862/O MUXF5 1.28 23.50 up 1.00 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix863/O MUXF5 2.47 25.97 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx1309/O LUT4 1.09 27.06 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/a(0)_dup_391/O LUT4 1.09 28.15 up 0.80 match_gen1_2_match_gen2_3_match_inst_inc(1)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1296/O LUT4 0.89 33.21 up 0.60 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx126/O LUT3 0.89 34.10 up 0.60 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/reg_reg_b(4)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 ------------------------------------------------------------------------------------------------------- Critical path #10, (path slack = -9.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_2_match_gen2_3_match_inst_gen_3_matching_memory1/reg_reg_a(5)/Q FDP 0.00 2.41 up 2.10 match_gen1_2_match_gen2_3_match_inst_gen_3_matching_memory1/ix629_ix114/DPO RAM64X1D 2.20 4.61 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/NOT_modgen_sub_3909_nx56/O LUT4 1.29 5.90 up 1.00 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_sub_3909_nx100/O LUT4 1.19 7.09 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ysa_minus(7)/O LUT2 2.09 9.18 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3953_ix57/LO LUT2_L 0.29 9.47 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3953_ix59/LO MUXCY_L 0.50 9.97 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3953_ix63/LO MUXCY_L 0.02 10.00 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_gt_3953_ix67/O MUXCY 1.10 11.10 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/cmp_b_ll_a(4)/O LUT4 1.19 12.29 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx790/O LUT4 0.89 13.18 up 0.60 track_post_match(8)(4)/O LUT3 1.19 14.37 up 0.90 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx643/O LUT2 1.09 15.46 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix10/LO LUT1_L 0.29 15.75 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix14/LO MUXCY_L 0.50 16.25 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix0_ix18/O XORCY 1.41 17.66 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix19/LO LUT1_L 0.29 17.95 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix23/LO MUXCY_L 0.50 18.45 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix2_ix27/O XORCY 1.41 19.86 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix23/LO LUT2_L 0.29 20.15 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/modgen_add_4054_ix25/O XORCY 1.18 21.33 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx837/O LUT4 0.89 22.22 up 0.60 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix862/O MUXF5 1.28 23.50 up 1.00 match_gen1_2_match_gen2_3_match_inst_matching_logic1/ix863/O MUXF5 2.47 25.97 up 1.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/nx1309/O LUT4 1.09 27.06 up 0.80 match_gen1_2_match_gen2_3_match_inst_matching_logic1/a(0)_dup_391/O LUT4 1.09 28.15 up 0.80 match_gen1_2_match_gen2_3_match_inst_inc(1)(1)/O LUT4 1.69 29.84 up 1.40 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1280/O LUT2 1.19 31.03 up 0.90 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1288/O LUT4 1.29 32.32 up 1.00 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx1294/O LUT4 0.89 33.21 up 0.60 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/nx124/O LUT3 0.89 34.10 up 0.60 match_gen1_2_match_gen2_3_match_inst_gen_1_matching_memory1/reg_reg_b(5)/D FDP 0.00 34.10 up 0.00 data arrival time 34.10 data required time (default specified - setup time) 24.77 ------------------------------------------------------------------------------------------------------- data required time 24.77 data arrival time 34.10 ---------- slack -9.33 -------------------------------------------------------------------------------------------------------