******************************************************* Cell: toplevel View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 26267 Number of Memory Bits : 203096 Number of accumulated instances : 29766 Number of ports : 186 Number of nets : 4727 Number of instances : 509 Number of references to this view : 0 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 1 x 1 1 NOT VCC stratix 1 x 1 1 VCC input_0 work 1 x 18 18 NOT 1 1 VCC 1344 1344 Memory Bits 1 1 lpm_mult_23 1 1 lpm_mult_21 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 2 2 GND 377 377 LCs input_1 work 1 x 18 18 NOT 1 1 VCC 1344 1344 Memory Bits 1 1 lpm_mult_19 1 1 lpm_mult_17 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 2 2 GND 400 400 LCs input_2 work 1 x 18 18 NOT 1 1 VCC 1344 1344 Memory Bits 1 1 lpm_mult_15 1 1 lpm_mult_13 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 2 2 GND 408 408 LCs input_3 work 1 x 18 18 NOT 1 1 VCC 1344 1344 Memory Bits 1 1 lpm_mult_11 1 1 lpm_mult_9 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 2 2 GND 383 383 LCs input_4 work 1 x 18 18 NOT 1 1 VCC 1344 1344 Memory Bits 1 1 lpm_mult_7 1 1 lpm_mult_5 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 2 2 GND 407 407 LCs input_5 work 1 x 18 18 NOT 1 1 VCC 1344 1344 Memory Bits 1 1 lpm_mult_3 1 1 lpm_mult_1 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 2 2 GND 399 399 LCs l_dpram_7_6_64_2_0 OPERATORS 18 x 448 8064 Memory Bits matching_logic_1_12 work 3 x 1 3 GND 1 3 VCC 806 2418 LCs matching_logic_2_8 work 3 x 806 2418 LCs 1 3 GND 1 3 VCC matching_logic_3_0 work 3 x 806 2418 LCs 1 3 GND 1 3 VCC matching_memory work 45 x 24 1080 NOT 1 45 GND 3328 149760 Memory Bits 111 4995 LCs matching_memory work 9 x 24 216 NOT 1 9 GND 3328 29952 Memory Bits 105 945 LCs reconst work 1 x 6 6 NOT 1 1 VCC 1 1 GND 672 672 Memory Bits 1 1 lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED 6 6 lpm_mult_13_13_9_18_SIGNED_1_LPM_MULT_UNUSED 821 821 LCs seed_merger work 3 x 1 3 GND 1224 3672 Memory Bits 189 567 LCs sorter_8 work 18 x 421 7578 LCs stratix_io_input stratix 126 x 1 126 IOs stratix_io_output stratix 60 x 1 60 IOs stratix_lcell_counter stratix 108 x 1 108 LCs stratix_lcell_normal stratix 80 x 1 80 LCs uniquifier_42 work 1 x 148 148 LCs 1 1 GND uniquifier_52 work 3 x 168 504 LCs 1 3 GND uniquifier_53 work 1 x 170 170 LCs 1 1 GND zch_merger work 1 x 1 1 VCC 1 1 GND 1248 1248 Memory Bits 238 238 LCs 3 3 lpm_mult_25 zch_resorter work 1 x 1 1 GND 1664 1664 Memory Bits 91 91 LCs zch_table_0_0 work 1 x 19 19 LCs zch_table_0_1 work 1 x 26 26 LCs zch_table_0_2 work 1 x 21 21 LCs zch_table_1_0 work 1 x 25 25 LCs zch_table_1_1 work 1 x 27 27 LCs zch_table_1_2 work 1 x 29 29 LCs zch_table_2_0 work 1 x 13 13 LCs zch_table_3_0 work 1 x 23 23 LCs zch_table_3_1 work 1 x 24 24 LCs zch_table_3_2 work 1 x 26 26 LCs zch_table_4_0 work 1 x 26 26 LCs zch_table_4_1 work 1 x 29 29 LCs zch_table_4_2 work 1 x 25 25 LCs zch_table_5_0 work 1 x 28 28 LCs zch_table_5_1 work 1 x 26 26 LCs zch_table_5_2 work 1 x 27 27 LCs ******************************************************* Cell: input_5 View: default_unfold_2871 Library: work ******************************************************* Total accumulated area : Number of LCs : 399 Number of Memory Bits : 1344 Number of accumulated instances : 433 Number of ports : 81 Number of nets : 324 Number of instances : 107 Number of references to this view : 1 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 19 x 1 19 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryo stratix 1 x 1 1 LCs buffer_merger work 1 x 52 52 LCs 1 1 GND 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 89 178 LCs l_dpram_21_6_64_2_0 OPERATORS 1 x 1344 1344 Memory Bits lpm_mult_1 OPERATORS 1 x 1 1 lpm_mult_1 lpm_mult_3 OPERATORS 1 x 1 1 lpm_mult_3 stratix_lcell_arithmetic stratix 52 x 1 52 LCs stratix_lcell_counter stratix 6 x 1 6 LCs stratix_lcell_reg stratix 11 x 1 11 LCs stratix_lcell_sync_reg stratix 9 x 1 9 LCs yt_lut_5 work 1 x 90 90 LCs ******************************************************* Cell: inputcontrol View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 89 Number of accumulated instances : 92 Number of ports : 45 Number of nets : 105 Number of instances : 92 Number of references to this view : 12 Cell Library References Total Area NOT stratix 3 x 1 3 NOT stratix_lcell stratix 16 x 1 16 LCs stratix_lcell_normal stratix 24 x 1 24 LCs stratix_lcell_reg stratix 49 x 1 49 LCs ******************************************************* Cell: buffer_merger View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 52 Number of accumulated instances : 56 Number of ports : 105 Number of nets : 190 Number of instances : 56 Number of references to this view : 6 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 1 x 1 1 NOT lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED work 2 x 1 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED stratix_lcell_arithmetic stratix 4 x 1 4 LCs stratix_lcell_normal stratix 48 x 1 48 LCs ******************************************************* Cell: lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of ports : 80 Number of nets : 0 Number of instances : 0 Number of references to this view : 2 ******************************************************* Cell: yt_lut_5 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 90 Number of accumulated instances : 90 Number of ports : 18 Number of nets : 97 Number of instances : 90 Number of references to this view : 1 Cell Library References Total Area stratix_lcell_normal stratix 90 x 1 90 LCs ******************************************************* Cell: lpm_mult_1 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 36 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: lpm_mult_3 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 28 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: l_dpram_21_6_64_2_0 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of Memory Bits : 1344 Number of ports : 56 Number of nets : 0 Number of instances : 0 Number of references to this view : 19 ******************************************************* Cell: input_4 View: default_unfold_2870 Library: work ******************************************************* Total accumulated area : Number of LCs : 407 Number of Memory Bits : 1344 Number of accumulated instances : 441 Number of ports : 81 Number of nets : 323 Number of instances : 107 Number of references to this view : 1 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 19 x 1 19 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryo stratix 1 x 1 1 LCs buffer_merger work 1 x 52 52 LCs 1 1 GND 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 89 178 LCs l_dpram_21_6_64_2_0 OPERATORS 1 x 1344 1344 Memory Bits lpm_mult_5 OPERATORS 1 x 1 1 lpm_mult_5 lpm_mult_7 OPERATORS 1 x 1 1 lpm_mult_7 stratix_lcell_arithmetic stratix 52 x 1 52 LCs stratix_lcell_counter stratix 6 x 1 6 LCs stratix_lcell_reg stratix 11 x 1 11 LCs stratix_lcell_sync_reg stratix 9 x 1 9 LCs yt_lut_4 work 1 x 98 98 LCs ******************************************************* Cell: yt_lut_4 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 98 Number of accumulated instances : 98 Number of ports : 18 Number of nets : 105 Number of instances : 98 Number of references to this view : 1 Cell Library References Total Area stratix_lcell_normal stratix 98 x 1 98 LCs ******************************************************* Cell: lpm_mult_5 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 36 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: lpm_mult_7 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 26 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: input_3 View: default_unfold_2869 Library: work ******************************************************* Total accumulated area : Number of LCs : 383 Number of Memory Bits : 1344 Number of accumulated instances : 417 Number of ports : 81 Number of nets : 383 Number of instances : 180 Number of references to this view : 1 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 19 x 1 19 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryo stratix 1 x 1 1 LCs buffer_merger work 1 x 52 52 LCs 1 1 GND 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 89 178 LCs l_dpram_21_6_64_2_0 OPERATORS 1 x 1344 1344 Memory Bits lpm_mult_11 OPERATORS 1 x 1 1 lpm_mult_11 lpm_mult_9 OPERATORS 1 x 1 1 lpm_mult_9 stratix_lcell_arithmetic stratix 52 x 1 52 LCs stratix_lcell_counter stratix 6 x 1 6 LCs stratix_lcell_normal stratix 74 x 1 74 LCs stratix_lcell_reg stratix 11 x 1 11 LCs stratix_lcell_sync_reg stratix 9 x 1 9 LCs ******************************************************* Cell: lpm_mult_9 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 36 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: lpm_mult_11 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 22 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: input_2 View: default_unfold_2868 Library: work ******************************************************* Total accumulated area : Number of LCs : 408 Number of Memory Bits : 1344 Number of accumulated instances : 442 Number of ports : 81 Number of nets : 408 Number of instances : 205 Number of references to this view : 1 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 19 x 1 19 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryo stratix 1 x 1 1 LCs buffer_merger work 1 x 52 52 LCs 1 1 GND 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 89 178 LCs l_dpram_21_6_64_2_0 OPERATORS 1 x 1344 1344 Memory Bits lpm_mult_13 OPERATORS 1 x 1 1 lpm_mult_13 lpm_mult_15 OPERATORS 1 x 1 1 lpm_mult_15 stratix_lcell_arithmetic stratix 52 x 1 52 LCs stratix_lcell_counter stratix 6 x 1 6 LCs stratix_lcell_normal stratix 99 x 1 99 LCs stratix_lcell_reg stratix 11 x 1 11 LCs stratix_lcell_sync_reg stratix 9 x 1 9 LCs ******************************************************* Cell: lpm_mult_13 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 36 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: lpm_mult_15 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 22 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: input_1 View: default_unfold_2867 Library: work ******************************************************* Total accumulated area : Number of LCs : 400 Number of Memory Bits : 1344 Number of accumulated instances : 434 Number of ports : 81 Number of nets : 402 Number of instances : 197 Number of references to this view : 1 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 19 x 1 19 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryo stratix 1 x 1 1 LCs buffer_merger work 1 x 52 52 LCs 1 1 GND 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 89 178 LCs l_dpram_21_6_64_2_0 OPERATORS 1 x 1344 1344 Memory Bits lpm_mult_17 OPERATORS 1 x 1 1 lpm_mult_17 lpm_mult_19 OPERATORS 1 x 1 1 lpm_mult_19 stratix_lcell_arithmetic stratix 52 x 1 52 LCs stratix_lcell_counter stratix 6 x 1 6 LCs stratix_lcell_normal stratix 91 x 1 91 LCs stratix_lcell_reg stratix 11 x 1 11 LCs stratix_lcell_sync_reg stratix 9 x 1 9 LCs ******************************************************* Cell: lpm_mult_17 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 36 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: lpm_mult_19 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 26 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: input_0 View: default_unfold_2866 Library: work ******************************************************* Total accumulated area : Number of LCs : 377 Number of Memory Bits : 1344 Number of accumulated instances : 411 Number of ports : 81 Number of nets : 380 Number of instances : 174 Number of references to this view : 1 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 19 x 1 19 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryo stratix 1 x 1 1 LCs buffer_merger work 1 x 52 52 LCs 1 1 GND 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 89 178 LCs l_dpram_21_6_64_2_0 OPERATORS 1 x 1344 1344 Memory Bits lpm_mult_21 OPERATORS 1 x 1 1 lpm_mult_21 lpm_mult_23 OPERATORS 1 x 1 1 lpm_mult_23 stratix_lcell_arithmetic stratix 52 x 1 52 LCs stratix_lcell_counter stratix 6 x 1 6 LCs stratix_lcell_normal stratix 68 x 1 68 LCs stratix_lcell_reg stratix 11 x 1 11 LCs stratix_lcell_sync_reg stratix 9 x 1 9 LCs ******************************************************* Cell: lpm_mult_21 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 36 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: lpm_mult_23 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 28 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: reconst View: default_unfold_2185 Library: work ******************************************************* Total accumulated area : Number of LCs : 821 Number of Memory Bits : 672 Number of accumulated instances : 838 Number of ports : 268 Number of nets : 1188 Number of instances : 801 Number of references to this view : 1 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 7 x 1 7 NOT VCC stratix 1 x 1 1 VCC acoeff_lut_2 work 1 x 38 38 LCs altshift_taps_42_16_1_1_0 OPERATORS 1 x 672 672 Memory Bits lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED work 1 x 1 1 lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED lpm_mult_13_13_9_18_SIGNED_1_LPM_MULT_UNUSED work 6 x 1 6 lpm_mult_13_13_9_18_SIGNED_1_LPM_MULT_UNUSED stratix_lcell_arithmetic stratix 90 x 1 90 LCs stratix_lcell_normal stratix 371 x 1 371 LCs stratix_lcell_reg stratix 304 x 1 304 LCs stratix_lcell_sync_reg stratix 18 x 1 18 LCs ******************************************************* Cell: acoeff_lut_2 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 38 Number of accumulated instances : 38 Number of ports : 18 Number of nets : 43 Number of instances : 38 Number of references to this view : 1 Cell Library References Total Area stratix_lcell_normal stratix 38 x 1 38 LCs ******************************************************* Cell: lpm_mult_13_13_9_18_SIGNED_1_LPM_MULT_UNUSED View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of ports : 55 Number of nets : 0 Number of instances : 0 Number of references to this view : 6 ******************************************************* Cell: lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of ports : 76 Number of nets : 0 Number of instances : 0 Number of references to this view : 1 ******************************************************* Cell: altshift_taps_42_16_1_1_0 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of Memory Bits : 672 Number of ports : 127 Number of nets : 0 Number of instances : 0 Number of references to this view : 4 ******************************************************* Cell: zch_table_5_2 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 27 Number of accumulated instances : 27 Number of ports : 10 Number of nets : 34 Number of instances : 27 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 27 x 1 27 LCs ******************************************************* Cell: sorter_8 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 421 Number of accumulated instances : 503 Number of ports : 42 Number of nets : 525 Number of instances : 503 Number of references to this view : 36 Cell Library References Total Area NOT stratix 82 x 1 82 NOT stratix_lcell_arithmetic stratix 80 x 1 80 LCs stratix_lcell_normal stratix 338 x 1 338 LCs stratix_lcell_sync_reg stratix 3 x 1 3 LCs ******************************************************* Cell: zch_table_5_1 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 26 Number of accumulated instances : 26 Number of ports : 10 Number of nets : 33 Number of instances : 26 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 26 x 1 26 LCs ******************************************************* Cell: zch_table_5_0 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 28 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 28 x 1 28 LCs ******************************************************* Cell: zch_table_4_2 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 25 Number of accumulated instances : 25 Number of ports : 10 Number of nets : 32 Number of instances : 25 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 25 x 1 25 LCs ******************************************************* Cell: zch_table_4_1 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 29 Number of accumulated instances : 29 Number of ports : 10 Number of nets : 36 Number of instances : 29 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 29 x 1 29 LCs ******************************************************* Cell: zch_table_4_0 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 26 Number of accumulated instances : 26 Number of ports : 10 Number of nets : 33 Number of instances : 26 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 26 x 1 26 LCs ******************************************************* Cell: zch_table_3_2 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 26 Number of accumulated instances : 26 Number of ports : 10 Number of nets : 33 Number of instances : 26 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 26 x 1 26 LCs ******************************************************* Cell: zch_table_3_1 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 24 Number of accumulated instances : 24 Number of ports : 10 Number of nets : 31 Number of instances : 24 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 24 x 1 24 LCs ******************************************************* Cell: zch_table_3_0 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 23 Number of accumulated instances : 23 Number of ports : 10 Number of nets : 30 Number of instances : 23 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 23 x 1 23 LCs ******************************************************* Cell: zch_table_2_0 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 13 Number of accumulated instances : 13 Number of ports : 10 Number of nets : 20 Number of instances : 13 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 13 x 1 13 LCs ******************************************************* Cell: zch_table_1_2 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 29 Number of accumulated instances : 29 Number of ports : 10 Number of nets : 36 Number of instances : 29 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 29 x 1 29 LCs ******************************************************* Cell: zch_table_1_1 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 27 Number of accumulated instances : 27 Number of ports : 10 Number of nets : 34 Number of instances : 27 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 27 x 1 27 LCs ******************************************************* Cell: zch_table_1_0 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 25 Number of accumulated instances : 25 Number of ports : 10 Number of nets : 32 Number of instances : 25 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 25 x 1 25 LCs ******************************************************* Cell: zch_table_0_2 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 21 Number of accumulated instances : 21 Number of ports : 10 Number of nets : 28 Number of instances : 21 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 21 x 1 21 LCs ******************************************************* Cell: zch_table_0_1 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 26 Number of accumulated instances : 26 Number of ports : 10 Number of nets : 33 Number of instances : 26 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 26 x 1 26 LCs ******************************************************* Cell: zch_table_0_0 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 19 Number of accumulated instances : 19 Number of ports : 10 Number of nets : 26 Number of instances : 19 Number of references to this view : 2 Cell Library References Total Area stratix_lcell_normal stratix 19 x 1 19 LCs ******************************************************* Cell: matching_memory View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 111 Number of Memory Bits : 3328 Number of accumulated instances : 139 Number of ports : 87 Number of nets : 229 Number of instances : 139 Number of references to this view : 60 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 25 x 1 25 NOT l_dpram_26_6_64_2_0 OPERATORS 2 x 1664 3328 Memory Bits stratix_lcell_normal stratix 99 x 1 99 LCs stratix_lcell_sync_reg stratix 12 x 1 12 LCs ******************************************************* Cell: l_dpram_26_6_64_2_0 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of Memory Bits : 1664 Number of ports : 66 Number of nets : 0 Number of instances : 0 Number of references to this view : 13 ******************************************************* Cell: matching_memory View: default_unfold_2672_0 Library: work ******************************************************* Total accumulated area : Number of LCs : 105 Number of Memory Bits : 3328 Number of accumulated instances : 133 Number of ports : 87 Number of nets : 209 Number of instances : 133 Number of references to this view : 12 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 25 x 1 25 NOT l_dpram_26_6_64_2_0 OPERATORS 2 x 1664 3328 Memory Bits stratix_lcell_normal stratix 93 x 1 93 LCs stratix_lcell_sync_reg stratix 12 x 1 12 LCs ******************************************************* Cell: matching_logic_3_0 View: default_unfold_2202 Library: work ******************************************************* Total accumulated area : Number of LCs : 806 Number of accumulated instances : 811 Number of ports : 265 Number of nets : 1050 Number of instances : 811 Number of references to this view : 4 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 3 x 1 3 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryi stratix 1 x 1 1 LCs atom_lcell_carryo stratix 4 x 1 4 LCs stratix_lcell_arithmetic stratix 607 x 1 607 LCs stratix_lcell_normal stratix 194 x 1 194 LCs ******************************************************* Cell: matching_logic_2_8 View: default_unfold_2209 Library: work ******************************************************* Total accumulated area : Number of LCs : 806 Number of accumulated instances : 811 Number of ports : 265 Number of nets : 1050 Number of instances : 811 Number of references to this view : 4 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 3 x 1 3 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryi stratix 1 x 1 1 LCs atom_lcell_carryo stratix 4 x 1 4 LCs stratix_lcell_arithmetic stratix 607 x 1 607 LCs stratix_lcell_normal stratix 194 x 1 194 LCs ******************************************************* Cell: matching_logic_1_12 View: default_unfold_2219 Library: work ******************************************************* Total accumulated area : Number of LCs : 806 Number of accumulated instances : 811 Number of ports : 265 Number of nets : 1050 Number of instances : 811 Number of references to this view : 4 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 3 x 1 3 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryi stratix 1 x 1 1 LCs atom_lcell_carryo stratix 3 x 1 3 LCs stratix_lcell_arithmetic stratix 608 x 1 608 LCs stratix_lcell_normal stratix 194 x 1 194 LCs ******************************************************* Cell: seed_merger View: default_unfold_2616_0 Library: work ******************************************************* Total accumulated area : Number of LCs : 189 Number of Memory Bits : 1224 Number of accumulated instances : 194 Number of ports : 219 Number of nets : 517 Number of instances : 194 Number of references to this view : 6 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 1 x 1 1 NOT l_dpram_51_3_8_2_0 OPERATORS 3 x 408 1224 Memory Bits stratix_lcell_arithmetic stratix 30 x 1 30 LCs stratix_lcell_counter stratix 18 x 1 18 LCs stratix_lcell_normal stratix 138 x 1 138 LCs stratix_lcell_reg stratix 3 x 1 3 LCs ******************************************************* Cell: l_dpram_51_3_8_2_0 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of Memory Bits : 408 Number of ports : 110 Number of nets : 0 Number of instances : 0 Number of references to this view : 10 ******************************************************* Cell: uniquifier_52 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 168 Number of accumulated instances : 170 Number of ports : 110 Number of nets : 228 Number of instances : 170 Number of references to this view : 6 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 1 x 1 1 NOT stratix_lcell_arithmetic stratix 9 x 1 9 LCs stratix_lcell_normal stratix 53 x 1 53 LCs stratix_lcell_reg stratix 106 x 1 106 LCs ******************************************************* Cell: zch_merger View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 238 Number of Memory Bits : 1248 Number of accumulated instances : 247 Number of ports : 220 Number of nets : 610 Number of instances : 247 Number of references to this view : 2 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 1 x 1 1 NOT VCC stratix 1 x 1 1 VCC atom_lcell_carryi stratix 3 x 1 3 LCs atom_lcell_carryo stratix 2 x 1 2 LCs l_dpram_52_3_8_2_0 OPERATORS 3 x 416 1248 Memory Bits lpm_mult_25 OPERATORS 3 x 1 3 lpm_mult_25 stratix_lcell_arithmetic stratix 62 x 1 62 LCs stratix_lcell_counter stratix 18 x 1 18 LCs stratix_lcell_normal stratix 150 x 1 150 LCs stratix_lcell_reg stratix 3 x 1 3 LCs ******************************************************* Cell: lpm_mult_25 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of ports : 14 Number of nets : 0 Number of instances : 0 Number of references to this view : 10 ******************************************************* Cell: l_dpram_52_3_8_2_0 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of Memory Bits : 416 Number of ports : 112 Number of nets : 0 Number of instances : 0 Number of references to this view : 10 ******************************************************* Cell: uniquifier_53 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 170 Number of accumulated instances : 172 Number of ports : 112 Number of nets : 231 Number of instances : 172 Number of references to this view : 2 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 1 x 1 1 NOT stratix_lcell_arithmetic stratix 9 x 1 9 LCs stratix_lcell_normal stratix 53 x 1 53 LCs stratix_lcell_reg stratix 108 x 1 108 LCs ******************************************************* Cell: zch_resorter View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 91 Number of Memory Bits : 1664 Number of accumulated instances : 95 Number of ports : 102 Number of nets : 267 Number of instances : 95 Number of references to this view : 2 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 1 x 1 1 NOT l_dpram_52_4_16_2_0 OPERATORS 2 x 832 1664 Memory Bits stratix_lcell_arithmetic stratix 10 x 1 10 LCs stratix_lcell_counter stratix 16 x 1 16 LCs stratix_lcell_normal stratix 64 x 1 64 LCs stratix_lcell_reg stratix 1 x 1 1 LCs ******************************************************* Cell: l_dpram_52_4_16_2_0 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of Memory Bits : 832 Number of ports : 114 Number of nets : 0 Number of instances : 0 Number of references to this view : 7 ******************************************************* Cell: uniquifier_42 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 148 Number of accumulated instances : 150 Number of ports : 90 Number of nets : 198 Number of instances : 150 Number of references to this view : 2 Cell Library References Total Area GND stratix 1 x 1 1 GND NOT stratix 1 x 1 1 NOT stratix_lcell_arithmetic stratix 9 x 1 9 LCs stratix_lcell_normal stratix 53 x 1 53 LCs stratix_lcell_reg stratix 86 x 1 86 LCs ******************************************************* Cell: l_dpram_7_6_64_2_0 View: LPM Library: OPERATORS ******************************************************* Total accumulated area : Number of Memory Bits : 448 Number of ports : 28 Number of nets : 0 Number of instances : 0 Number of references to this view : 55 *********************************************** Device Utilization for EP1S30F780C *********************************************** Resource Used Avail Utilization ----------------------------------------------- IOs 186 577 32.24% LCs 26267 32470 80.90% Memory Bits 203096 3317184 6.12% DSP block 9-bit elems 0 96 0.00% ----------------------------------------------- Using default wire table: stratix_default Clock Frequency Report Clock : Frequency ------------------------------------ clk : 53.4 MHz clk1_in(5) : 260.1 MHz clk1_in(4) : 260.1 MHz clk1_in(3) : 260.1 MHz clk1_in(2) : 260.1 MHz clk1_in(1) : 260.1 MHz clk1_in(0) : 260.1 MHz clk0_in(5) : 260.1 MHz clk0_in(4) : 260.1 MHz clk0_in(3) : 260.1 MHz clk0_in(2) : 260.1 MHz clk0_in(1) : 260.1 MHz clk0_in(0) : 260.1 MHz input_gen_5_input_inst/inputcontrol1/NOT_clk_in : 500.2 MHz input_gen_5_input_inst/inputcontrol0/NOT_clk_in : 500.2 MHz input_gen_4_input_inst/inputcontrol1/NOT_clk_in : 500.2 MHz input_gen_4_input_inst/inputcontrol0/NOT_clk_in : 500.2 MHz input_gen_3_input_inst/inputcontrol1/NOT_clk_in : 500.2 MHz input_gen_3_input_inst/inputcontrol0/NOT_clk_in : 500.2 MHz input_gen_2_input_inst/inputcontrol1/NOT_clk_in : 500.2 MHz input_gen_2_input_inst/inputcontrol0/NOT_clk_in : 500.2 MHz input_gen_1_input_inst/inputcontrol1/NOT_clk_in : 500.2 MHz input_gen_1_input_inst/inputcontrol0/NOT_clk_in : 500.2 MHz input_gen_0_input_inst/inputcontrol1/NOT_clk_in : 500.2 MHz input_gen_0_input_inst/inputcontrol0/NOT_clk_in : 500.2 MHz Slack Table at End Points End points Slack Arrival Required rise fall rise fall match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(4)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(0)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(2)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(2)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(3)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(4)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(5)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(4)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(0)/dataa : 6.28 18.22 18.22 24.50 24.50 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(2)/dataa : 6.28 18.22 18.22 24.50 24.50 Critical Path Report Critical path #1, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1321/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1259/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1441/Y NOT 0.00 18.22 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(3)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #2, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_2_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/ix1323/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/ix1260/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/ix1446/Y NOT 0.00 18.22 up 0.55 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(2)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #3, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1325/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1262/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1456/Y NOT 0.00 18.22 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(0)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #4, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1319/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1258/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1436/Y NOT 0.00 18.22 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(4)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #5, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1317/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1257/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1431/Y NOT 0.00 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(5)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #6, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1319/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1258/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1436/Y NOT 0.00 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(4)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #7, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1321/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1259/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1441/Y NOT 0.00 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(3)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #8, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1323/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1260/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1446/Y NOT 0.00 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(2)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #9, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1323/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1260/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/ix1446/Y NOT 0.00 18.22 up 0.55 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(2)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 ------------------------------------------------------------------------------------------------------- Critical path #10, (path slack = 6.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix77/q(10) GENERIC_BLACK_BOX 0.00 0.00 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix159/combout stratix_lcell_normal 1.06 1.06 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix125/combout stratix_lcell_normal 0.86 1.92 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix11/combout stratix_lcell_normal 1.00 2.92 up 0.82 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4287_ix47/combout stratix_lcell_arithmetic 0.86 3.78 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix122/combout stratix_lcell_normal 0.95 4.73 up 0.67 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix57/combout stratix_lcell_normal 0.71 5.44 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix48/combout stratix_lcell_normal 1.12 6.56 up 0.73 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix145/combout stratix_lcell_normal 1.03 7.59 up 0.64 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix79/combout stratix_lcell_normal 0.94 8.53 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix270/cout atom_lcell_carryo 0.47 9.00 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix12/combout stratix_lcell_arithmetic 0.40 9.40 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix15/combout stratix_lcell_normal 0.83 10.23 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix1066/cout atom_lcell_carryo 0.47 10.69 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix17/cout stratix_lcell_arithmetic 0.03 10.72 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4425_ix19/combout stratix_lcell_arithmetic 0.40 11.12 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix88/combout stratix_lcell_normal 1.10 12.22 up 1.03 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix89/combout stratix_lcell_normal 0.65 12.87 up 0.58 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix154/combout stratix_lcell_normal 0.73 13.60 up 0.55 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix143/combout stratix_lcell_normal 0.94 14.54 up 0.76 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1337/combout stratix_lcell_normal 0.83 15.37 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1335/combout stratix_lcell_normal 0.62 15.99 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1287/combout stratix_lcell_normal 0.77 16.77 up 0.70 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1325/combout stratix_lcell_normal 0.73 17.49 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1262/combout stratix_lcell_normal 0.73 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/ix1456/Y NOT 0.00 18.22 up 0.55 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_a(0)/dataa stratix_lcell_sync_reg 0.00 18.22 up 0.00 data arrival time 18.22 data required time (default specified - setup time) 24.50 ------------------------------------------------------------------------------------------------------- data required time 24.50 data arrival time 18.22 ---------- slack 6.28 -------------------------------------------------------------------------------------------------------