******************************************************* Cell: toplevel View: default Library: work ******************************************************* Total accumulated area : Number of BUFGP : 13 Number of Dffs or Latches : 6501 Number of Function Generators : 49554 Number of IBUF : 113 Number of MUX CARRYs : 6867 Number of MUXF5 : 3106 Number of MUXF6 : 65 Number of OBUF : 60 Number of accumulated instances : 46050 Number of ports : 186 Number of nets : 5091 Number of instances : 1071 Number of references to this view : 0 Cell Library References Total Area BUFGP xcv2 13 x 1 13 BUFGP FD xcv2 9 x 1 9 Dffs or Latches FDCE xcv2 324 x 1 324 Dffs or Latches GND xcv2 1 x 1 1 GND IBUF xcv2 113 x 1 113 IBUF LUT1 xcv2 7 x 1 7 Function Generators LUT2 xcv2 10 x 1 10 Function Generators LUT3 xcv2 69 x 1 69 Function Generators LUT4 xcv2 202 x 1 202 Function Generators MUXF5 xcv2 22 x 1 22 MUXF5 OBUF xcv2 60 x 1 60 OBUF RAM64X1D xcv2 126 x 8 1008 Function Generators VCC xcv2 1 x 1 1 VCC input_0 work 1 x 1 1 GND 1 1 VCC 6 6 MUXF7 12 12 MUXF6 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 207 207 Dffs or Latches 42 42 MUXF5 408 408 Function Generators 299 299 gates input_1 work 1 x 1 1 GND 1 1 VCC 5 5 MUXF7 16 16 MUXF6 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 207 207 Dffs or Latches 38 38 MUXF5 390 390 Function Generators 281 281 gates input_2 work 1 x 1 1 GND 1 1 VCC 8 8 MUXF7 17 17 MUXF6 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 207 207 Dffs or Latches 40 40 MUXF5 373 373 Function Generators 264 264 gates input_3 work 1 x 1 1 GND 1 1 VCC 6 6 MUXF7 15 15 MUXF6 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 207 207 Dffs or Latches 36 36 MUXF5 368 368 Function Generators 259 259 gates input_4 work 1 x 1 1 VCC 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 GND 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 207 207 Dffs or Latches 17 17 MUXF5 499 499 Function Generators 390 390 gates input_5 work 1 x 1 1 VCC 2 2 Block Multipliers 47 47 MUX CARRYs 48 48 XORCY 2 2 GND 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED 207 207 Dffs or Latches 19 19 MUXF5 495 495 Function Generators 386 386 gates matching_logic_1_12 work 3 x 797 2391 gates 1 3 GND 1 3 VCC 16 48 MUXF5 10 30 XORCY 500 1500 MUX CARRYs 799 2397 Function Generators matching_logic_2_8 work 3 x 797 2391 gates 1 3 GND 1 3 VCC 16 48 MUXF5 10 30 XORCY 500 1500 MUX CARRYs 799 2397 Function Generators matching_logic_3_0 work 3 x 796 2388 gates 1 3 GND 1 3 VCC 17 51 MUXF5 10 30 XORCY 500 1500 MUX CARRYs 805 2415 Function Generators matching_memory work 9 x 99 891 gates 1 9 GND 1 9 VCC 2 18 MUXF5 19 171 Dffs or Latches 6 54 MUX CARRYs 412 3708 Function Generators matching_memory work 45 x 105 4725 gates 1 45 GND 1 45 VCC 2 90 MUXF5 19 855 Dffs or Latches 6 270 MUX CARRYs 523 23535 Function Generators reconst work 1 x 1 1 VCC 1 1 GND 2 2 MUXF6 448 448 Dffs or Latches 85 85 MUX CARRYs 90 90 XORCY 1 1 lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED 6 6 lpm_mult_13_13_9_18_SIGNED_1_LPM_MULT_UNUSED 179 179 MUXF5 757 757 Function Generators 715 715 gates seed_merger work 3 x 186 558 gates 1 3 GND 53 159 MUXF5 30 90 Dffs or Latches 21 63 MUX CARRYs 493 1479 Function Generators sorter_8 work 18 x 420 7560 gates 1 18 GND 122 2196 MUXF5 155 2790 Dffs or Latches 80 1440 MUX CARRYs 421 7578 Function Generators uniquifier_42 work 1 x 49 49 gates 1 1 VCC 1 1 GND 2 2 MUXF5 87 87 Dffs or Latches 4 4 XORCY 22 22 MUX CARRYs 49 49 Function Generators uniquifier_52 work 3 x 49 147 gates 1 3 VCC 1 3 GND 2 6 MUXF5 107 321 Dffs or Latches 4 12 XORCY 22 66 MUX CARRYs 49 147 Function Generators uniquifier_53 work 1 x 49 49 gates 1 1 VCC 1 1 GND 2 2 MUXF5 109 109 Dffs or Latches 4 4 XORCY 22 22 MUX CARRYs 49 49 Function Generators zch_merger work 1 x 242 242 gates 1 1 VCC 1 1 GND 3 3 MUXF5 30 30 Dffs or Latches 26 26 XORCY 52 52 MUX CARRYs 555 555 Function Generators 3 3 Block Multipliers zch_resorter work 1 x 88 88 gates 1 1 GND 1 1 VCC 1 1 MUXF5 25 25 Dffs or Latches 11 11 MUX CARRYs 297 297 Function Generators zch_table_0_0 work 1 x 17 17 gates 20 20 Function Generators 5 5 MUXF5 zch_table_0_1 work 1 x 22 22 gates 25 25 Function Generators 3 3 MUXF5 zch_table_0_2 work 1 x 17 17 gates 20 20 Function Generators 5 5 MUXF5 zch_table_1_0 work 1 x 19 19 gates 22 22 Function Generators 1 1 MUXF6 5 5 MUXF5 zch_table_1_1 work 1 x 20 20 gates 23 23 Function Generators 1 1 GND 7 7 MUXF5 zch_table_1_2 work 1 x 24 24 gates 27 27 Function Generators 5 5 MUXF5 zch_table_2_0 work 1 x 12 12 gates 15 15 Function Generators zch_table_3_0 work 1 x 19 19 gates 22 22 Function Generators 5 5 MUXF5 zch_table_3_1 work 1 x 20 20 gates 23 23 Function Generators 6 6 MUXF5 zch_table_3_2 work 1 x 19 19 gates 22 22 Function Generators 6 6 MUXF5 zch_table_4_0 work 1 x 19 19 gates 22 22 Function Generators 6 6 MUXF5 zch_table_4_1 work 1 x 21 21 gates 24 24 Function Generators 1 1 VCC 7 7 MUXF5 zch_table_4_2 work 1 x 19 19 gates 22 22 Function Generators 1 1 GND 8 8 MUXF5 zch_table_5_0 work 1 x 21 21 gates 24 24 Function Generators 1 1 MUXF6 7 7 MUXF5 zch_table_5_1 work 1 x 25 25 gates 28 28 Function Generators 1 1 MUXF6 8 8 MUXF5 zch_table_5_2 work 1 x 20 20 gates 23 23 Function Generators 6 6 MUXF5 ******************************************************* Cell: input_5 View: default_unfold_2871 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 495 Number of MUX CARRYs : 47 Number of MUXF5 : 19 Number of accumulated instances : 732 Number of ports : 81 Number of nets : 372 Number of instances : 223 Number of references to this view : 1 Cell Library References Total Area FD xcv2 26 x 1 26 Dffs or Latches FDC xcv2 1 x 1 1 Dffs or Latches FDCE xcv2 6 x 1 6 Dffs or Latches FDR xcv2 1 x 1 1 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 3 x 1 3 Function Generators LUT1_L xcv2 19 x 1 19 Function Generators LUT2 xcv2 12 x 1 12 Function Generators LUT2_L xcv2 33 x 1 33 Function Generators LUT3 xcv2 2 x 1 2 Function Generators LUT4 xcv2 4 x 1 4 Function Generators MULT18X18 xcv2 2 x 1 2 Block Multipliers MUXCY_L xcv2 47 x 1 47 MUX CARRYs RAM64X1D xcv2 13 x 8 104 Function Generators VCC xcv2 1 x 1 1 VCC XORCY xcv2 48 x 1 48 XORCY buffer_merger work 1 x 55 55 gates 56 56 Function Generators 1 1 MUXF5 3 3 Dffs or Latches 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 42 84 gates 42 84 Function Generators 1 2 MUXF5 85 170 Dffs or Latches yt_lut_5 work 1 x 175 175 gates 178 178 Function Generators 1 1 GND 16 16 MUXF5 ******************************************************* Cell: inputcontrol View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 85 Number of Function Generators : 42 Number of MUXF5 : 1 Number of accumulated instances : 128 Number of ports : 45 Number of nets : 140 Number of instances : 128 Number of references to this view : 12 Cell Library References Total Area FDC xcv2 43 x 1 43 Dffs or Latches FDCE xcv2 1 x 1 1 Dffs or Latches FDCE_1 xcv2 33 x 1 33 Dffs or Latches FDC_1 xcv2 8 x 1 8 Dffs or Latches LUT1 xcv2 2 x 1 2 Function Generators LUT2 xcv2 16 x 1 16 Function Generators LUT3 xcv2 2 x 1 2 Function Generators LUT4 xcv2 22 x 1 22 Function Generators MUXF5 xcv2 1 x 1 1 MUXF5 ******************************************************* Cell: buffer_merger View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 3 Number of Function Generators : 56 Number of MUXF5 : 1 Number of accumulated instances : 62 Number of ports : 105 Number of nets : 197 Number of instances : 62 Number of references to this view : 6 Cell Library References Total Area FDC xcv2 3 x 1 3 Dffs or Latches LUT1 xcv2 2 x 1 2 Function Generators LUT2 xcv2 6 x 1 6 Function Generators LUT3 xcv2 2 x 1 2 Function Generators LUT4 xcv2 46 x 1 46 Function Generators MUXF5 xcv2 1 x 1 1 MUXF5 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED work 2 x 1 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED ******************************************************* Cell: lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of ports : 80 Number of nets : 0 Number of instances : 0 Number of references to this view : 2 ******************************************************* Cell: yt_lut_5 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 178 Number of MUXF5 : 16 Number of accumulated instances : 195 Number of ports : 18 Number of nets : 202 Number of instances : 195 Number of references to this view : 1 Cell Library References Total Area GND xcv2 1 x 1 1 GND LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 11 x 1 11 Function Generators LUT3 xcv2 10 x 1 10 Function Generators LUT4 xcv2 154 x 1 154 Function Generators MUXF5 xcv2 16 x 1 16 MUXF5 ******************************************************* Cell: input_4 View: default_unfold_2870 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 499 Number of MUX CARRYs : 47 Number of MUXF5 : 17 Number of accumulated instances : 734 Number of ports : 81 Number of nets : 371 Number of instances : 223 Number of references to this view : 1 Cell Library References Total Area FD xcv2 26 x 1 26 Dffs or Latches FDC xcv2 1 x 1 1 Dffs or Latches FDCE xcv2 6 x 1 6 Dffs or Latches FDR xcv2 1 x 1 1 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 3 x 1 3 Function Generators LUT1_L xcv2 19 x 1 19 Function Generators LUT2 xcv2 12 x 1 12 Function Generators LUT2_L xcv2 33 x 1 33 Function Generators LUT3 xcv2 2 x 1 2 Function Generators LUT4 xcv2 4 x 1 4 Function Generators MULT18X18 xcv2 2 x 1 2 Block Multipliers MUXCY_L xcv2 47 x 1 47 MUX CARRYs RAM64X1D xcv2 13 x 8 104 Function Generators VCC xcv2 1 x 1 1 VCC XORCY xcv2 48 x 1 48 XORCY buffer_merger work 1 x 55 55 gates 56 56 Function Generators 1 1 MUXF5 3 3 Dffs or Latches 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 42 84 gates 42 84 Function Generators 1 2 MUXF5 85 170 Dffs or Latches yt_lut_4 work 1 x 179 179 gates 182 182 Function Generators 1 1 GND 14 14 MUXF5 ******************************************************* Cell: yt_lut_4 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 182 Number of MUXF5 : 14 Number of accumulated instances : 197 Number of ports : 18 Number of nets : 204 Number of instances : 197 Number of references to this view : 1 Cell Library References Total Area GND xcv2 1 x 1 1 GND LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 12 x 1 12 Function Generators LUT3 xcv2 20 x 1 20 Function Generators LUT4 xcv2 147 x 1 147 Function Generators MUXF5 xcv2 14 x 1 14 MUXF5 ******************************************************* Cell: input_3 View: default_unfold_2869 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 368 Number of MUX CARRYs : 47 Number of MUXF5 : 36 Number of MUXF6 : 15 Number of accumulated instances : 642 Number of ports : 81 Number of nets : 463 Number of instances : 327 Number of references to this view : 1 Cell Library References Total Area FD xcv2 26 x 1 26 Dffs or Latches FDC xcv2 1 x 1 1 Dffs or Latches FDCE xcv2 6 x 1 6 Dffs or Latches FDR xcv2 1 x 1 1 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 6 x 1 6 Function Generators LUT1_L xcv2 19 x 1 19 Function Generators LUT2 xcv2 13 x 1 13 Function Generators LUT2_L xcv2 33 x 1 33 Function Generators LUT3 xcv2 4 x 1 4 Function Generators LUT4 xcv2 49 x 1 49 Function Generators MULT18X18 xcv2 2 x 1 2 Block Multipliers MUXCY_L xcv2 47 x 1 47 MUX CARRYs MUXF5 xcv2 33 x 1 33 MUXF5 MUXF6 xcv2 15 x 1 15 MUXF6 MUXF7 xcv2 6 x 1 6 MUXF7 RAM64X1D xcv2 13 x 8 104 Function Generators VCC xcv2 1 x 1 1 VCC XORCY xcv2 48 x 1 48 XORCY buffer_merger work 1 x 55 55 gates 56 56 Function Generators 1 1 MUXF5 3 3 Dffs or Latches 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 42 84 gates 42 84 Function Generators 1 2 MUXF5 85 170 Dffs or Latches ******************************************************* Cell: input_2 View: default_unfold_2868 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 373 Number of MUX CARRYs : 47 Number of MUXF5 : 40 Number of MUXF6 : 17 Number of accumulated instances : 655 Number of ports : 81 Number of nets : 476 Number of instances : 340 Number of references to this view : 1 Cell Library References Total Area FD xcv2 26 x 1 26 Dffs or Latches FDC xcv2 1 x 1 1 Dffs or Latches FDCE xcv2 6 x 1 6 Dffs or Latches FDR xcv2 1 x 1 1 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 6 x 1 6 Function Generators LUT1_L xcv2 19 x 1 19 Function Generators LUT2 xcv2 12 x 1 12 Function Generators LUT2_L xcv2 33 x 1 33 Function Generators LUT3 xcv2 3 x 1 3 Function Generators LUT4 xcv2 56 x 1 56 Function Generators MULT18X18 xcv2 2 x 1 2 Block Multipliers MUXCY_L xcv2 47 x 1 47 MUX CARRYs MUXF5 xcv2 37 x 1 37 MUXF5 MUXF6 xcv2 17 x 1 17 MUXF6 MUXF7 xcv2 8 x 1 8 MUXF7 RAM64X1D xcv2 13 x 8 104 Function Generators VCC xcv2 1 x 1 1 VCC XORCY xcv2 48 x 1 48 XORCY buffer_merger work 1 x 55 55 gates 56 56 Function Generators 1 1 MUXF5 3 3 Dffs or Latches 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 42 84 gates 42 84 Function Generators 1 2 MUXF5 85 170 Dffs or Latches ******************************************************* Cell: input_1 View: default_unfold_2867 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 390 Number of MUX CARRYs : 47 Number of MUXF5 : 38 Number of MUXF6 : 16 Number of accumulated instances : 666 Number of ports : 81 Number of nets : 489 Number of instances : 351 Number of references to this view : 1 Cell Library References Total Area FD xcv2 26 x 1 26 Dffs or Latches FDC xcv2 1 x 1 1 Dffs or Latches FDCE xcv2 6 x 1 6 Dffs or Latches FDR xcv2 1 x 1 1 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 6 x 1 6 Function Generators LUT1_L xcv2 19 x 1 19 Function Generators LUT2 xcv2 18 x 1 18 Function Generators LUT2_L xcv2 33 x 1 33 Function Generators LUT3 xcv2 6 x 1 6 Function Generators LUT4 xcv2 64 x 1 64 Function Generators MULT18X18 xcv2 2 x 1 2 Block Multipliers MUXCY_L xcv2 47 x 1 47 MUX CARRYs MUXF5 xcv2 35 x 1 35 MUXF5 MUXF6 xcv2 16 x 1 16 MUXF6 MUXF7 xcv2 5 x 1 5 MUXF7 RAM64X1D xcv2 13 x 8 104 Function Generators VCC xcv2 1 x 1 1 VCC XORCY xcv2 48 x 1 48 XORCY buffer_merger work 1 x 55 55 gates 56 56 Function Generators 1 1 MUXF5 3 3 Dffs or Latches 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 42 84 gates 42 84 Function Generators 1 2 MUXF5 85 170 Dffs or Latches ******************************************************* Cell: input_0 View: default_unfold_2866 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 207 Number of Function Generators : 408 Number of MUX CARRYs : 47 Number of MUXF5 : 42 Number of MUXF6 : 12 Number of accumulated instances : 685 Number of ports : 81 Number of nets : 509 Number of instances : 370 Number of references to this view : 1 Cell Library References Total Area FD xcv2 26 x 1 26 Dffs or Latches FDC xcv2 1 x 1 1 Dffs or Latches FDCE xcv2 6 x 1 6 Dffs or Latches FDR xcv2 1 x 1 1 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 7 x 1 7 Function Generators LUT1_L xcv2 19 x 1 19 Function Generators LUT2 xcv2 14 x 1 14 Function Generators LUT2_L xcv2 33 x 1 33 Function Generators LUT3 xcv2 12 x 1 12 Function Generators LUT4 xcv2 79 x 1 79 Function Generators MULT18X18 xcv2 2 x 1 2 Block Multipliers MUXCY_L xcv2 47 x 1 47 MUX CARRYs MUXF5 xcv2 39 x 1 39 MUXF5 MUXF6 xcv2 12 x 1 12 MUXF6 MUXF7 xcv2 6 x 1 6 MUXF7 RAM64X1D xcv2 13 x 8 104 Function Generators VCC xcv2 1 x 1 1 VCC XORCY xcv2 48 x 1 48 XORCY buffer_merger work 1 x 55 55 gates 56 56 Function Generators 1 1 MUXF5 3 3 Dffs or Latches 2 2 lpm_fifo_dc_32_5_32_OFF_LPM_FIFO_DC_UNUSED inputcontrol work 2 x 42 84 gates 42 84 Function Generators 1 2 MUXF5 85 170 Dffs or Latches ******************************************************* Cell: reconst View: default_unfold_2185 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 448 Number of Function Generators : 757 Number of MUX CARRYs : 85 Number of MUXF5 : 179 Number of MUXF6 : 2 Number of accumulated instances : 1570 Number of ports : 268 Number of nets : 1780 Number of instances : 1526 Number of references to this view : 1 Cell Library References Total Area FD xcv2 412 x 1 412 Dffs or Latches FDC xcv2 34 x 1 34 Dffs or Latches FDR xcv2 2 x 1 2 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 4 x 1 4 Function Generators LUT2 xcv2 28 x 1 28 Function Generators LUT2_L xcv2 90 x 1 90 Function Generators LUT3 xcv2 109 x 1 109 Function Generators LUT4 xcv2 450 x 1 450 Function Generators MUXCY_L xcv2 85 x 1 85 MUX CARRYs MUXF5 xcv2 168 x 1 168 MUXF5 MUXF6 xcv2 2 x 1 2 MUXF6 SRLC16 xcv2 42 x 1 42 Function Generators VCC xcv2 1 x 1 1 VCC XORCY xcv2 90 x 1 90 XORCY acoeff_lut_2 work 1 x 34 34 gates 34 34 Function Generators 11 11 MUXF5 lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED work 1 x 1 1 lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED lpm_mult_13_13_9_18_SIGNED_1_LPM_MULT_UNUSED work 6 x 1 6 lpm_mult_13_13_9_18_SIGNED_1_LPM_MULT_UNUSED ******************************************************* Cell: acoeff_lut_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 34 Number of MUXF5 : 11 Number of accumulated instances : 45 Number of ports : 18 Number of nets : 50 Number of instances : 45 Number of references to this view : 1 Cell Library References Total Area LUT2 xcv2 4 x 1 4 Function Generators LUT3 xcv2 2 x 1 2 Function Generators LUT4 xcv2 28 x 1 28 Function Generators MUXF5 xcv2 11 x 1 11 MUXF5 ******************************************************* Cell: lpm_mult_13_13_9_18_SIGNED_1_LPM_MULT_UNUSED View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of ports : 55 Number of nets : 0 Number of instances : 0 Number of references to this view : 6 ******************************************************* Cell: lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of ports : 76 Number of nets : 0 Number of instances : 0 Number of references to this view : 1 ******************************************************* Cell: zch_table_5_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 23 Number of MUXF5 : 6 Number of accumulated instances : 29 Number of ports : 10 Number of nets : 36 Number of instances : 29 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 4 x 1 4 Function Generators LUT4 xcv2 16 x 1 16 Function Generators MUXF5 xcv2 6 x 1 6 MUXF5 ******************************************************* Cell: sorter_8 View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 155 Number of Function Generators : 421 Number of MUX CARRYs : 80 Number of MUXF5 : 122 Number of accumulated instances : 779 Number of ports : 42 Number of nets : 801 Number of instances : 779 Number of references to this view : 36 Cell Library References Total Area FDC xcv2 3 x 1 3 Dffs or Latches FDCE xcv2 8 x 1 8 Dffs or Latches FDPE xcv2 144 x 1 144 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 4 x 1 4 Function Generators LUT2 xcv2 124 x 1 124 Function Generators LUT2_L xcv2 80 x 1 80 Function Generators LUT3 xcv2 134 x 1 134 Function Generators LUT4 xcv2 79 x 1 79 Function Generators MUXCY xcv2 8 x 1 8 MUX CARRYs MUXCY_L xcv2 72 x 1 72 MUX CARRYs MUXF5 xcv2 122 x 1 122 MUXF5 ******************************************************* Cell: zch_table_5_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 28 Number of MUXF5 : 8 Number of MUXF6 : 1 Number of accumulated instances : 37 Number of ports : 10 Number of nets : 44 Number of instances : 37 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 1 x 1 1 Function Generators LUT3 xcv2 4 x 1 4 Function Generators LUT4 xcv2 20 x 1 20 Function Generators MUXF5 xcv2 8 x 1 8 MUXF5 MUXF6 xcv2 1 x 1 1 MUXF6 ******************************************************* Cell: zch_table_5_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 24 Number of MUXF5 : 7 Number of MUXF6 : 1 Number of accumulated instances : 32 Number of ports : 10 Number of nets : 39 Number of instances : 32 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 2 x 1 2 Function Generators LUT3 xcv2 1 x 1 1 Function Generators LUT4 xcv2 18 x 1 18 Function Generators MUXF5 xcv2 7 x 1 7 MUXF5 MUXF6 xcv2 1 x 1 1 MUXF6 ******************************************************* Cell: zch_table_4_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 8 Number of accumulated instances : 31 Number of ports : 10 Number of nets : 38 Number of instances : 31 Number of references to this view : 2 Cell Library References Total Area GND xcv2 1 x 1 1 GND LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 3 x 1 3 Function Generators LUT4 xcv2 16 x 1 16 Function Generators MUXF5 xcv2 8 x 1 8 MUXF5 ******************************************************* Cell: zch_table_4_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 24 Number of MUXF5 : 7 Number of accumulated instances : 32 Number of ports : 10 Number of nets : 39 Number of instances : 32 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 1 x 1 1 Function Generators LUT3 xcv2 2 x 1 2 Function Generators LUT4 xcv2 18 x 1 18 Function Generators MUXF5 xcv2 7 x 1 7 MUXF5 VCC xcv2 1 x 1 1 VCC ******************************************************* Cell: zch_table_4_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 6 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 1 x 1 1 Function Generators LUT3 xcv2 1 x 1 1 Function Generators LUT4 xcv2 17 x 1 17 Function Generators MUXF5 xcv2 6 x 1 6 MUXF5 ******************************************************* Cell: zch_table_3_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 6 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 4 x 1 4 Function Generators LUT4 xcv2 15 x 1 15 Function Generators MUXF5 xcv2 6 x 1 6 MUXF5 ******************************************************* Cell: zch_table_3_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 23 Number of MUXF5 : 6 Number of accumulated instances : 29 Number of ports : 10 Number of nets : 36 Number of instances : 29 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 3 x 1 3 Function Generators LUT3 xcv2 1 x 1 1 Function Generators LUT4 xcv2 16 x 1 16 Function Generators MUXF5 xcv2 6 x 1 6 MUXF5 ******************************************************* Cell: zch_table_3_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 5 Number of accumulated instances : 27 Number of ports : 10 Number of nets : 34 Number of instances : 27 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 3 x 1 3 Function Generators LUT4 xcv2 16 x 1 16 Function Generators MUXF5 xcv2 5 x 1 5 MUXF5 ******************************************************* Cell: zch_table_2_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 15 Number of accumulated instances : 15 Number of ports : 10 Number of nets : 22 Number of instances : 15 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 3 x 1 3 Function Generators LUT4 xcv2 9 x 1 9 Function Generators ******************************************************* Cell: zch_table_1_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 27 Number of MUXF5 : 5 Number of accumulated instances : 32 Number of ports : 10 Number of nets : 39 Number of instances : 32 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 2 x 1 2 Function Generators LUT3 xcv2 5 x 1 5 Function Generators LUT4 xcv2 17 x 1 17 Function Generators MUXF5 xcv2 5 x 1 5 MUXF5 ******************************************************* Cell: zch_table_1_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 23 Number of MUXF5 : 7 Number of accumulated instances : 31 Number of ports : 10 Number of nets : 38 Number of instances : 31 Number of references to this view : 2 Cell Library References Total Area GND xcv2 1 x 1 1 GND LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 5 x 1 5 Function Generators LUT4 xcv2 15 x 1 15 Function Generators MUXF5 xcv2 7 x 1 7 MUXF5 ******************************************************* Cell: zch_table_1_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 22 Number of MUXF5 : 5 Number of MUXF6 : 1 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 2 x 1 2 Function Generators LUT4 xcv2 17 x 1 17 Function Generators MUXF5 xcv2 5 x 1 5 MUXF5 MUXF6 xcv2 1 x 1 1 MUXF6 ******************************************************* Cell: zch_table_0_2 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 20 Number of MUXF5 : 5 Number of accumulated instances : 25 Number of ports : 10 Number of nets : 32 Number of instances : 25 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 5 x 1 5 Function Generators LUT4 xcv2 12 x 1 12 Function Generators MUXF5 xcv2 5 x 1 5 MUXF5 ******************************************************* Cell: zch_table_0_1 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 25 Number of MUXF5 : 3 Number of accumulated instances : 28 Number of ports : 10 Number of nets : 35 Number of instances : 28 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 5 x 1 5 Function Generators LUT4 xcv2 17 x 1 17 Function Generators MUXF5 xcv2 3 x 1 3 MUXF5 ******************************************************* Cell: zch_table_0_0 View: default Library: work ******************************************************* Total accumulated area : Number of Function Generators : 20 Number of MUXF5 : 5 Number of accumulated instances : 25 Number of ports : 10 Number of nets : 32 Number of instances : 25 Number of references to this view : 2 Cell Library References Total Area LUT1 xcv2 3 x 1 3 Function Generators LUT3 xcv2 2 x 1 2 Function Generators LUT4 xcv2 15 x 1 15 Function Generators MUXF5 xcv2 5 x 1 5 MUXF5 ******************************************************* Cell: matching_memory View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 19 Number of Function Generators : 523 Number of MUX CARRYs : 6 Number of MUXF5 : 2 Number of accumulated instances : 188 Number of ports : 87 Number of nets : 227 Number of instances : 188 Number of references to this view : 60 Cell Library References Total Area FDP xcv2 12 x 1 12 Dffs or Latches FDPE xcv2 6 x 1 6 Dffs or Latches FDR xcv2 1 x 1 1 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 2 x 1 2 Function Generators LUT2 xcv2 19 x 1 19 Function Generators LUT3 xcv2 18 x 1 18 Function Generators LUT4 xcv2 62 x 1 62 Function Generators LUT4_L xcv2 6 x 1 6 Function Generators MUXCY xcv2 2 x 1 2 MUX CARRYs MUXCY_L xcv2 4 x 1 4 MUX CARRYs MUXF5 xcv2 2 x 1 2 MUXF5 RAM64X1D xcv2 52 x 8 416 Function Generators VCC xcv2 1 x 1 1 VCC ******************************************************* Cell: matching_memory View: default_unfold_2672 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 19 Number of Function Generators : 412 Number of MUX CARRYs : 6 Number of MUXF5 : 2 Number of accumulated instances : 168 Number of ports : 87 Number of nets : 206 Number of instances : 168 Number of references to this view : 12 Cell Library References Total Area FDP xcv2 12 x 1 12 Dffs or Latches FDPE xcv2 6 x 1 6 Dffs or Latches FDR xcv2 1 x 1 1 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 2 x 1 2 Function Generators LUT2 xcv2 19 x 1 19 Function Generators LUT3 xcv2 11 x 1 11 Function Generators LUT4 xcv2 62 x 1 62 Function Generators LUT4_L xcv2 6 x 1 6 Function Generators MUXCY xcv2 2 x 1 2 MUX CARRYs MUXCY_L xcv2 4 x 1 4 MUX CARRYs MUXF5 xcv2 2 x 1 2 MUXF5 RAM64X1D xcv2 39 x 8 312 Function Generators VCC xcv2 1 x 1 1 VCC ******************************************************* Cell: matching_logic_3_0 View: default_unfold_2202 Library: work ******************************************************* Total accumulated area : Number of Function Generators : 805 Number of MUX CARRYs : 500 Number of MUXF5 : 17 Number of accumulated instances : 1334 Number of ports : 265 Number of nets : 1567 Number of instances : 1334 Number of references to this view : 4 Cell Library References Total Area GND xcv2 1 x 1 1 GND LUT1 xcv2 24 x 1 24 Function Generators LUT1_L xcv2 6 x 1 6 Function Generators LUT2 xcv2 66 x 1 66 Function Generators LUT2_L xcv2 493 x 1 493 Function Generators LUT3 xcv2 37 x 1 37 Function Generators LUT4 xcv2 176 x 1 176 Function Generators LUT4_L xcv2 3 x 1 3 Function Generators MUXCY xcv2 58 x 1 58 MUX CARRYs MUXCY_L xcv2 442 x 1 442 MUX CARRYs MUXF5 xcv2 17 x 1 17 MUXF5 VCC xcv2 1 x 1 1 VCC XORCY xcv2 10 x 1 10 XORCY ******************************************************* Cell: matching_logic_2_8 View: default_unfold_2209 Library: work ******************************************************* Total accumulated area : Number of Function Generators : 799 Number of MUX CARRYs : 500 Number of MUXF5 : 16 Number of accumulated instances : 1327 Number of ports : 265 Number of nets : 1560 Number of instances : 1327 Number of references to this view : 4 Cell Library References Total Area GND xcv2 1 x 1 1 GND LUT1 xcv2 25 x 1 25 Function Generators LUT1_L xcv2 5 x 1 5 Function Generators LUT2 xcv2 64 x 1 64 Function Generators LUT2_L xcv2 493 x 1 493 Function Generators LUT3 xcv2 38 x 1 38 Function Generators LUT4 xcv2 170 x 1 170 Function Generators LUT4_L xcv2 4 x 1 4 Function Generators MUXCY xcv2 58 x 1 58 MUX CARRYs MUXCY_L xcv2 442 x 1 442 MUX CARRYs MUXF5 xcv2 16 x 1 16 MUXF5 VCC xcv2 1 x 1 1 VCC XORCY xcv2 10 x 1 10 XORCY ******************************************************* Cell: matching_logic_1_12 View: default_unfold_2219 Library: work ******************************************************* Total accumulated area : Number of Function Generators : 799 Number of MUX CARRYs : 500 Number of MUXF5 : 16 Number of accumulated instances : 1327 Number of ports : 265 Number of nets : 1560 Number of instances : 1327 Number of references to this view : 4 Cell Library References Total Area GND xcv2 1 x 1 1 GND LUT1 xcv2 24 x 1 24 Function Generators LUT1_L xcv2 6 x 1 6 Function Generators LUT2 xcv2 64 x 1 64 Function Generators LUT2_L xcv2 493 x 1 493 Function Generators LUT3 xcv2 37 x 1 37 Function Generators LUT4 xcv2 172 x 1 172 Function Generators LUT4_L xcv2 3 x 1 3 Function Generators MUXCY xcv2 58 x 1 58 MUX CARRYs MUXCY_L xcv2 442 x 1 442 MUX CARRYs MUXF5 xcv2 16 x 1 16 MUXF5 VCC xcv2 1 x 1 1 VCC XORCY xcv2 10 x 1 10 XORCY ******************************************************* Cell: seed_merger View: default_unfold_2616 Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 30 Number of Function Generators : 493 Number of MUX CARRYs : 21 Number of MUXF5 : 53 Number of accumulated instances : 445 Number of ports : 219 Number of nets : 607 Number of instances : 445 Number of references to this view : 6 Cell Library References Total Area FDC xcv2 12 x 1 12 Dffs or Latches FDCE xcv2 18 x 1 18 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 54 x 1 54 Function Generators LUT2 xcv2 20 x 1 20 Function Generators LUT2_L xcv2 21 x 1 21 Function Generators LUT3 xcv2 67 x 1 67 Function Generators LUT4 xcv2 25 x 1 25 Function Generators MUXCY xcv2 3 x 1 3 MUX CARRYs MUXCY_L xcv2 18 x 1 18 MUX CARRYs MUXF5 xcv2 53 x 1 53 MUXF5 RAM16X1D xcv2 153 x 2 306 Function Generators ******************************************************* Cell: uniquifier_52 View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 107 Number of Function Generators : 49 Number of MUX CARRYs : 22 Number of MUXF5 : 2 Number of accumulated instances : 186 Number of ports : 110 Number of nets : 242 Number of instances : 186 Number of references to this view : 6 Cell Library References Total Area FD xcv2 53 x 1 53 Dffs or Latches FDC xcv2 2 x 1 2 Dffs or Latches FDE xcv2 52 x 1 52 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 1 x 1 1 Function Generators LUT1_L xcv2 2 x 1 2 Function Generators LUT2_L xcv2 2 x 1 2 Function Generators LUT3 xcv2 17 x 1 17 Function Generators LUT4 xcv2 9 x 1 9 Function Generators LUT4_L xcv2 18 x 1 18 Function Generators MUXCY xcv2 8 x 1 8 MUX CARRYs MUXCY_L xcv2 14 x 1 14 MUX CARRYs MUXF5 xcv2 2 x 1 2 MUXF5 VCC xcv2 1 x 1 1 VCC XORCY xcv2 4 x 1 4 XORCY ******************************************************* Cell: zch_merger View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 30 Number of Function Generators : 555 Number of MUX CARRYs : 52 Number of MUXF5 : 3 Number of accumulated instances : 515 Number of ports : 220 Number of nets : 692 Number of instances : 515 Number of references to this view : 2 Cell Library References Total Area FDC xcv2 12 x 1 12 Dffs or Latches FDCE xcv2 18 x 1 18 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 9 x 1 9 Function Generators LUT1_L xcv2 29 x 1 29 Function Generators LUT2 xcv2 15 x 1 15 Function Generators LUT2_L xcv2 21 x 1 21 Function Generators LUT3 xcv2 66 x 1 66 Function Generators LUT4 xcv2 97 x 1 97 Function Generators LUT4_L xcv2 6 x 1 6 Function Generators MULT18X18 xcv2 3 x 1 3 Block Multipliers MUXCY xcv2 9 x 1 9 MUX CARRYs MUXCY_L xcv2 43 x 1 43 MUX CARRYs MUXF5 xcv2 3 x 1 3 MUXF5 RAM16X1D xcv2 156 x 2 312 Function Generators VCC xcv2 1 x 1 1 VCC XORCY xcv2 26 x 1 26 XORCY ******************************************************* Cell: uniquifier_53 View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 109 Number of Function Generators : 49 Number of MUX CARRYs : 22 Number of MUXF5 : 2 Number of accumulated instances : 188 Number of ports : 112 Number of nets : 245 Number of instances : 188 Number of references to this view : 2 Cell Library References Total Area FD xcv2 54 x 1 54 Dffs or Latches FDC xcv2 2 x 1 2 Dffs or Latches FDE xcv2 53 x 1 53 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 1 x 1 1 Function Generators LUT1_L xcv2 2 x 1 2 Function Generators LUT2_L xcv2 2 x 1 2 Function Generators LUT3 xcv2 17 x 1 17 Function Generators LUT4 xcv2 9 x 1 9 Function Generators LUT4_L xcv2 18 x 1 18 Function Generators MUXCY xcv2 8 x 1 8 MUX CARRYs MUXCY_L xcv2 14 x 1 14 MUX CARRYs MUXF5 xcv2 2 x 1 2 MUXF5 VCC xcv2 1 x 1 1 VCC XORCY xcv2 4 x 1 4 XORCY ******************************************************* Cell: zch_resorter View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 25 Number of Function Generators : 297 Number of MUX CARRYs : 11 Number of MUXF5 : 1 Number of accumulated instances : 232 Number of ports : 102 Number of nets : 290 Number of instances : 232 Number of references to this view : 2 Cell Library References Total Area FDC xcv2 9 x 1 9 Dffs or Latches FDCE xcv2 16 x 1 16 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 3 x 1 3 Function Generators LUT2 xcv2 13 x 1 13 Function Generators LUT2_L xcv2 7 x 1 7 Function Generators LUT3 xcv2 50 x 1 50 Function Generators LUT4 xcv2 12 x 1 12 Function Generators LUT4_L xcv2 4 x 1 4 Function Generators MUXCY xcv2 3 x 1 3 MUX CARRYs MUXCY_L xcv2 8 x 1 8 MUX CARRYs MUXF5 xcv2 1 x 1 1 MUXF5 RAM16X1D xcv2 104 x 2 208 Function Generators VCC xcv2 1 x 1 1 VCC ******************************************************* Cell: uniquifier_42 View: default Library: work ******************************************************* Total accumulated area : Number of Dffs or Latches : 87 Number of Function Generators : 49 Number of MUX CARRYs : 22 Number of MUXF5 : 2 Number of accumulated instances : 166 Number of ports : 90 Number of nets : 212 Number of instances : 166 Number of references to this view : 2 Cell Library References Total Area FD xcv2 43 x 1 43 Dffs or Latches FDC xcv2 2 x 1 2 Dffs or Latches FDE xcv2 42 x 1 42 Dffs or Latches GND xcv2 1 x 1 1 GND LUT1 xcv2 1 x 1 1 Function Generators LUT1_L xcv2 2 x 1 2 Function Generators LUT2_L xcv2 2 x 1 2 Function Generators LUT3 xcv2 17 x 1 17 Function Generators LUT4 xcv2 9 x 1 9 Function Generators LUT4_L xcv2 18 x 1 18 Function Generators MUXCY xcv2 8 x 1 8 MUX CARRYs MUXCY_L xcv2 14 x 1 14 MUX CARRYs MUXF5 xcv2 2 x 1 2 MUXF5 VCC xcv2 1 x 1 1 VCC XORCY xcv2 4 x 1 4 XORCY Number of global buffers used: 13 *********************************************** Device Utilization for 2V6000bf957 *********************************************** Resource Used Avail Utilization ----------------------------------------------- IOs 173 684 25.29% Global Buffers 13 16 81.25% Function Generators 49554 67584 73.32% CLB Slices 24777 33792 73.32% Dffs or Latches 6501 69636 9.34% Block RAMs 0 144 0.00% Block Multipliers 15 144 10.42% ----------------------------------------------- Using wire table: xcv2-6000-6_wc Clock Frequency Report Clock : Frequency ------------------------------------ clk : 38.8 MHz clk1_in(5) : 192.3 MHz clk1_in(4) : 192.3 MHz clk1_in(3) : 192.3 MHz clk1_in(2) : 192.3 MHz clk1_in(1) : 192.3 MHz clk1_in(0) : 192.3 MHz clk0_in(5) : 192.3 MHz clk0_in(4) : 192.3 MHz clk0_in(3) : 192.3 MHz clk0_in(2) : 192.3 MHz clk0_in(1) : 192.3 MHz clk0_in(0) : 192.3 MHz Slack Table at End Points End points Slack Arrival Required rise fall rise fall match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_1_match_gen2_1_match_inst_gen_2_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_0_match_gen2_1_match_inst_gen_3_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_1_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_2_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_1_match_gen2_1_match_inst_gen_3_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_0_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_2_match_gen2_1_match_inst_gen_3_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 match_gen1_2_match_gen2_1_match_inst_gen_2_matching_memory1/reg_reg_b(4)/D : -0.75 25.47 25.47 24.72 24.72 Critical Path Report Critical path #1, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_2_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_2_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix108/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_2_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/nx846/O LUT4 0.75 8.28 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_2_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_2_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix2_ix22/LO MUXCY_L 0.34 14.32 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix2_ix26/O XORCY 1.38 15.70 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix23/LO LUT2_L 0.33 16.03 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 0.88 16.90 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_2_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_2_match_gen2_1_match_inst_matching_logic1/nx1340/O LUT4 0.75 20.63 up 0.30 match_gen1_2_match_gen2_1_match_inst_matching_logic1/a(0)_dup_400/O LUT4 0.75 21.38 up 0.30 match_gen1_2_match_gen2_1_match_inst_inc(0)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_2_match_gen2_1_match_inst_gen_0_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #2, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_0_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix108/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_0_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/nx846/O LUT4 0.75 8.28 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_0_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_0_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix22/LO MUXCY_L 0.34 14.32 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix2_ix26/O XORCY 1.38 15.70 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix23/LO LUT2_L 0.33 16.03 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 0.88 16.90 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_0_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_0_match_gen2_1_match_inst_matching_logic1/nx1284/O LUT4 0.75 20.63 up 0.30 match_gen1_0_match_gen2_1_match_inst_matching_logic1/a(0)_dup_380/O LUT4 0.75 21.38 up 0.30 match_gen1_0_match_gen2_1_match_inst_inc(3)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_0_match_gen2_1_match_inst_gen_3_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_0_match_gen2_1_match_inst_gen_3_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_0_match_gen2_1_match_inst_gen_3_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_0_match_gen2_1_match_inst_gen_3_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_0_match_gen2_1_match_inst_gen_3_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #3, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix112/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx847/O LUT4 0.75 8.28 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_1_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix20/O XORCY 0.88 14.85 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix19/LO LUT2_L 0.33 15.18 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix21/LO MUXCY_L 0.34 15.52 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 1.38 16.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1256/O LUT4 0.75 20.63 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_374/O LUT4 0.75 21.38 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(4)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #4, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix108/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx847/O LUT4 0.75 8.28 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_1_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix20/O XORCY 0.88 14.85 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix19/LO LUT2_L 0.33 15.18 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix21/LO MUXCY_L 0.34 15.52 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 1.38 16.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1256/O LUT4 0.75 20.63 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_374/O LUT4 0.75 21.38 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(4)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #5, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix114/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx846/O LUT4 0.75 8.28 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_1_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix20/O XORCY 0.88 14.85 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix19/LO LUT2_L 0.33 15.18 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix21/LO MUXCY_L 0.34 15.52 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 1.38 16.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1256/O LUT4 0.75 20.63 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_374/O LUT4 0.75 21.38 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(4)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #6, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix112/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx846/O LUT4 0.75 8.28 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_1_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix20/O XORCY 0.88 14.85 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix19/LO LUT2_L 0.33 15.18 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix21/LO MUXCY_L 0.34 15.52 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 1.38 16.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1256/O LUT4 0.75 20.63 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_374/O LUT4 0.75 21.38 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(4)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #7, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix108/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx846/O LUT4 0.75 8.28 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_1_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix20/O XORCY 0.88 14.85 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix19/LO LUT2_L 0.33 15.18 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix21/LO MUXCY_L 0.34 15.52 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 1.38 16.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1256/O LUT4 0.75 20.63 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_374/O LUT4 0.75 21.38 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(4)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #8, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix114/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx847/O LUT4 0.75 8.28 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_1_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix22/LO MUXCY_L 0.34 14.32 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix26/O XORCY 1.38 15.70 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix23/LO LUT2_L 0.33 16.03 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 0.88 16.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1256/O LUT4 0.75 20.63 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_374/O LUT4 0.75 21.38 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(4)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #9, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix112/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx847/O LUT4 0.75 8.28 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_1_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix22/LO MUXCY_L 0.34 14.32 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix26/O XORCY 1.38 15.70 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix23/LO LUT2_L 0.33 16.03 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 0.88 16.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1256/O LUT4 0.75 20.63 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_374/O LUT4 0.75 21.38 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(4)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 ------------------------------------------------------------------------------------------------------- Critical path #10, (path slack = -0.7): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/reg_reg_a(5)/Q FDP 0.00 1.54 up 0.80 match_gen1_1_match_gen2_1_match_inst_gen_1_matching_memory1/ix629_ix108/DPO RAM64X1D 1.04 2.59 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4278_nx40/O LUT4 0.89 3.48 up 0.40 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_modgen_add_4278_nx80/O LUT4 0.75 4.23 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ysa_plus(7)/O LUT2 0.75 4.98 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix57/LO LUT2_L 0.33 5.31 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix59/LO MUXCY_L 0.34 5.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix63/LO MUXCY_L 0.04 5.69 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_gt_4339_ix67/O MUXCY 1.09 6.78 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx800/O LUT4 0.75 7.53 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx847/O LUT4 0.75 8.28 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix887/O MUXF5 0.78 9.06 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_nx359/O LUT2 0.75 9.81 up 0.30 match_gen1_1_match_gen2_1_match_inst_ab_select(3)/O LUT3 1.03 10.84 up 0.50 match_gen1_1_match_gen2_1_match_inst_matching_logic1/NOT_ab_select(3)/O LUT1 0.75 11.59 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix11/LO LUT4_L 0.33 11.92 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix15/LO MUXCY_L 0.34 12.26 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix0_ix19/O XORCY 1.38 13.64 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix18/LO LUT1_L 0.33 13.97 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix22/LO MUXCY_L 0.34 14.32 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix2_ix26/O XORCY 1.38 15.70 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix23/LO LUT2_L 0.33 16.03 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/modgen_add_4424_ix25/O XORCY 0.88 16.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx852/O LUT4 0.75 17.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/ix878/O MUXF5 0.78 18.43 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(1)(1)/O LUT2 1.45 19.88 up 0.80 match_gen1_1_match_gen2_1_match_inst_matching_logic1/nx1256/O LUT4 0.75 20.63 up 0.30 match_gen1_1_match_gen2_1_match_inst_matching_logic1/a(0)_dup_374/O LUT4 0.75 21.38 up 0.30 match_gen1_1_match_gen2_1_match_inst_inc(4)(1)/O LUT4 1.03 22.40 up 0.50 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1290/O LUT4 0.75 23.15 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1320/O LUT4 0.75 23.90 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx1297/O LUT4 0.75 24.65 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/nx126/O LUT4 0.75 25.40 up 0.30 match_gen1_1_match_gen2_1_match_inst_gen_4_matching_memory1/reg_reg_b(4)/D FDP 0.00 25.40 up 0.00 data arrival time 25.40 data required time (default specified - setup time) 24.72 ------------------------------------------------------------------------------------------------------- data required time 24.72 data arrival time 25.40 ---------- slack -0.68 -------------------------------------------------------------------------------------------------------