Clock Frequency Report Clock : Frequency ------------------------------------ clk : 53.7 MHz clk1_in(5) : 146.8 MHz clk1_in(4) : 146.8 MHz clk1_in(3) : 146.8 MHz clk1_in(2) : 146.8 MHz clk1_in(1) : 146.8 MHz clk1_in(0) : 146.8 MHz clk0_in(5) : 146.8 MHz clk0_in(4) : 146.8 MHz clk0_in(3) : 146.8 MHz clk0_in(2) : 146.8 MHz clk0_in(1) : 146.8 MHz clk0_in(0) : 146.8 MHz Critical Path Report Critical path #1, (path slack = 2.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clk0_in(4) (offset) 0.00 (falling edge) delay thru clock network 4.17 (worst case) pulse width 4.17 input_gen_4_input_inst_inputcontrol0/reg_stage_a_end/clk stratix_lcell_normal 4.17 (falling edge) input_gen_4_input_inst_inputcontrol0/reg_stage_a_end/regout stratix_lcell_normal 0.00 4.38 up 1.11 input_gen_4_input_inst_inputcontrol0/ix1319/combout stratix_lcell_normal 1.34 5.71 up 1.08 input_gen_4_input_inst_inputcontrol0/reg_d_out_reg(23)/datad stratix_lcell_normal 0.00 5.71 up 0.00 data arrival time 5.71 clk0_in(4) (offset) 0.00 (rising edge) delay thru clock network 0.00 (ideal) input_gen_4_input_inst_inputcontrol0/reg_d_out_reg(23)/clk stratix_lcell_normal 0.00 (rising edge) clock cycle 8.33 library setup time (0.28) data required time 8.05 ------------------------------------------------------------------------------------------------------- data required time 8.05 data arrival time 5.71 ---------- slack 2.34 ------------------------------------------------------------------------------------------------------- Critical path #2, (path slack = 2.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clk1_in(1) (offset) 0.00 (falling edge) delay thru clock network 4.17 (worst case) pulse width 4.17 input_gen_1_input_inst_inputcontrol1/reg_stage_a_end/clk stratix_lcell_normal 4.17 (falling edge) input_gen_1_input_inst_inputcontrol1/reg_stage_a_end/regout stratix_lcell_normal 0.00 4.38 up 1.11 input_gen_1_input_inst_inputcontrol1/ix1319/combout stratix_lcell_normal 1.34 5.71 up 1.08 input_gen_1_input_inst_inputcontrol1/reg_d_out_reg(26)/datad stratix_lcell_normal 0.00 5.71 up 0.00 data arrival time 5.71 clk1_in(1) (offset) 0.00 (rising edge) delay thru clock network 0.00 (ideal) input_gen_1_input_inst_inputcontrol1/reg_d_out_reg(26)/clk stratix_lcell_normal 0.00 (rising edge) clock cycle 8.33 library setup time (0.28) data required time 8.05 ------------------------------------------------------------------------------------------------------- data required time 8.05 data arrival time 5.71 ---------- slack 2.34 ------------------------------------------------------------------------------------------------------- Critical path #3, (path slack = 2.3): NAME GATE ARRIVAL LOAD ------------------------------------------------------------------------------------------------------- clk0_in(4) (offset) 0.00 (falling edge) delay thru clock network 4.17 (worst case) pulse width 4.17 input_gen_4_input_inst_inputcontrol0/reg_stage_a_end/clk stratix_lcell_normal 4.17 (falling edge) input_gen_4_input_inst_inputcontrol0/reg_stage_a_end/regout stratix_lcell_normal 0.00 4.38 up 1.11 input_gen_4_input_inst_inputcontrol0/ix1319/combout stratix_lcell_normal 1.34 5.71 up 1.08 input_gen_4_input_inst_inputcontrol0/reg_d_out_reg(16)/datad stratix_lcell_normal 0.00 5.71 up 0.00 data arrival time 5.71 clk0_in(4) (offset) 0.00 (rising edge) delay thru clock network 0.00 (ideal) input_gen_4_input_inst_inputcontrol0/reg_d_out_reg(16)/clk stratix_lcell_normal 0.00 (rising edge) clock cycle 8.33 library setup time (0.28) data required time 8.05 ------------------------------------------------------------------------------------------------------- data required time 8.05 data arrival time 5.71 ---------- slack 2.34 -------------------------------------------------------------------------------------------------------