******************************************************* Cell: reconst View: default Library: work ******************************************************* Total accumulated area : Number of DFFs : 18 Number of GND : 1 Number of IOs : 268 Number of LCs : 3554 Number of VCC : 1 Black Box lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED : 1 Number of accumulated instances : 3779 Number of ports : 268 Number of nets : 5124 Number of instances : 3741 Number of references to this view : 0 Cell Library References Total Area DFFC_P apex20e 18 x 1 18 DFFs 1 18 LCs GND apex20e 1 x 1 1 GND NOT apex20e 2 x VCC apex20e 1 x 1 1 VCC acoeff_lut_2 work 1 x 39 39 LCs apex20_io_input_none_from_pin apex20e 124 x 1 124 IOs apex20_io_output_none_none apex20e 96 x 1 96 IOs apex20_lcell_arithmetic apex20e 1316 x 1 1316 LCs apex20_lcell_normal apex20e 1219 x 1 1219 LCs apex20_lcell_reg apex20e 884 x 1 884 LCs atom_lcell_carryi apex20e 18 x 1 18 LCs atom_lcell_carryo apex20e 60 x 1 60 LCs lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED work 1 x 1 1 lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED ******************************************************* Cell: acoeff_lut_2 View: default Library: work ******************************************************* Total accumulated area : Number of LCs : 39 Number of accumulated instances : 39 Number of ports : 18 Number of nets : 44 Number of instances : 39 Number of references to this view : 1 Cell Library References Total Area apex20_lcell_normal apex20e 39 x 1 39 LCs ******************************************************* Cell: lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED View: INTERFACE Library: work ******************************************************* Total accumulated area : Number of lpm_divide_21_16_SIGNED_SIGNED_TRUE_11_LPM_DIVIDE_UNUSED : 1 Number of ports : 76 Number of nets : 0 Number of instances : 0 Number of references to this view : 1 *********************************************** Device Utilization for EP20K200EBC356 *********************************************** Resource Used Avail Utilization ----------------------------------------------- IOs 268 273 98.17% LCs 3554 8320 42.72% Memory Bits 0 106496 0.00% ----------------------------------------------- Using default wire table: apex20e_default Clock Frequency Report Clock : Frequency ------------------------------------ clk : 45.3 MHz Slack Table at End Points End points Slack Arrival Required rise fall rise fall reg_acoeff_stage1(2)(3)/dataa : 2.93 21.22 21.22 24.15 24.15 reg_acoeff_stage1(2)(12)/dataa : 2.98 21.17 21.17 24.15 24.15 reg_acoeff_stage1(2)(7)/dataa : 2.98 21.17 21.17 24.15 24.15 reg_acoeff_stage1(2)(5)/dataa : 3.02 21.13 21.13 24.15 24.15 reg_acoeff_stage1(2)(10)/dataa : 3.02 21.13 21.13 24.15 24.15 reg_acoeff_stage1(2)(0)/dataa : 3.07 21.08 21.08 24.15 24.15 reg_acoeff_stage1(2)(2)/dataa : 3.07 21.08 21.08 24.15 24.15 reg_acoeff_stage1(2)(6)/dataa : 3.07 21.08 21.08 24.15 24.15 reg_acoeff_stage1(2)(11)/dataa : 3.07 21.08 21.08 24.15 24.15 reg_acoeff_stage1(2)(4)/dataa : 3.07 21.08 21.08 24.15 24.15 Critical Path Report Critical path #1, (path slack = 2.9): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix558/combout apex20_lcell_normal 2.38 18.84 up 1.22 lgen_2_acoeff_lut_inst/ix542/combout apex20_lcell_normal 2.38 21.22 up 1.22 reg_acoeff_stage1(2)(3)/dataa apex20_lcell_reg 0.00 21.22 up 0.00 data arrival time 21.22 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.22 ---------- slack 2.93 ---------------------------------------------------------------------------------------------------- Critical path #2, (path slack = 3.0): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix553/combout apex20_lcell_normal 2.38 18.84 up 1.22 lgen_2_acoeff_lut_inst/ix538/combout apex20_lcell_normal 2.33 21.17 up 1.22 reg_acoeff_stage1(2)(7)/dataa apex20_lcell_reg 0.00 21.17 up 0.00 data arrival time 21.17 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.17 ---------- slack 2.98 ---------------------------------------------------------------------------------------------------- Critical path #3, (path slack = 3.0): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix561/combout apex20_lcell_normal 2.38 18.84 up 1.22 lgen_2_acoeff_lut_inst/ix533/combout apex20_lcell_normal 2.33 21.17 up 1.22 reg_acoeff_stage1(2)(12)/dataa apex20_lcell_reg 0.00 21.17 up 0.00 data arrival time 21.17 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.17 ---------- slack 2.98 ---------------------------------------------------------------------------------------------------- Critical path #4, (path slack = 3.0): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix549/combout apex20_lcell_normal 2.38 18.84 up 1.22 lgen_2_acoeff_lut_inst/ix535/combout apex20_lcell_normal 2.29 21.13 up 1.22 reg_acoeff_stage1(2)(10)/dataa apex20_lcell_reg 0.00 21.13 up 0.00 data arrival time 21.13 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.13 ---------- slack 3.02 ---------------------------------------------------------------------------------------------------- Critical path #5, (path slack = 3.0): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix556/combout apex20_lcell_normal 2.38 18.84 up 1.22 lgen_2_acoeff_lut_inst/ix540/combout apex20_lcell_normal 2.29 21.13 up 1.22 reg_acoeff_stage1(2)(5)/dataa apex20_lcell_reg 0.00 21.13 up 0.00 data arrival time 21.13 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.13 ---------- slack 3.02 ---------------------------------------------------------------------------------------------------- Critical path #6, (path slack = 3.0): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(4)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.57 8.37 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.04 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.71 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.37 up 3.50 lgen_2_acoeff_lut_inst/ix558/combout apex20_lcell_normal 2.38 18.75 up 1.22 lgen_2_acoeff_lut_inst/ix542/combout apex20_lcell_normal 2.38 21.13 up 1.22 reg_acoeff_stage1(2)(3)/dataa apex20_lcell_reg 0.00 21.13 up 0.00 data arrival time 21.13 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.13 ---------- slack 3.02 ---------------------------------------------------------------------------------------------------- Critical path #7, (path slack = 3.1): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix557/combout apex20_lcell_normal 2.29 18.75 up 1.22 lgen_2_acoeff_lut_inst/ix541/combout apex20_lcell_normal 2.33 21.08 up 1.22 reg_acoeff_stage1(2)(4)/dataa apex20_lcell_reg 0.00 21.08 up 0.00 data arrival time 21.08 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.08 ---------- slack 3.07 ---------------------------------------------------------------------------------------------------- Critical path #8, (path slack = 3.1): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix548/combout apex20_lcell_normal 2.29 18.75 up 1.22 lgen_2_acoeff_lut_inst/ix534/combout apex20_lcell_normal 2.33 21.08 up 1.22 reg_acoeff_stage1(2)(11)/dataa apex20_lcell_reg 0.00 21.08 up 0.00 data arrival time 21.08 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.08 ---------- slack 3.07 ---------------------------------------------------------------------------------------------------- Critical path #9, (path slack = 3.1): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix555/combout apex20_lcell_normal 2.29 18.75 up 1.22 lgen_2_acoeff_lut_inst/ix539/combout apex20_lcell_normal 2.33 21.08 up 1.22 reg_acoeff_stage1(2)(6)/dataa apex20_lcell_reg 0.00 21.08 up 0.00 data arrival time 21.08 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.08 ---------- slack 3.07 ---------------------------------------------------------------------------------------------------- Critical path #10, (path slack = 3.1): NAME GATE ARRIVAL LOAD ---------------------------------------------------------------------------------------------------- clock information not specified delay thru clock network 0.00 (ideal) reg_track_stage0(5)/regout apex20_lcell_reg 0.00 3.80 up 3.50 ix1275/combout apex20_lcell_normal 4.66 8.46 up 3.50 ix1434/combout apex20_lcell_normal 1.67 10.13 up 1.22 ix282/combout apex20_lcell_normal 1.67 11.80 up 1.22 reg_mask_id_stage1(3)/combout apex20_lcell_normal 4.66 16.46 up 3.50 lgen_2_acoeff_lut_inst/ix567/combout apex20_lcell_normal 2.29 18.75 up 1.22 lgen_2_acoeff_lut_inst/ix543/combout apex20_lcell_normal 2.33 21.08 up 1.22 reg_acoeff_stage1(2)(2)/dataa apex20_lcell_reg 0.00 21.08 up 0.00 data arrival time 21.08 data required time (default specified - setup time) 24.15 ---------------------------------------------------------------------------------------------------- data required time 24.15 data arrival time 21.08 ---------- slack 3.07 ----------------------------------------------------------------------------------------------------