set quartus_exec_path D:\QUARTUS2.2/bin
set quartus_exec_path D:\QUARTUS2.2/bin
set register2register 25
set input2register 25
set register2output 25
_gc_read_init
_gc_run_init
set input_file_list { J:/vhdl/gtu/src/gtu_types.vhd J:/vhdl/gtu/src/track_types.vhd J:/vhdl/gtu/src/inputcontrol.vhd J:/vhdl/gtu/src/buffer_merger.vhd J:/vhdl/gtu/src/proj_d.vhd J:/vhdl/gtu/src/proj_y.vhd J:/vhdl/gtu/src/rec_tables.vhd J:/vhdl/gtu/src/input.vhd J:/vhdl/gtu/src/sorter.vhd J:/vhdl/gtu/src/zch_table.vhd J:/vhdl/gtu/src/z_channel.vhd J:/vhdl/gtu/src/matching_logic.vhd J:/vhdl/gtu/src/matching_memory.vhd J:/vhdl/gtu/src/match.vhd J:/vhdl/gtu/src/seed_merger.vhd J:/vhdl/gtu/src/zch_merger.vhd J:/vhdl/gtu/src/zch_resorter.vhd J:/vhdl/gtu/src/uniquifier.vhd J:/vhdl/gtu/src/unique.vhd J:/vhdl/gtu/src/reconst.vhd J:/vhdl/gtu/src/toplevel.vhd }
set edifout_write_noopted_contents FALSE
set part EP20K200EQC208
set process 1
set chip TRUE
set macro FALSE
set optimize_for area
set report brief
set -hierarchy auto
set hierarchy_auto TRUE
set hierarchy_preserve FALSE
set hierarchy_flatten FALSE
set output_file J:/vhdl/gtu/syn_ls/toplevel_0.edf
set novendor_constraint_file FALSE
set sdf_write_flat_netlist TRUE
set target apex20e
_gc_read
_gc_run
_gc_read_init
_gc_run_init
set input_file_list { J:/vhdl/gtu/src/gtu_types.vhd J:/vhdl/gtu/src/track_types.vhd J:/vhdl/gtu/src/inputcontrol.vhd J:/vhdl/gtu/src/buffer_merger.vhd J:/vhdl/gtu/src/proj_d.vhd J:/vhdl/gtu/src/proj_y.vhd J:/vhdl/gtu/src/rec_tables.vhd J:/vhdl/gtu/src/input.vhd J:/vhdl/gtu/src/sorter.vhd J:/vhdl/gtu/src/zch_table.vhd J:/vhdl/gtu/src/z_channel.vhd J:/vhdl/gtu/src/matching_logic.vhd J:/vhdl/gtu/src/matching_memory.vhd J:/vhdl/gtu/src/match.vhd J:/vhdl/gtu/src/seed_merger.vhd J:/vhdl/gtu/src/zch_merger.vhd J:/vhdl/gtu/src/zch_resorter.vhd J:/vhdl/gtu/src/uniquifier.vhd J:/vhdl/gtu/src/unique.vhd J:/vhdl/gtu/src/reconst.vhd J:/vhdl/gtu/src/toplevel.vhd }
set process 3
set chip TRUE
set macro FALSE
set hierarchy_auto TRUE
set hierarchy_preserve FALSE
set hierarchy_flatten FALSE
set output_file J:/vhdl/gtu/syn_ls/toplevel_0.edf
set target apex20e
_gc_read
_gc_run
place_and_route J:/vhdl/gtu/syn_ls/toplevel_0.edf -target apex20e -exe_path D:QUARTUS2.2/bin -part EP20K1000EBC652 -speed_grade 3  -quartus_compile -quartus_ba_sim -ba_format Verilog
_gc_read_init
_gc_run_init
set input_file_list { J:/vhdl/gtu/src/gtu_types.vhd J:/vhdl/gtu/src/track_types.vhd J:/vhdl/gtu/src/inputcontrol.vhd J:/vhdl/gtu/src/buffer_merger.vhd J:/vhdl/gtu/src/proj_d.vhd J:/vhdl/gtu/src/proj_y.vhd J:/vhdl/gtu/src/rec_tables.vhd J:/vhdl/gtu/src/input.vhd J:/vhdl/gtu/src/sorter.vhd J:/vhdl/gtu/src/zch_table.vhd J:/vhdl/gtu/src/z_channel.vhd J:/vhdl/gtu/src/matching_logic.vhd J:/vhdl/gtu/src/matching_memory.vhd J:/vhdl/gtu/src/match.vhd J:/vhdl/gtu/src/seed_merger.vhd J:/vhdl/gtu/src/zch_merger.vhd J:/vhdl/gtu/src/zch_resorter.vhd J:/vhdl/gtu/src/uniquifier.vhd J:/vhdl/gtu/src/unique.vhd J:/vhdl/gtu/src/reconst.vhd J:/vhdl/gtu/src/toplevel.vhd }
set part 2V4000bf957
set process 6
set wire_table xcv2-40-6_wc
set chip TRUE
set macro FALSE
set hierarchy_auto TRUE
set hierarchy_preserve FALSE
set hierarchy_flatten FALSE
set output_file J:/vhdl/gtu/syn_ls/toplevel_1.edf
set sdf_write_flat_netlist FALSE
set target xcv2
_gc_read
_gc_run
place_and_route J:/vhdl/gtu/syn_ls/toplevel_1.edf -target xcv2 -part 2V6000bf957 -speed_grade 6  -m1_pr_high -ba_format Verilog -m1_no_bits