Release 6.2i - xst G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 2.32 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 2.32 s | Elapsed : 0.00 / 1.00 s --> Reading design: zch_merger.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : zch_merger.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : zch_merger Output Format : NGC Target Device : xc2vp40-5-ff1152 ---- Source Options Top Module Name : zch_merger Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : zch_merger.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES Optimize Instantiated Primitives : NO tristate2logic : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work. Architecture gtu_types of Entity gtu_types is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd. WARNING:Xst:647 - Input is never used. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. Found 5-bit adder for signal <$n0005> created at line 104. Found 6-bit adder for signal <$n0014> created at line 104. Found 6-bit adder for signal <$n0015>. Found 4-bit adder for signal <$n0019> created at line 95. Found 6-bit adder for signal <$n0025> created at line 104. Found 6-bit adder for signal <$n0026>. Found 4-bit adder for signal <$n0048> created at line 104. Found 3-bit adder for signal <$n0049> created at line 95. Found 3-bit comparator not equal for signal <$n0053> created at line 194. Found 3-bit comparator not equal for signal <$n0057> created at line 194. Found 3-bit comparator not equal for signal <$n0061> created at line 194. Found 3-bit adder for signal <$n0069> created at line 163. Found 4-bit adder for signal <$n0072>. Found 3-bit adder for signal <$n0079> created at line 163. Found 4-bit adder for signal <$n0082>. Found 4-bit subtractor for signal <$n0098> created at line 104. Found 4-bit subtractor for signal <$n0099> created at line 104. Found 4-bit subtractor for signal <$n0100> created at line 104. Found 4-bit comparator less for signal <$n0101> created at line 198. Found 4-bit comparator equal for signal <$n0102> created at line 198. Found 7-bit comparator less for signal <$n0103> created at line 198. Found 4-bit comparator less for signal <$n0104> created at line 198. Found 4-bit comparator equal for signal <$n0105> created at line 198. Found 7-bit comparator less for signal <$n0106> created at line 198. Found 4-bit comparator less for signal <$n0107> created at line 198. Found 4-bit comparator equal for signal <$n0108> created at line 198. Found 7-bit comparator less for signal <$n0109> created at line 198. Found 4x3-bit multiplier for signal <$n0113> created at line 104. Found 4x3-bit multiplier for signal <$n0114> created at line 104. Found 4x3-bit multiplier for signal <$n0115> created at line 104. Found 3-bit up counter for signal . Found 3-bit register for signal . Found 9-bit register for signal . Found 3-bit up counter for signal . Summary: inferred 3 RAM(s). inferred 6 Counter(s). inferred 12 D-type flip-flop(s). inferred 15 Adder/Subtracter(s). inferred 3 Multiplier(s). inferred 12 Comparator(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # LUT RAMs : 3 8x52-bit dual-port distributed RAM: 3 # Multipliers : 3 4x3-bit multiplier : 3 # Adders/Subtractors : 13 6-bit adder : 4 4-bit subtractor : 3 3-bit adder : 1 4-bit adder : 4 5-bit adder : 1 # Counters : 6 3-bit up counter : 6 # Registers : 6 1-bit register : 3 3-bit register : 3 # Comparators : 12 7-bit comparator less : 3 4-bit comparator equal : 3 4-bit comparator less : 3 3-bit comparator not equal : 3 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block zch_merger, actual ratio is 2. FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s) FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s) FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s) FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s) FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s) FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s) FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s) FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s) FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s) ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : zch_merger.ngr Top Level Output File Name : zch_merger Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 220 Macro Statistics : # RAM : 3 # 8x52-bit dual-port distributed RAM: 3 # Registers : 12 # 1-bit register : 3 # 3-bit register : 9 # Adders/Subtractors : 3 # 6-bit adder : 3 # Multipliers : 3 # 4x3-bit multiplier : 3 # Comparators : 12 # 3-bit comparator not equal : 3 # 4-bit comparator equal : 3 # 4-bit comparator less : 3 # 7-bit comparator less : 3 Cell Usage : # BELS : 294 # GND : 1 # LUT1 : 6 # LUT1_D : 1 # LUT1_L : 12 # LUT2 : 27 # LUT2_D : 1 # LUT2_L : 5 # LUT3 : 131 # LUT3_D : 4 # LUT3_L : 9 # LUT4 : 36 # LUT4_D : 8 # LUT4_L : 8 # MUXCY : 30 # MUXF5 : 1 # VCC : 1 # XORCY : 13 # FlipFlops/Latches : 39 # FD : 3 # FDR : 9 # FDRE : 27 # RAMS : 156 # RAM16X1D : 156 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 218 # IBUF : 163 # OBUF : 55 # MULTs : 3 # MULT18X18 : 3 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2vp40ff1152-5 Number of Slices: 530 out of 19392 2% Number of Slice Flip Flops: 39 out of 38784 0% Number of 4 input LUTs: 404 out of 38784 1% Number of bonded IOBs: 218 out of 692 31% Number of MULT18X18s: 3 out of 192 1% Number of GCLKs: 1 out of 16 6% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 195 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -5 Minimum period: 15.199ns (Maximum Frequency: 65.794MHz) Minimum input arrival time before clock: 2.788ns Maximum output required time after clock: 19.442ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk' Delay: 15.199ns (Levels of Logic = 14) Source: Mram_mem<0>_inst_ramx1d_49 (RAM) Destination: rd_addr_reg_2_2 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: Mram_mem<0>_inst_ramx1d_49 to rd_addr_reg_2_2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAM16X1D:WCLK->DPO 5 1.570 0.663 Mram_mem<0>_inst_ramx1d_49 (mem_out<0><49>) LUT1_L:I0->LO 1 0.351 0.100 Msub__n0100__n00141 (_n0100<0>) MULT18X18:A0->P1 2 1.533 0.624 Mmult__n0115_inst_mult_0 (mem_out_with_z<0><50>) LUT1_L:I0->LO 1 0.351 0.000 mem_out_with_z<0><50>_rt (mem_out_with_z<0><50>_rt) MUXCY:S->O 1 0.422 0.000 Madd__n0025_inst_cy_14 (Madd__n0025_inst_cy_14) XORCY:CI->O 4 0.973 0.650 Madd__n0025_inst_sum_8 (_n0025<2>) LUT1_L:I0->LO 1 0.351 0.000 _n0167<2>1 (_n0167<2>) MUXCY:S->O 1 0.422 0.468 Madd__n0026_inst_cy_9 (Madd__n0026_inst_cy_9) LUT2_L:I0->LO 0 0.351 0.000 Madd__n0026_inst_cy_10 (Madd__n0026_inst_cy_10) XORCY:CI->O 1 0.973 0.468 Madd__n0026_inst_sum_4 (_n0026<4>) LUT4_L:I0->LO 1 0.351 0.100 _n0199<3>31 (CHOICE689) LUT4:I3->O 4 0.351 0.650 _n0199<3>64 (mem_out_sortnum<0><3>) LUT4:I1->O 5 0.351 0.663 _n0062110 (lower_than_next<0>) LUT3:I0->O 2 0.351 0.624 pop<2>8_SW0 (N10329) LUT4:I1->O 6 0.351 0.676 pop<2>53 (pop<2>) FDRE:CE 0.461 rd_addr_reg_2_0 ---------------------------------------- Total 15.199ns (9.513ns logic, 5.686ns route) (62.6% logic, 37.4% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 2.788ns (Levels of Logic = 1) Source: pretrigger (PAD) Destination: wr_addr_last_0_0 (FF) Destination Clock: clk rising Data Path: pretrigger to wr_addr_last_0_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 36 0.969 1.051 pretrigger_IBUF (pretrigger_IBUF) FDR:R 0.768 wr_addr_last_2_1 ---------------------------------------- Total 2.788ns (1.737ns logic, 1.051ns route) (62.3% logic, 37.7% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 19.442ns (Levels of Logic = 16) Source: Mram_mem<0>_inst_ramx1d_49 (RAM) Destination: track_out<52> (PAD) Source Clock: clk rising Data Path: Mram_mem<0>_inst_ramx1d_49 to track_out<52> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAM16X1D:WCLK->DPO 5 1.570 0.663 Mram_mem<0>_inst_ramx1d_49 (mem_out<0><49>) LUT1_L:I0->LO 1 0.351 0.100 Msub__n0100__n00141 (_n0100<0>) MULT18X18:A0->P1 2 1.533 0.624 Mmult__n0115_inst_mult_0 (mem_out_with_z<0><50>) LUT1_L:I0->LO 1 0.351 0.000 mem_out_with_z<0><50>_rt (mem_out_with_z<0><50>_rt) MUXCY:S->O 1 0.422 0.000 Madd__n0025_inst_cy_14 (Madd__n0025_inst_cy_14) XORCY:CI->O 4 0.973 0.650 Madd__n0025_inst_sum_8 (_n0025<2>) LUT1_L:I0->LO 1 0.351 0.000 _n0167<2>1 (_n0167<2>) MUXCY:S->O 1 0.422 0.468 Madd__n0026_inst_cy_9 (Madd__n0026_inst_cy_9) LUT2_L:I0->LO 0 0.351 0.000 Madd__n0026_inst_cy_10 (Madd__n0026_inst_cy_10) XORCY:CI->O 1 0.973 0.468 Madd__n0026_inst_sum_4 (_n0026<4>) LUT4_L:I0->LO 1 0.351 0.100 _n0199<3>31 (CHOICE689) LUT4:I3->O 4 0.351 0.650 _n0199<3>64 (mem_out_sortnum<0><3>) LUT4:I1->O 5 0.351 0.663 _n0062110 (lower_than_next<0>) LUT3:I0->O 2 0.351 0.624 pop<2>8_SW0 (N10329) LUT4:I1->O 53 0.351 1.089 pop<2>53_1 (pop<2>53_1) MUXF5:S->O 1 0.693 0.468 track_out<52>58 (track_out_52_OBUF) OBUF:I->O 3.130 track_out_52_OBUF (track_out<52>) ---------------------------------------- Total 19.442ns (12.875ns logic, 6.567ns route) (66.2% logic, 33.8% route) ========================================================================= CPU : 32.11 / 34.98 s | Elapsed : 38.00 / 40.00 s --> Total memory usage is 159680 kilobytes