Release 6.2i - xst G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 2.31 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 2.31 s | Elapsed : 0.00 / 1.00 s --> Reading design: z_channel.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : z_channel.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : z_channel Output Format : NGC Target Device : xc2vp40-5-ff1152 ---- Source Options Top Module Name : z_channel Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : z_channel.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES Optimize Instantiated Primitives : NO tristate2logic : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work. Architecture gtu_types of Entity gtu_types is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd in Library work. Architecture default of Entity zch_table is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd in Library work. Architecture default of Entity sorter is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd in Library work. Architecture default of Entity z_channel is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). ERROR:Xst:834 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd line 28: Generic has not been given a value. --> Total memory usage is 43784 kilobytes