Release 6.2.01i - xst G.29 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 2.24 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 2.24 s | Elapsed : 0.00 / 0.00 s --> Reading design: toplevel.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : toplevel.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : toplevel Output Format : NGC Target Device : xc2vp40-5-ff1152 ---- Source Options Top Module Name : toplevel Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : toplevel.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES Optimize Instantiated Primitives : NO tristate2logic : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3215 - Unit work/TOPLEVEL is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/toplevel.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/toplevel.vhd WARNING:HDLParsers:3215 - Unit work/TOPLEVEL/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/toplevel.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/toplevel.vhd WARNING:HDLParsers:3215 - Unit work/RECONST is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/reconst.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/reconst.vhd WARNING:HDLParsers:3215 - Unit work/RECONST/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/reconst.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/reconst.vhd WARNING:HDLParsers:3215 - Unit work/DIVIDE_WRAPPER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd WARNING:HDLParsers:3215 - Unit work/DIVIDE_WRAPPER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd WARNING:HDLParsers:3481 - No primary, secondary unit in the file /home/cuveland/nfs/vhdl/gtu/syn_ise/cg_divide.vhd. Ignore this file from project file toplevel_vhdl.prj. WARNING:HDLParsers:3215 - Unit work/MULT_WRAPPER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd WARNING:HDLParsers:3215 - Unit work/MULT_WRAPPER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd WARNING:HDLParsers:3215 - Unit work/UNIQUE is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/unique.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/unique.vhd WARNING:HDLParsers:3215 - Unit work/UNIQUE/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/unique.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/unique.vhd WARNING:HDLParsers:3215 - Unit work/ZCH_RESORTER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd WARNING:HDLParsers:3215 - Unit work/ZCH_RESORTER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd WARNING:HDLParsers:3215 - Unit work/ZCH_MERGER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd WARNING:HDLParsers:3215 - Unit work/ZCH_MERGER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd WARNING:HDLParsers:3215 - Unit work/UNIQUIFIER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd WARNING:HDLParsers:3215 - Unit work/UNIQUIFIER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd WARNING:HDLParsers:3215 - Unit work/SEED_MERGER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/seed_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/seed_merger.vhd WARNING:HDLParsers:3215 - Unit work/SEED_MERGER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/seed_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/seed_merger.vhd WARNING:HDLParsers:3215 - Unit work/MATCH is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd WARNING:HDLParsers:3215 - Unit work/MATCH/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd WARNING:HDLParsers:3215 - Unit work/TRACK_TYPES is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/track_types.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd WARNING:HDLParsers:3215 - Unit work/MATCHING_LOGIC is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd WARNING:HDLParsers:3215 - Unit work/MATCHING_LOGIC/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd WARNING:HDLParsers:3215 - Unit work/MATCHING_MEMORY is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_memory.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_memory.vhd WARNING:HDLParsers:3215 - Unit work/MATCHING_MEMORY/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_memory.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_memory.vhd WARNING:HDLParsers:3215 - Unit work/Z_CHANNEL is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd WARNING:HDLParsers:3215 - Unit work/Z_CHANNEL/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd WARNING:HDLParsers:3215 - Unit work/SORTER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd WARNING:HDLParsers:3215 - Unit work/SORTER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd WARNING:HDLParsers:3215 - Unit work/ZCH_TABLE is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd WARNING:HDLParsers:3215 - Unit work/ZCH_TABLE/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd WARNING:HDLParsers:3215 - Unit work/INPUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd WARNING:HDLParsers:3215 - Unit work/INPUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd WARNING:HDLParsers:3215 - Unit work/MASK_ID_LUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd WARNING:HDLParsers:3215 - Unit work/MASK_ID_LUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd WARNING:HDLParsers:3215 - Unit work/YT_LUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd WARNING:HDLParsers:3215 - Unit work/YT_LUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd WARNING:HDLParsers:3215 - Unit work/C1_LUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd WARNING:HDLParsers:3215 - Unit work/C1_LUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd WARNING:HDLParsers:3215 - Unit work/ACOEFF_LUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd WARNING:HDLParsers:3215 - Unit work/ACOEFF_LUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd WARNING:HDLParsers:3215 - Unit work/PROJ_Y is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd WARNING:HDLParsers:3215 - Unit work/PROJ_Y/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd WARNING:HDLParsers:3215 - Unit work/PROJ_D is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd WARNING:HDLParsers:3215 - Unit work/PROJ_D/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd WARNING:HDLParsers:3215 - Unit work/BUFFER_MERGER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd WARNING:HDLParsers:3215 - Unit work/BUFFER_MERGER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd WARNING:HDLParsers:3215 - Unit work/FIFO_DC_WRAPPER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd WARNING:HDLParsers:3215 - Unit work/FIFO_DC_WRAPPER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd WARNING:HDLParsers:3481 - No primary, secondary unit in the file /home/cuveland/nfs/vhdl/gtu/syn_ise/cg_fifo_dc.vhd. Ignore this file from project file toplevel_vhdl.prj. WARNING:HDLParsers:3215 - Unit work/INPUTCONTROL is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/inputcontrol.vhd WARNING:HDLParsers:3215 - Unit work/INPUTCONTROL/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/inputcontrol.vhd WARNING:HDLParsers:3215 - Unit work/GTU_TYPES is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/gtu_types.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd WARNING:HDLParsers:3215 - Unit work/GTU_TYPES is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/gtu_types.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work. Architecture gtu_types of Entity gtu_types is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd in Library work. Architecture default of Entity fifo_dc_wrapper is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd in Library work. Architecture default of Entity mask_id_lut is up to date. Architecture default of Entity yt_lut is up to date. Architecture default of Entity c1_lut is up to date. Architecture default of Entity acoeff_lut is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd in Library work. Architecture default of Entity mult_wrapper is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd in Library work. Architecture default of Entity divide_wrapper is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/seed_merger.vhd in Library work. Architecture default of Entity seed_merger is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd in Library work. Architecture default of Entity uniquifier is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work. Architecture default of Entity zch_merger is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd in Library work. Architecture default of Entity zch_resorter is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_memory.vhd in Library work. Architecture default of Entity matching_memory is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd in Library work. Architecture default of Entity matching_logic is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd in Library work. Architecture default of Entity zch_table is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd in Library work. Architecture default of Entity sorter is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/inputcontrol.vhd in Library work. Architecture default of Entity inputcontrol is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd in Library work. Architecture default of Entity buffer_merger is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd in Library work. Architecture default of Entity proj_d is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd in Library work. Architecture default of Entity proj_y is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd in Library work. Architecture default of Entity input is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd in Library work. Architecture default of Entity z_channel is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd in Library work. Architecture default of Entity match is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/unique.vhd in Library work. Architecture default of Entity unique is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/reconst.vhd in Library work. Architecture default of Entity reconst is up to date. Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/toplevel.vhd in Library work. Architecture default of Entity toplevel is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd line 148: The following signals are missing in the process sensitivity list: data<1><23>, data<1><22>, data<1><21>, data<1><20>, data<0><23>, data<0><22>, data<0><21>, data<0><20>. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:753 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Unconnected output port 'full' of component 'cg_fifo_dc'. WARNING:Xst:766 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Generating a Black Box for component . Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 channel_index = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 zunit = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). depth = 8 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 channel_index = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 zunit = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 channel_index = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 zunit = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 channel_index = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 zunit = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 channel_index = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 zunit = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 channel_index = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 zunit = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 channel_index = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 zunit = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 channel_index = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 zunit = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 channel_index = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 zunit = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 channel_index = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 zunit = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 channel_index = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 zunit = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 channel_index = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 zunit = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 channel_index = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 zunit = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 channel_index = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 zunit = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 channel_index = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 zunit = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 channel_index = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 zunit = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 channel_index = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 zunit = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 channel_index = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 zunit = 0 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). seedline = 3 line_mask = 0 Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). seedline = 3 line_mask = 0 WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<3><1>, inc<3><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<3><1>, inc<3><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<3><1>, inc<3><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<3><1>, inc<3><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<3><1>, inc<3><0>. Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). seedline = 2 line_mask = 8 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). seedline = 2 line_mask = 8 WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<2><1>, inc<2><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<2><1>, inc<2><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<2><1>, inc<2><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<2><1>, inc<2><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<2><1>, inc<2><0>. Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). seedline = 1 line_mask = 12 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). seedline = 1 line_mask = 12 WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<1><1>, inc<1><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<1><1>, inc<1><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<1><1>, inc<1><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<1><1>, inc<1><0>. WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list: inc<1><1>, inc<1><0>. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). track_width = 52 WARNING:Xst:1610 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 101: Width mismatch. has a width of 42 bits but assigned expression is 52-bit wide. WARNING:Xst:1610 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 110: Width mismatch. has a width of 52 bits but assigned expression is 42-bit wide. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). track_width = 53 WARNING:Xst:1610 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 101: Width mismatch. has a width of 42 bits but assigned expression is 53-bit wide. WARNING:Xst:1610 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 110: Width mismatch. has a width of 53 bits but assigned expression is 42-bit wide. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd line 200: The following signals are missing in the process sensitivity list: mem_out<1><41>, mem_out<1><40>, mem_out<1><39>, mem_out<1><38>, mem_out<1><37>, mem_out<1><36>, mem_out<1><35>, mem_out<1><34>, mem_out<1><33>, mem_out<1><32>, mem_out<1><31>, mem_out<1><30>, mem_out<1><29>, mem_out<1><28>, mem_out<1><27>, mem_out<1><26>, mem_out<1><25>, mem_out<1><24>, mem_out<1><23>, mem_out<1><22>, mem_out<1><21>, mem_out<1><20>, mem_out<1><19>, mem_out<1><18>, mem_out<1><17>, mem_out<1><16>, mem_out<1><15>, mem_out<1><14>, mem_out<1><13>, mem_out<1><12>, mem_out<1><11>, mem_out<1><10>, mem_out<1><9>, mem_out<1><8>, mem_out<1><7>, mem_out<1><6>, mem_out<1><5>, mem_out<1><4>, mem_out<1><3>, mem_out<1><2>, mem_out<1><1>, mem_out<1><0>, mem_out<0><41>, mem_out<0><40>, mem_out<0><39>, mem_out<0><38>, mem_out<0><37>, mem_out<0><36>, mem_out<0><35>, mem_out<0><34>, mem_out<0><33>, mem_out<0><32>, mem_out<0><31>, mem_out<0><30>, mem_out<0><29>, mem_out<0><28>, mem_out<0><27>, mem_out<0><26>, mem_out<0><25>, mem_out<0><24>, mem_out<0><23>, mem_out<0><22>, mem_out<0><21>, mem_out<0><20>, mem_out<0><19>, mem_out<0><18>, mem_out<0><17>, mem_out<0><16>, mem_out<0><15>, mem_out<0><14>, mem_out<0><13>, mem_out<0><12>, mem_out<0><11>, mem_out<0><10>, mem_out<0><9>, mem_out<0><8>, mem_out<0><7>, mem_out<0><6>, mem_out<0><5>, mem_out<0><4>, mem_out<0><3>, mem_out<0><2>, mem_out<0><1>, mem_out<0><0>. Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). track_width = 42 Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 5 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 4 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 3 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 2 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 1 Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). plane = 0 Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:766 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd line 60: Generating a Black Box for component . Entity analyzed. Unit generated. Analyzing generic Entity (Architecture ). div_stages = 7 WARNING:Xst:753 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd line 58: Unconnected output port 'remd' of component 'cg_divide'. WARNING:Xst:766 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd line 58: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd. WARNING:Xst:647 - Input is never used. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 19-bit register for signal . Found 19-bit adder for signal . Summary: inferred 19 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 22x13-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 22x13-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 22x13-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 22x13-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 22x13-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 22x13-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 22x13-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd. Using one-hot encoding for signal . Found 2-bit adder for signal <$n0027> created at line 72. Found 2-bit adder for signal <$n0029> created at line 72. Found 32-bit adder for signal <$n0030> created at line 72. Found 32-bit adder for signal <$n0031> created at line 72. Found 32-bit comparator greatequal for signal <$n0039> created at line 169. Found 32-bit adder for signal <$n0040> created at line 72. Found 33-bit adder for signal <$n0043> created at line 72. Found 32-bit adder for signal <$n0044> created at line 72. Found 33-bit adder for signal <$n0047> created at line 72. Found 32-bit adder for signal <$n0062> created at line 72. Found 32-bit adder for signal <$n0071> created at line 72. Found 6-bit comparator equal for signal <$n0078> created at line 152. Found 6-bit comparator equal for signal <$n0079> created at line 152. Found 6-bit comparator equal for signal <$n0080> created at line 152. Found 6-bit comparator equal for signal <$n0081> created at line 152. Found 6-bit comparator equal for signal <$n0082> created at line 152. Found 6-bit comparator equal for signal <$n0083> created at line 152. Found 1-bit adder carry out for signal <$n0084> created at line 72. Found 1-bit adder carry out for signal <$n0085> created at line 72. Found 42-bit register for signal . Found 42-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 324 1-bit 2-to-1 multiplexers. Summary: inferred 87 D-type flip-flop(s). inferred 12 Adder/Subtracter(s). inferred 7 Comparator(s). inferred 324 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd. Found 16x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 16-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 16x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 16-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 4-bit comparator not equal for signal <$n0016> created at line 166. Found 4-bit comparator not equal for signal <$n0017> created at line 166. Found 3-bit comparator less for signal <$n0029> created at line 184. Found 3-bit comparator equal for signal <$n0030> created at line 184. Found 7-bit comparator less for signal <$n0031> created at line 184. Found 4-bit up counter for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 4-bit up counter for signal . Found 42 1-bit 2-to-1 multiplexers. Summary: inferred 2 RAM(s). inferred 4 Counter(s). inferred 9 D-type flip-flop(s). inferred 5 Comparator(s). inferred 42 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd. WARNING:Xst:647 - Input > is never used. Using one-hot encoding for signal . Found 2-bit adder for signal <$n0027> created at line 72. Found 2-bit adder for signal <$n0029> created at line 72. Found 32-bit adder for signal <$n0030> created at line 72. Found 32-bit adder for signal <$n0031> created at line 72. Found 32-bit comparator greatequal for signal <$n0039> created at line 169. Found 32-bit adder for signal <$n0040> created at line 72. Found 33-bit adder for signal <$n0043> created at line 72. Found 32-bit adder for signal <$n0044> created at line 72. Found 33-bit adder for signal <$n0047> created at line 72. Found 32-bit adder for signal <$n0062> created at line 72. Found 32-bit adder for signal <$n0071> created at line 72. Found 6-bit comparator equal for signal <$n0078> created at line 152. Found 6-bit comparator equal for signal <$n0079> created at line 152. Found 6-bit comparator equal for signal <$n0080> created at line 152. Found 6-bit comparator equal for signal <$n0081> created at line 152. Found 6-bit comparator equal for signal <$n0082> created at line 152. Found 6-bit comparator equal for signal <$n0083> created at line 152. Found 1-bit adder carry out for signal <$n0084> created at line 72. Found 1-bit adder carry out for signal <$n0085> created at line 72. Found 42-bit register for signal . Found 42-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 324 1-bit 2-to-1 multiplexers. Summary: inferred 87 D-type flip-flop(s). inferred 12 Adder/Subtracter(s). inferred 7 Comparator(s). inferred 324 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. Found 5-bit adder for signal <$n0004> created at line 103. Found 6-bit adder for signal <$n0012> created at line 103. Found 6-bit adder for signal <$n0013>. Found 4-bit adder for signal <$n0017> created at line 94. Found 6-bit adder for signal <$n0022> created at line 103. Found 6-bit adder for signal <$n0023>. Found 4-bit adder for signal <$n0048> created at line 103. Found 3-bit adder for signal <$n0049> created at line 94. Found 3-bit comparator not equal for signal <$n0053> created at line 178. Found 3-bit comparator not equal for signal <$n0057> created at line 178. Found 3-bit comparator not equal for signal <$n0061> created at line 178. Found 4-bit adder for signal <$n0067>. Found 4-bit adder for signal <$n0072>. Found 4-bit subtractor for signal <$n0088> created at line 103. Found 4-bit subtractor for signal <$n0089> created at line 103. Found 4-bit subtractor for signal <$n0090> created at line 103. Found 4-bit comparator less for signal <$n0091> created at line 182. Found 4-bit comparator equal for signal <$n0092> created at line 182. Found 7-bit comparator less for signal <$n0093> created at line 182. Found 4-bit comparator less for signal <$n0094> created at line 182. Found 4-bit comparator equal for signal <$n0095> created at line 182. Found 7-bit comparator less for signal <$n0096> created at line 182. Found 4-bit comparator less for signal <$n0097> created at line 182. Found 4-bit comparator equal for signal <$n0098> created at line 182. Found 7-bit comparator less for signal <$n0099> created at line 182. Found 4x3-bit multiplier for signal <$n0103> created at line 103. Found 4x3-bit multiplier for signal <$n0104> created at line 103. Found 4x3-bit multiplier for signal <$n0105> created at line 103. Found 3-bit up counter for signal . Found 3-bit register for signal . Found 9-bit register for signal . Found 3-bit up counter for signal . Summary: inferred 3 RAM(s). inferred 6 Counter(s). inferred 12 D-type flip-flop(s). inferred 13 Adder/Subtracter(s). inferred 3 Multiplier(s). inferred 12 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd. WARNING:Xst:647 - Input > is never used. Using one-hot encoding for signal . Found 2-bit adder for signal <$n0027> created at line 72. Found 2-bit adder for signal <$n0029> created at line 72. Found 32-bit adder for signal <$n0030> created at line 72. Found 32-bit adder for signal <$n0031> created at line 72. Found 32-bit comparator greatequal for signal <$n0039> created at line 169. Found 32-bit adder for signal <$n0040> created at line 72. Found 33-bit adder for signal <$n0043> created at line 72. Found 32-bit adder for signal <$n0044> created at line 72. Found 33-bit adder for signal <$n0047> created at line 72. Found 32-bit adder for signal <$n0062> created at line 72. Found 32-bit adder for signal <$n0071> created at line 72. Found 6-bit comparator equal for signal <$n0078> created at line 152. Found 6-bit comparator equal for signal <$n0079> created at line 152. Found 6-bit comparator equal for signal <$n0080> created at line 152. Found 6-bit comparator equal for signal <$n0081> created at line 152. Found 6-bit comparator equal for signal <$n0082> created at line 152. Found 6-bit comparator equal for signal <$n0083> created at line 152. Found 1-bit adder carry out for signal <$n0084> created at line 72. Found 1-bit adder carry out for signal <$n0085> created at line 72. Found 42-bit register for signal . Found 42-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 324 1-bit 2-to-1 multiplexers. Summary: inferred 87 D-type flip-flop(s). inferred 12 Adder/Subtracter(s). inferred 7 Comparator(s). inferred 324 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/seed_merger.vhd. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 8x52-bit dual-port distributed RAM for signal >. ----------------------------------------------------------------------- | aspect ratio | 8-word x 52-bit | | | clock | connected to signal | rise | | write enable | connected to signal > | high | | address | connected to signal > | | | dual address | connected to signal > | | | data in | connected to signal > | | | data out | not connected | | | dual data out | connected to signal > | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 3-bit comparator not equal for signal <$n0024> created at line 149. Found 3-bit comparator not equal for signal <$n0026> created at line 149. Found 3-bit comparator not equal for signal <$n0028> created at line 149. Found 3-bit comparator less for signal <$n0045> created at line 153. Found 3-bit comparator equal for signal <$n0046> created at line 153. Found 7-bit comparator less for signal <$n0047> created at line 153. Found 3-bit comparator less for signal <$n0048> created at line 153. Found 3-bit comparator equal for signal <$n0049> created at line 153. Found 7-bit comparator less for signal <$n0050> created at line 153. Found 3-bit comparator less for signal <$n0051> created at line 153. Found 3-bit comparator equal for signal <$n0052> created at line 153. Found 7-bit comparator less for signal <$n0053> created at line 153. Found 3-bit up counter for signal . Found 3-bit register for signal . Found 9-bit register for signal . Found 3-bit up counter for signal . Summary: inferred 3 RAM(s). inferred 6 Counter(s). inferred 12 D-type flip-flop(s). inferred 12 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 3-bit adder for signal <$n0004> created at line 193. Found 6-bit adder for signal <$n0038> created at line 129. Found 7-bit comparator less for signal <$n0046> created at line 172. Found 7-bit comparator greater for signal <$n0047> created at line 173. Found 7-bit comparator less for signal <$n0048> created at line 174. Found 7-bit comparator greater for signal <$n0049> created at line 175. Found 7-bit comparator less for signal <$n0057> created at line 172. Found 7-bit comparator greater for signal <$n0058> created at line 173. Found 7-bit comparator less for signal <$n0059> created at line 174. Found 7-bit comparator greater for signal <$n0060> created at line 175. Found 7-bit comparator less for signal <$n0068> created at line 172. Found 7-bit comparator greater for signal <$n0069> created at line 173. Found 7-bit comparator less for signal <$n0070> created at line 174. Found 7-bit comparator greater for signal <$n0071> created at line 175. Found 7-bit comparator less for signal <$n0079> created at line 172. Found 7-bit comparator greater for signal <$n0080> created at line 173. Found 7-bit comparator less for signal <$n0081> created at line 174. Found 7-bit comparator greater for signal <$n0082> created at line 175. Found 7-bit comparator less for signal <$n0090> created at line 172. Found 7-bit comparator greater for signal <$n0091> created at line 173. Found 7-bit comparator less for signal <$n0092> created at line 174. Found 7-bit comparator greater for signal <$n0093> created at line 175. Found 3-bit adder for signal <$n0094> created at line 194. Found 3-bit adder for signal <$n0096> created at line 206. Found 3-bit adder for signal <$n0097> created at line 218. Found 3-bit comparator greatequal for signal <$n0100> created at line 238. Found 3-bit adder for signal <$n0102> created at line 194. Found 3-bit adder for signal <$n0103> created at line 194. Found 3-bit adder for signal <$n0104> created at line 194. Found 3-bit adder for signal <$n0106> created at line 206. Found 3-bit adder for signal <$n0108> created at line 206. Found 3-bit adder for signal <$n0110> created at line 206. Found 3-bit adder for signal <$n0111> created at line 218. Found 3-bit adder for signal <$n0112> created at line 218. Found 3-bit adder for signal <$n0113> created at line 218. Found 3-bit comparator less for signal <$n0139> created at line 150. Found 3-bit comparator equal for signal <$n0140> created at line 150. Found 10-bit comparator less for signal <$n0141> created at line 150. Found 3-bit comparator greater for signal <$n0142> created at line 153. Found 10-bit comparator greater for signal <$n0143> created at line 153. Found 3-bit comparator less for signal <$n0144> created at line 156. Found 3-bit comparator equal for signal <$n0145> created at line 156. Found 10-bit comparator less for signal <$n0146> created at line 156. Found 3-bit comparator greater for signal <$n0147> created at line 159. Found 10-bit comparator greater for signal <$n0148> created at line 159. Found 3-bit comparator less for signal <$n0149> created at line 162. Found 3-bit comparator equal for signal <$n0150> created at line 162. Found 10-bit comparator less for signal <$n0151> created at line 162. Found 3-bit comparator greater for signal <$n0152> created at line 165. Found 10-bit comparator greater for signal <$n0153> created at line 165. Found 3-bit comparator less for signal <$n0154> created at line 168. Found 3-bit comparator equal for signal <$n0155> created at line 168. Found 10-bit comparator less for signal <$n0156> created at line 168. Found 3-bit comparator less for signal <$n0157> created at line 150. Found 3-bit comparator equal for signal <$n0158> created at line 150. Found 10-bit comparator less for signal <$n0159> created at line 150. Found 3-bit comparator greater for signal <$n0160> created at line 153. Found 10-bit comparator greater for signal <$n0161> created at line 153. Found 3-bit comparator less for signal <$n0162> created at line 156. Found 3-bit comparator equal for signal <$n0163> created at line 156. Found 10-bit comparator less for signal <$n0164> created at line 156. Found 3-bit comparator greater for signal <$n0165> created at line 159. Found 10-bit comparator greater for signal <$n0166> created at line 159. Found 3-bit comparator less for signal <$n0167> created at line 162. Found 3-bit comparator equal for signal <$n0168> created at line 162. Found 10-bit comparator less for signal <$n0169> created at line 162. Found 3-bit comparator greater for signal <$n0170> created at line 165. Found 10-bit comparator greater for signal <$n0171> created at line 165. Found 3-bit comparator less for signal <$n0172> created at line 168. Found 3-bit comparator equal for signal <$n0173> created at line 168. Found 10-bit comparator less for signal <$n0174> created at line 168. Found 3-bit comparator less for signal <$n0175> created at line 150. Found 3-bit comparator equal for signal <$n0176> created at line 150. Found 10-bit comparator less for signal <$n0177> created at line 150. Found 3-bit comparator greater for signal <$n0178> created at line 153. Found 10-bit comparator greater for signal <$n0179> created at line 153. Found 3-bit comparator less for signal <$n0180> created at line 156. Found 3-bit comparator equal for signal <$n0181> created at line 156. Found 10-bit comparator less for signal <$n0182> created at line 156. Found 3-bit comparator greater for signal <$n0183> created at line 159. Found 10-bit comparator greater for signal <$n0184> created at line 159. Found 3-bit comparator less for signal <$n0185> created at line 162. Found 3-bit comparator equal for signal <$n0186> created at line 162. Found 10-bit comparator less for signal <$n0187> created at line 162. Found 3-bit comparator greater for signal <$n0188> created at line 165. Found 10-bit comparator greater for signal <$n0189> created at line 165. Found 3-bit comparator less for signal <$n0190> created at line 168. Found 3-bit comparator equal for signal <$n0191> created at line 168. Found 10-bit comparator less for signal <$n0192> created at line 168. Found 3-bit comparator less for signal <$n0193> created at line 150. Found 3-bit comparator equal for signal <$n0194> created at line 150. Found 10-bit comparator less for signal <$n0195> created at line 150. Found 3-bit comparator greater for signal <$n0196> created at line 153. Found 10-bit comparator greater for signal <$n0197> created at line 153. Found 3-bit comparator less for signal <$n0198> created at line 156. Found 3-bit comparator equal for signal <$n0199> created at line 156. Found 10-bit comparator less for signal <$n0200> created at line 156. Found 3-bit comparator greater for signal <$n0201> created at line 159. Found 10-bit comparator greater for signal <$n0202> created at line 159. Found 3-bit comparator less for signal <$n0203> created at line 162. Found 3-bit comparator equal for signal <$n0204> created at line 162. Found 10-bit comparator less for signal <$n0205> created at line 162. Found 3-bit comparator greater for signal <$n0206> created at line 165. Found 10-bit comparator greater for signal <$n0207> created at line 165. Found 3-bit comparator less for signal <$n0208> created at line 168. Found 3-bit comparator equal for signal <$n0209> created at line 168. Found 10-bit comparator less for signal <$n0210> created at line 168. Found 3-bit comparator less for signal <$n0211> created at line 150. Found 3-bit comparator equal for signal <$n0212> created at line 150. Found 10-bit comparator less for signal <$n0213> created at line 150. Found 3-bit comparator greater for signal <$n0214> created at line 153. Found 10-bit comparator greater for signal <$n0215> created at line 153. Found 3-bit comparator less for signal <$n0216> created at line 156. Found 3-bit comparator equal for signal <$n0217> created at line 156. Found 10-bit comparator less for signal <$n0218> created at line 156. Found 3-bit comparator greater for signal <$n0219> created at line 159. Found 10-bit comparator greater for signal <$n0220> created at line 159. Found 3-bit comparator less for signal <$n0221> created at line 162. Found 3-bit comparator equal for signal <$n0222> created at line 162. Found 10-bit comparator less for signal <$n0223> created at line 162. Found 3-bit comparator greater for signal <$n0224> created at line 165. Found 10-bit comparator greater for signal <$n0225> created at line 165. Found 3-bit comparator less for signal <$n0226> created at line 168. Found 3-bit comparator equal for signal <$n0227> created at line 168. Found 10-bit comparator less for signal <$n0228> created at line 168. Found 7-bit subtractor for signal . Found 3-bit adder for signal . Found 10-bit subtractor for signal . Found 10-bit adder for signal . Found 10-bit subtractor for signal . Found 10-bit adder for signal . Found 36 1-bit 2-to-1 multiplexers. Summary: inferred 20 Adder/Subtracter(s). inferred 111 Comparator(s). inferred 36 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 3-bit adder for signal <$n0003> created at line 193. Found 6-bit adder for signal <$n0038> created at line 129. Found 7-bit comparator less for signal <$n0046> created at line 172. Found 7-bit comparator greater for signal <$n0047> created at line 173. Found 7-bit comparator less for signal <$n0048> created at line 174. Found 7-bit comparator greater for signal <$n0049> created at line 175. Found 7-bit comparator less for signal <$n0057> created at line 172. Found 7-bit comparator greater for signal <$n0058> created at line 173. Found 7-bit comparator less for signal <$n0059> created at line 174. Found 7-bit comparator greater for signal <$n0060> created at line 175. Found 7-bit comparator less for signal <$n0068> created at line 172. Found 7-bit comparator greater for signal <$n0069> created at line 173. Found 7-bit comparator less for signal <$n0070> created at line 174. Found 7-bit comparator greater for signal <$n0071> created at line 175. Found 7-bit comparator less for signal <$n0079> created at line 172. Found 7-bit comparator greater for signal <$n0080> created at line 173. Found 7-bit comparator less for signal <$n0081> created at line 174. Found 7-bit comparator greater for signal <$n0082> created at line 175. Found 7-bit comparator less for signal <$n0090> created at line 172. Found 7-bit comparator greater for signal <$n0091> created at line 173. Found 7-bit comparator less for signal <$n0092> created at line 174. Found 7-bit comparator greater for signal <$n0093> created at line 175. Found 3-bit adder for signal <$n0094> created at line 194. Found 3-bit adder for signal <$n0096> created at line 206. Found 3-bit adder for signal <$n0097> created at line 218. Found 3-bit comparator greatequal for signal <$n0100> created at line 238. Found 3-bit adder for signal <$n0102> created at line 194. Found 3-bit adder for signal <$n0103> created at line 194. Found 3-bit adder for signal <$n0104> created at line 194. Found 3-bit adder for signal <$n0106> created at line 206. Found 3-bit adder for signal <$n0108> created at line 206. Found 3-bit adder for signal <$n0110> created at line 206. Found 3-bit adder for signal <$n0111> created at line 218. Found 3-bit adder for signal <$n0112> created at line 218. Found 3-bit adder for signal <$n0113> created at line 218. Found 3-bit comparator less for signal <$n0139> created at line 150. Found 3-bit comparator equal for signal <$n0140> created at line 150. Found 10-bit comparator less for signal <$n0141> created at line 150. Found 3-bit comparator greater for signal <$n0142> created at line 153. Found 10-bit comparator greater for signal <$n0143> created at line 153. Found 3-bit comparator less for signal <$n0144> created at line 156. Found 3-bit comparator equal for signal <$n0145> created at line 156. Found 10-bit comparator less for signal <$n0146> created at line 156. Found 3-bit comparator greater for signal <$n0147> created at line 159. Found 10-bit comparator greater for signal <$n0148> created at line 159. Found 3-bit comparator less for signal <$n0149> created at line 162. Found 3-bit comparator equal for signal <$n0150> created at line 162. Found 10-bit comparator less for signal <$n0151> created at line 162. Found 3-bit comparator greater for signal <$n0152> created at line 165. Found 10-bit comparator greater for signal <$n0153> created at line 165. Found 3-bit comparator less for signal <$n0154> created at line 168. Found 3-bit comparator equal for signal <$n0155> created at line 168. Found 10-bit comparator less for signal <$n0156> created at line 168. Found 3-bit comparator less for signal <$n0157> created at line 150. Found 3-bit comparator equal for signal <$n0158> created at line 150. Found 10-bit comparator less for signal <$n0159> created at line 150. Found 3-bit comparator greater for signal <$n0160> created at line 153. Found 10-bit comparator greater for signal <$n0161> created at line 153. Found 3-bit comparator less for signal <$n0162> created at line 156. Found 3-bit comparator equal for signal <$n0163> created at line 156. Found 10-bit comparator less for signal <$n0164> created at line 156. Found 3-bit comparator greater for signal <$n0165> created at line 159. Found 10-bit comparator greater for signal <$n0166> created at line 159. Found 3-bit comparator less for signal <$n0167> created at line 162. Found 3-bit comparator equal for signal <$n0168> created at line 162. Found 10-bit comparator less for signal <$n0169> created at line 162. Found 3-bit comparator greater for signal <$n0170> created at line 165. Found 10-bit comparator greater for signal <$n0171> created at line 165. Found 3-bit comparator less for signal <$n0172> created at line 168. Found 3-bit comparator equal for signal <$n0173> created at line 168. Found 10-bit comparator less for signal <$n0174> created at line 168. Found 3-bit comparator less for signal <$n0175> created at line 150. Found 3-bit comparator equal for signal <$n0176> created at line 150. Found 10-bit comparator less for signal <$n0177> created at line 150. Found 3-bit comparator greater for signal <$n0178> created at line 153. Found 10-bit comparator greater for signal <$n0179> created at line 153. Found 3-bit comparator less for signal <$n0180> created at line 156. Found 3-bit comparator equal for signal <$n0181> created at line 156. Found 10-bit comparator less for signal <$n0182> created at line 156. Found 3-bit comparator greater for signal <$n0183> created at line 159. Found 10-bit comparator greater for signal <$n0184> created at line 159. Found 3-bit comparator less for signal <$n0185> created at line 162. Found 3-bit comparator equal for signal <$n0186> created at line 162. Found 10-bit comparator less for signal <$n0187> created at line 162. Found 3-bit comparator greater for signal <$n0188> created at line 165. Found 10-bit comparator greater for signal <$n0189> created at line 165. Found 3-bit comparator less for signal <$n0190> created at line 168. Found 3-bit comparator equal for signal <$n0191> created at line 168. Found 10-bit comparator less for signal <$n0192> created at line 168. Found 3-bit comparator less for signal <$n0193> created at line 150. Found 3-bit comparator equal for signal <$n0194> created at line 150. Found 10-bit comparator less for signal <$n0195> created at line 150. Found 3-bit comparator greater for signal <$n0196> created at line 153. Found 10-bit comparator greater for signal <$n0197> created at line 153. Found 3-bit comparator less for signal <$n0198> created at line 156. Found 3-bit comparator equal for signal <$n0199> created at line 156. Found 10-bit comparator less for signal <$n0200> created at line 156. Found 3-bit comparator greater for signal <$n0201> created at line 159. Found 10-bit comparator greater for signal <$n0202> created at line 159. Found 3-bit comparator less for signal <$n0203> created at line 162. Found 3-bit comparator equal for signal <$n0204> created at line 162. Found 10-bit comparator less for signal <$n0205> created at line 162. Found 3-bit comparator greater for signal <$n0206> created at line 165. Found 10-bit comparator greater for signal <$n0207> created at line 165. Found 3-bit comparator less for signal <$n0208> created at line 168. Found 3-bit comparator equal for signal <$n0209> created at line 168. Found 10-bit comparator less for signal <$n0210> created at line 168. Found 3-bit comparator less for signal <$n0211> created at line 150. Found 3-bit comparator equal for signal <$n0212> created at line 150. Found 10-bit comparator less for signal <$n0213> created at line 150. Found 3-bit comparator greater for signal <$n0214> created at line 153. Found 10-bit comparator greater for signal <$n0215> created at line 153. Found 3-bit comparator less for signal <$n0216> created at line 156. Found 3-bit comparator equal for signal <$n0217> created at line 156. Found 10-bit comparator less for signal <$n0218> created at line 156. Found 3-bit comparator greater for signal <$n0219> created at line 159. Found 10-bit comparator greater for signal <$n0220> created at line 159. Found 3-bit comparator less for signal <$n0221> created at line 162. Found 3-bit comparator equal for signal <$n0222> created at line 162. Found 10-bit comparator less for signal <$n0223> created at line 162. Found 3-bit comparator greater for signal <$n0224> created at line 165. Found 10-bit comparator greater for signal <$n0225> created at line 165. Found 3-bit comparator less for signal <$n0226> created at line 168. Found 3-bit comparator equal for signal <$n0227> created at line 168. Found 10-bit comparator less for signal <$n0228> created at line 168. Found 7-bit subtractor for signal . Found 3-bit adder for signal . Found 10-bit subtractor for signal . Found 10-bit adder for signal . Found 10-bit subtractor for signal . Found 10-bit adder for signal . Found 36 1-bit 2-to-1 multiplexers. Summary: inferred 20 Adder/Subtracter(s). inferred 111 Comparator(s). inferred 36 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 3-bit adder for signal <$n0002> created at line 193. Found 6-bit adder for signal <$n0038> created at line 129. Found 7-bit comparator less for signal <$n0046> created at line 172. Found 7-bit comparator greater for signal <$n0047> created at line 173. Found 7-bit comparator less for signal <$n0048> created at line 174. Found 7-bit comparator greater for signal <$n0049> created at line 175. Found 7-bit comparator less for signal <$n0057> created at line 172. Found 7-bit comparator greater for signal <$n0058> created at line 173. Found 7-bit comparator less for signal <$n0059> created at line 174. Found 7-bit comparator greater for signal <$n0060> created at line 175. Found 7-bit comparator less for signal <$n0068> created at line 172. Found 7-bit comparator greater for signal <$n0069> created at line 173. Found 7-bit comparator less for signal <$n0070> created at line 174. Found 7-bit comparator greater for signal <$n0071> created at line 175. Found 7-bit comparator less for signal <$n0079> created at line 172. Found 7-bit comparator greater for signal <$n0080> created at line 173. Found 7-bit comparator less for signal <$n0081> created at line 174. Found 7-bit comparator greater for signal <$n0082> created at line 175. Found 7-bit comparator less for signal <$n0090> created at line 172. Found 7-bit comparator greater for signal <$n0091> created at line 173. Found 7-bit comparator less for signal <$n0092> created at line 174. Found 7-bit comparator greater for signal <$n0093> created at line 175. Found 3-bit adder for signal <$n0094> created at line 194. Found 3-bit adder for signal <$n0096> created at line 206. Found 3-bit adder for signal <$n0097> created at line 218. Found 3-bit comparator greatequal for signal <$n0100> created at line 238. Found 3-bit adder for signal <$n0102> created at line 194. Found 3-bit adder for signal <$n0103> created at line 194. Found 3-bit adder for signal <$n0104> created at line 194. Found 3-bit adder for signal <$n0106> created at line 206. Found 3-bit adder for signal <$n0108> created at line 206. Found 3-bit adder for signal <$n0110> created at line 206. Found 3-bit adder for signal <$n0111> created at line 218. Found 3-bit adder for signal <$n0112> created at line 218. Found 3-bit adder for signal <$n0113> created at line 218. Found 3-bit comparator less for signal <$n0139> created at line 150. Found 3-bit comparator equal for signal <$n0140> created at line 150. Found 10-bit comparator less for signal <$n0141> created at line 150. Found 3-bit comparator greater for signal <$n0142> created at line 153. Found 10-bit comparator greater for signal <$n0143> created at line 153. Found 3-bit comparator less for signal <$n0144> created at line 156. Found 3-bit comparator equal for signal <$n0145> created at line 156. Found 10-bit comparator less for signal <$n0146> created at line 156. Found 3-bit comparator greater for signal <$n0147> created at line 159. Found 10-bit comparator greater for signal <$n0148> created at line 159. Found 3-bit comparator less for signal <$n0149> created at line 162. Found 3-bit comparator equal for signal <$n0150> created at line 162. Found 10-bit comparator less for signal <$n0151> created at line 162. Found 3-bit comparator greater for signal <$n0152> created at line 165. Found 10-bit comparator greater for signal <$n0153> created at line 165. Found 3-bit comparator less for signal <$n0154> created at line 168. Found 3-bit comparator equal for signal <$n0155> created at line 168. Found 10-bit comparator less for signal <$n0156> created at line 168. Found 3-bit comparator less for signal <$n0157> created at line 150. Found 3-bit comparator equal for signal <$n0158> created at line 150. Found 10-bit comparator less for signal <$n0159> created at line 150. Found 3-bit comparator greater for signal <$n0160> created at line 153. Found 10-bit comparator greater for signal <$n0161> created at line 153. Found 3-bit comparator less for signal <$n0162> created at line 156. Found 3-bit comparator equal for signal <$n0163> created at line 156. Found 10-bit comparator less for signal <$n0164> created at line 156. Found 3-bit comparator greater for signal <$n0165> created at line 159. Found 10-bit comparator greater for signal <$n0166> created at line 159. Found 3-bit comparator less for signal <$n0167> created at line 162. Found 3-bit comparator equal for signal <$n0168> created at line 162. Found 10-bit comparator less for signal <$n0169> created at line 162. Found 3-bit comparator greater for signal <$n0170> created at line 165. Found 10-bit comparator greater for signal <$n0171> created at line 165. Found 3-bit comparator less for signal <$n0172> created at line 168. Found 3-bit comparator equal for signal <$n0173> created at line 168. Found 10-bit comparator less for signal <$n0174> created at line 168. Found 3-bit comparator less for signal <$n0175> created at line 150. Found 3-bit comparator equal for signal <$n0176> created at line 150. Found 10-bit comparator less for signal <$n0177> created at line 150. Found 3-bit comparator greater for signal <$n0178> created at line 153. Found 10-bit comparator greater for signal <$n0179> created at line 153. Found 3-bit comparator less for signal <$n0180> created at line 156. Found 3-bit comparator equal for signal <$n0181> created at line 156. Found 10-bit comparator less for signal <$n0182> created at line 156. Found 3-bit comparator greater for signal <$n0183> created at line 159. Found 10-bit comparator greater for signal <$n0184> created at line 159. Found 3-bit comparator less for signal <$n0185> created at line 162. Found 3-bit comparator equal for signal <$n0186> created at line 162. Found 10-bit comparator less for signal <$n0187> created at line 162. Found 3-bit comparator greater for signal <$n0188> created at line 165. Found 10-bit comparator greater for signal <$n0189> created at line 165. Found 3-bit comparator less for signal <$n0190> created at line 168. Found 3-bit comparator equal for signal <$n0191> created at line 168. Found 10-bit comparator less for signal <$n0192> created at line 168. Found 3-bit comparator less for signal <$n0193> created at line 150. Found 3-bit comparator equal for signal <$n0194> created at line 150. Found 10-bit comparator less for signal <$n0195> created at line 150. Found 3-bit comparator greater for signal <$n0196> created at line 153. Found 10-bit comparator greater for signal <$n0197> created at line 153. Found 3-bit comparator less for signal <$n0198> created at line 156. Found 3-bit comparator equal for signal <$n0199> created at line 156. Found 10-bit comparator less for signal <$n0200> created at line 156. Found 3-bit comparator greater for signal <$n0201> created at line 159. Found 10-bit comparator greater for signal <$n0202> created at line 159. Found 3-bit comparator less for signal <$n0203> created at line 162. Found 3-bit comparator equal for signal <$n0204> created at line 162. Found 10-bit comparator less for signal <$n0205> created at line 162. Found 3-bit comparator greater for signal <$n0206> created at line 165. Found 10-bit comparator greater for signal <$n0207> created at line 165. Found 3-bit comparator less for signal <$n0208> created at line 168. Found 3-bit comparator equal for signal <$n0209> created at line 168. Found 10-bit comparator less for signal <$n0210> created at line 168. Found 3-bit comparator less for signal <$n0211> created at line 150. Found 3-bit comparator equal for signal <$n0212> created at line 150. Found 10-bit comparator less for signal <$n0213> created at line 150. Found 3-bit comparator greater for signal <$n0214> created at line 153. Found 10-bit comparator greater for signal <$n0215> created at line 153. Found 3-bit comparator less for signal <$n0216> created at line 156. Found 3-bit comparator equal for signal <$n0217> created at line 156. Found 10-bit comparator less for signal <$n0218> created at line 156. Found 3-bit comparator greater for signal <$n0219> created at line 159. Found 10-bit comparator greater for signal <$n0220> created at line 159. Found 3-bit comparator less for signal <$n0221> created at line 162. Found 3-bit comparator equal for signal <$n0222> created at line 162. Found 10-bit comparator less for signal <$n0223> created at line 162. Found 3-bit comparator greater for signal <$n0224> created at line 165. Found 10-bit comparator greater for signal <$n0225> created at line 165. Found 3-bit comparator less for signal <$n0226> created at line 168. Found 3-bit comparator equal for signal <$n0227> created at line 168. Found 10-bit comparator less for signal <$n0228> created at line 168. Found 7-bit subtractor for signal . Found 3-bit adder for signal . Found 10-bit subtractor for signal . Found 10-bit adder for signal . Found 10-bit subtractor for signal . Found 10-bit adder for signal . Found 36 1-bit 2-to-1 multiplexers. Summary: inferred 20 Adder/Subtracter(s). inferred 111 Comparator(s). inferred 36 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_memory.vhd. Found 64x26-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 26-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 64x26-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 26-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 5-bit adder for signal <$n0039> created at line 147. Found 5-bit adder for signal <$n0040> created at line 148. Found 6-bit comparator not equal for signal <$n0048> created at line 186. Found 6-bit comparator equal for signal <$n0049> created at line 190. Found 1-bit register for signal . Found 6-bit register for signal . Found 6-bit register for signal . Found 6-bit register for signal . Found 6 1-bit 2-to-1 multiplexers. Summary: inferred 2 RAM(s). inferred 19 D-type flip-flop(s). inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). inferred 6 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd. Found 10-bit 4-to-1 multiplexer for signal <$n0043>. Found 3-bit 4-to-1 multiplexer for signal <$n0044>. Found 6-bit 4-to-1 multiplexer for signal <$n0045>. Found 10-bit 4-to-1 multiplexer for signal <$n0046>. Found 3-bit 4-to-1 multiplexer for signal <$n0047>. Found 6-bit 4-to-1 multiplexer for signal <$n0048>. Found 10-bit 4-to-1 multiplexer for signal <$n0049>. Found 3-bit 4-to-1 multiplexer for signal <$n0050>. Found 6-bit 4-to-1 multiplexer for signal <$n0051>. Found 10-bit 4-to-1 multiplexer for signal <$n0052>. Found 3-bit 4-to-1 multiplexer for signal <$n0053>. Found 6-bit 4-to-1 multiplexer for signal <$n0054>. Found 10-bit 4-to-1 multiplexer for signal <$n0055>. Found 3-bit 4-to-1 multiplexer for signal <$n0056>. Found 6-bit 4-to-1 multiplexer for signal <$n0057>. Found 10-bit 4-to-1 multiplexer for signal <$n0058>. Found 3-bit 4-to-1 multiplexer for signal <$n0059>. Found 6-bit 4-to-1 multiplexer for signal <$n0060>. Found 10-bit 4-to-1 multiplexer for signal <$n0061>. Found 3-bit 4-to-1 multiplexer for signal <$n0062>. Found 6-bit 4-to-1 multiplexer for signal <$n0063>. Found 10-bit 4-to-1 multiplexer for signal <$n0064>. Found 3-bit 4-to-1 multiplexer for signal <$n0065>. Found 6-bit 4-to-1 multiplexer for signal <$n0066>. Found 10-bit comparator lessequal for signal <$n0080> created at line 129. Found 3-bit comparator equal for signal <$n0081> created at line 129. Found 10-bit comparator lessequal for signal <$n0083> created at line 129. Found 3-bit comparator equal for signal <$n0084> created at line 129. Found 10-bit comparator lessequal for signal <$n0086> created at line 129. Found 3-bit comparator equal for signal <$n0087> created at line 129. Found 10-bit comparator lessequal for signal <$n0089> created at line 129. Found 3-bit comparator equal for signal <$n0090> created at line 129. Found 10-bit comparator lessequal for signal <$n0092> created at line 129. Found 3-bit comparator equal for signal <$n0093> created at line 129. Found 10-bit comparator lessequal for signal <$n0095> created at line 129. Found 3-bit comparator equal for signal <$n0096> created at line 129. Found 10-bit comparator lessequal for signal <$n0098> created at line 129. Found 3-bit comparator equal for signal <$n0099> created at line 129. Found 10-bit comparator lessequal for signal <$n0101> created at line 129. Found 3-bit comparator equal for signal <$n0102> created at line 129. Found 48-bit register for signal >. Found 24-bit register for signal >. Found 3-bit register for signal . Found 80-bit register for signal >. Summary: inferred 75 D-type flip-flop(s). inferred 16 Comparator(s). inferred 152 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 80x11-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 7x8-bit multiplier for signal

. Found 13-bit adder for signal . Found 11-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd. WARNING:Xst:647 - Input > is never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 8-bit subtractor for signal <$n0000> created at line 83. Found 9x9-bit multiplier for signal

. Found 8-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 80x11-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 7x8-bit multiplier for signal

. Found 13-bit adder for signal . Found 11-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd. WARNING:Xst:647 - Input > is never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 8-bit subtractor for signal <$n0000> created at line 83. Found 9x9-bit multiplier for signal

. Found 8-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 80x11-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 7x8-bit multiplier for signal

. Found 13-bit adder for signal . Found 11-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd. WARNING:Xst:647 - Input > is never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 8-bit subtractor for signal <$n0000> created at line 83. Found 9x9-bit multiplier for signal

. Found 8-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 80x11-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 7x8-bit multiplier for signal

. Found 13-bit adder for signal . Found 11-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd. WARNING:Xst:647 - Input > is never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 8-bit subtractor for signal <$n0000> created at line 83. Found 9x9-bit multiplier for signal

. Found 8-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 78x11-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 7x8-bit multiplier for signal

. Found 13-bit adder for signal . Found 11-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd. WARNING:Xst:647 - Input > is never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 8-bit subtractor for signal <$n0000> created at line 83. Found 9x9-bit multiplier for signal

. Found 8-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd. Found 77x11-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 7x8-bit multiplier for signal

. Found 13-bit adder for signal . Found 11-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd. WARNING:Xst:647 - Input > is never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 8-bit subtractor for signal <$n0000> created at line 83. Found 9x9-bit multiplier for signal

. Found 8-bit adder for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 1 Multiplier(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd. Found 4-bit comparator less for signal <$n0030> created at line 173. Found 1-bit register for signal >. Found 2-bit register for signal . Summary: inferred 3 D-type flip-flop(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/inputcontrol.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 9 | | Inputs | 3 | | Outputs | 2 | | Clock | clk_in (rising_edge) | | Reset | rst_n (negative) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 32-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 83 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/reconst.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal > and currently occupies 7 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal > and currently occupies 7 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. Found 7-bit shift register for signal <41>>. Found 7-bit shift register for signal <40>>. Found 7-bit shift register for signal <39>>. Found 7-bit shift register for signal <38>>. Found 7-bit shift register for signal <37>>. Found 7-bit shift register for signal <36>>. Found 7-bit shift register for signal <35>>. Found 7-bit shift register for signal <34>>. Found 7-bit shift register for signal <33>>. Found 7-bit shift register for signal <32>>. Found 7-bit shift register for signal <31>>. Found 7-bit shift register for signal <30>>. Found 7-bit shift register for signal <29>>. Found 7-bit shift register for signal <28>>. Found 7-bit shift register for signal <27>>. Found 7-bit shift register for signal <26>>. Found 7-bit shift register for signal <25>>. Found 7-bit shift register for signal <24>>. Found 7-bit shift register for signal <23>>. Found 7-bit shift register for signal <22>>. Found 7-bit shift register for signal <21>>. Found 7-bit shift register for signal <20>>. Found 7-bit shift register for signal <19>>. Found 7-bit shift register for signal <18>>. Found 7-bit shift register for signal <17>>. Found 7-bit shift register for signal <16>>. Found 7-bit shift register for signal <15>>. Found 7-bit shift register for signal <14>>. Found 7-bit shift register for signal <13>>. Found 7-bit shift register for signal <12>>. Found 7-bit shift register for signal <11>>. Found 7-bit shift register for signal <10>>. Found 7-bit shift register for signal <9>>. Found 7-bit shift register for signal <8>>. Found 7-bit shift register for signal <7>>. Found 7-bit shift register for signal <6>>. Found 7-bit shift register for signal <5>>. Found 7-bit shift register for signal <4>>. Found 7-bit shift register for signal <3>>. Found 7-bit shift register for signal <2>>. Found 7-bit shift register for signal <1>>. Found 7-bit shift register for signal <0>>. Found 12-bit adder for signal <$n0000> created at line 206. Found 18-bit adder for signal <$n0001> created at line 198. Found 17-bit subtractor for signal <$n0002> created at line 206. Found 18-bit adder for signal <$n0004>. Found 18-bit adder for signal <$n0005>. Found 18-bit adder for signal <$n0006>. Found 18-bit adder for signal <$n0007>. Found 18-bit adder for signal . Found 16-bit register for signal . Found 78-bit register for signal . Found 108-bit register for signal . Found 13-bit register for signal . Found 3-bit shift register for signal . Found 21-bit register for signal . Found 7-bit register for signal >. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 42-bit register for signal . Found 5-bit shift register for signal . Found 7-bit register for signal >. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 78-bit register for signal . Found 35 1-bit 2-to-1 multiplexers. Summary: inferred 382 D-type flip-flop(s). inferred 8 Adder/Subtracter(s). inferred 35 Multiplexer(s). inferred 89 Shift register(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/unique.vhd. Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd. Found 1-bit register for signal . Found 10 1-bit 2-to-1 multiplexers. Summary: inferred 1 D-type flip-flop(s). inferred 10 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd. Found 1-bit register for signal . Found 10 1-bit 2-to-1 multiplexers. Summary: inferred 1 D-type flip-flop(s). inferred 10 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd. Found 1-bit register for signal . Found 10 1-bit 2-to-1 multiplexers. Summary: inferred 1 D-type flip-flop(s). inferred 10 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd. Found 64x7-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 7-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 6-bit up counter for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd. Found 64x21-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 21-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to internal node | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 7-bit register for signal . Found 6-bit up counter for signal . Found 6-bit register for signal . Found 1-bit register for signal . Found 10-bit register for signal . Found 13-bit adder for signal . Found 4-bit register for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). inferred 28 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd. Found 64x21-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 21-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to internal node | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 7-bit register for signal . Found 6-bit up counter for signal . Found 6-bit register for signal . Found 1-bit register for signal . Found 10-bit register for signal . Found 13-bit adder for signal . Found 4-bit register for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). inferred 28 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd. Found 64x21-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 21-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to internal node | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 7-bit register for signal . Found 6-bit up counter for signal . Found 6-bit register for signal . Found 1-bit register for signal . Found 10-bit register for signal . Found 13-bit adder for signal . Found 4-bit register for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). inferred 28 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd. Found 64x21-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 21-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to internal node | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 7-bit register for signal . Found 6-bit up counter for signal . Found 6-bit register for signal . Found 1-bit register for signal . Found 10-bit register for signal . Found 13-bit adder for signal . Found 4-bit register for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). inferred 28 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd. Found 64x21-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 21-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to internal node | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 7-bit register for signal . Found 6-bit up counter for signal . Found 6-bit register for signal . Found 1-bit register for signal . Found 10-bit register for signal . Found 13-bit adder for signal . Found 4-bit register for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). inferred 28 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd. Found 64x21-bit dual-port distributed RAM for signal . ----------------------------------------------------------------------- | aspect ratio | 64-word x 21-bit | | | clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to internal node | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. Found 7-bit register for signal . Found 6-bit up counter for signal . Found 6-bit register for signal . Found 1-bit register for signal . Found 10-bit register for signal . Found 13-bit adder for signal . Found 4-bit register for signal . Summary: inferred 1 RAM(s). inferred 1 Counter(s). inferred 28 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). Unit synthesized. Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/toplevel.vhd. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Selecting encoding for FSM_0 ... Optimizing FSM on signal with one-hot encoding. Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # LUT RAMs : 146 64x21-bit dual-port distributed RAM: 6 64x7-bit dual-port distributed RAM: 18 64x26-bit dual-port distributed RAM: 108 8x52-bit dual-port distributed RAM: 12 16x52-bit dual-port distributed RAM: 2 # ROMs : 13 77x11-bit ROM : 1 78x11-bit ROM : 1 80x11-bit ROM : 4 22x13-bit ROM : 7 # Multipliers : 15 9x9-bit multiplier : 6 7x8-bit multiplier : 6 4x3-bit multiplier : 3 # Adders/Subtractors : 405 17-bit subtractor : 1 18-bit adder : 6 12-bit adder : 1 8-bit subtractor : 6 8-bit adder : 6 11-bit adder : 6 13-bit adder : 12 6-bit adder : 13 7-bit subtractor : 9 10-bit subtractor : 18 10-bit adder : 18 33-bit adder : 10 32-bit adder : 30 19-bit adder : 6 1-bit adder carry out : 10 5-bit adder : 109 3-bit adder : 127 4-bit subtractor : 3 4-bit adder : 4 2-bit adder : 10 # Counters : 52 6-bit up counter : 24 3-bit up counter : 24 4-bit up counter : 4 # Registers : 955 6-bit register : 312 4-bit register : 8 7-bit register : 6 10-bit register : 150 1-bit register : 201 21-bit register : 1 16-bit register : 25 18-bit register : 6 13-bit register : 13 32-bit register : 12 8-bit register : 24 2-bit register : 6 3-bit register : 174 42-bit register : 11 19-bit register : 6 # Shift Registers : 89 3-bit shift register : 5 5-bit shift register : 42 7-bit shift register : 42 # Comparators : 1489 10-bit comparator lessequal : 144 6-bit comparator not equal : 54 10-bit comparator greater : 135 3-bit comparator greater : 135 10-bit comparator less : 180 3-bit comparator greatequal : 9 7-bit comparator greater : 90 4-bit comparator equal : 3 4-bit comparator less : 9 3-bit comparator not equal : 12 7-bit comparator less : 103 3-bit comparator equal : 334 3-bit comparator less : 190 4-bit comparator not equal : 2 6-bit comparator equal : 84 32-bit comparator greatequal : 5 # Multiplexers : 665 7-bit 2-to-1 multiplexer : 9 3-bit 2-to-1 multiplexer : 117 17-bit 2-to-1 multiplexer : 1 18-bit 2-to-1 multiplexer : 1 6-bit 4-to-1 multiplexer : 144 3-bit 4-to-1 multiplexer : 144 10-bit 4-to-1 multiplexer : 144 6-bit 2-to-1 multiplexer : 54 33-bit 2-to-1 multiplexer : 20 32-bit 2-to-1 multiplexer : 30 42-bit 2-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Launcher: "cg_fifo_dc.ngo" is up to date. Launcher: "cg_divide.ngo" is up to date. Loading core for timing and area information for instance . Loading core for timing and area information for instance . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1710 - FF/Latch (without init value) is constant in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) is constant in block . Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/xilinx6.2i. Mapping all equations... WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Building and optimizing final netlist ... WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . Register match_inst22_matching_memory15_reg_last_5 equivalent to match_inst23_matching_memory15_reg_last_5 has been removed Register match_inst21_matching_memory15_reg_last_5 equivalent to match_inst23_matching_memory15_reg_last_5 has been removed Register match_inst22_matching_memory15_reg_last_4 equivalent to match_inst23_matching_memory15_reg_last_4 has been removed Register match_inst21_matching_memory15_reg_last_4 equivalent to match_inst23_matching_memory15_reg_last_4 has been removed Register match_inst22_matching_memory15_reg_last_3 equivalent to match_inst23_matching_memory15_reg_last_3 has been removed Register match_inst21_matching_memory15_reg_last_3 equivalent to match_inst23_matching_memory15_reg_last_3 has been removed Register match_inst22_matching_memory15_reg_last_0 equivalent to match_inst23_matching_memory15_reg_last_0 has been removed Register match_inst21_matching_memory15_reg_last_0 equivalent to match_inst23_matching_memory15_reg_last_0 has been removed Register match_inst22_matching_memory15_reg_last_1 equivalent to match_inst23_matching_memory15_reg_last_1 has been removed Register match_inst21_matching_memory15_reg_last_1 equivalent to match_inst23_matching_memory15_reg_last_1 has been removed Register match_inst22_matching_memory15_reg_last_2 equivalent to match_inst23_matching_memory15_reg_last_2 has been removed Register match_inst21_matching_memory15_reg_last_2 equivalent to match_inst23_matching_memory15_reg_last_2 has been removed Register match_inst22_matching_memory14_reg_last_5 equivalent to match_inst23_matching_memory14_reg_last_5 has been removed Register match_inst21_matching_memory14_reg_last_5 equivalent to match_inst23_matching_memory14_reg_last_5 has been removed Register match_inst22_matching_memory14_reg_last_4 equivalent to match_inst23_matching_memory14_reg_last_4 has been removed Register match_inst21_matching_memory14_reg_last_4 equivalent to match_inst23_matching_memory14_reg_last_4 has been removed Register match_inst22_matching_memory14_reg_last_3 equivalent to match_inst23_matching_memory14_reg_last_3 has been removed Register match_inst21_matching_memory14_reg_last_3 equivalent to match_inst23_matching_memory14_reg_last_3 has been removed Register match_inst22_matching_memory14_reg_last_0 equivalent to match_inst23_matching_memory14_reg_last_0 has been removed Register match_inst21_matching_memory14_reg_last_0 equivalent to match_inst23_matching_memory14_reg_last_0 has been removed Register match_inst22_matching_memory14_reg_last_1 equivalent to match_inst23_matching_memory14_reg_last_1 has been removed Register match_inst21_matching_memory14_reg_last_1 equivalent to match_inst23_matching_memory14_reg_last_1 has been removed Register match_inst22_matching_memory14_reg_last_2 equivalent to match_inst23_matching_memory14_reg_last_2 has been removed Register match_inst21_matching_memory14_reg_last_2 equivalent to match_inst23_matching_memory14_reg_last_2 has been removed Register match_inst22_matching_memory13_reg_last_5 equivalent to match_inst23_matching_memory13_reg_last_5 has been removed Register match_inst21_matching_memory13_reg_last_5 equivalent to match_inst23_matching_memory13_reg_last_5 has been removed Register match_inst22_matching_memory13_reg_last_4 equivalent to match_inst23_matching_memory13_reg_last_4 has been removed Register match_inst21_matching_memory13_reg_last_4 equivalent to match_inst23_matching_memory13_reg_last_4 has been removed Register match_inst22_matching_memory13_reg_last_3 equivalent to match_inst23_matching_memory13_reg_last_3 has been removed Register match_inst21_matching_memory13_reg_last_3 equivalent to match_inst23_matching_memory13_reg_last_3 has been removed Register match_inst22_matching_memory13_reg_last_0 equivalent to match_inst23_matching_memory13_reg_last_0 has been removed Register match_inst21_matching_memory13_reg_last_0 equivalent to match_inst23_matching_memory13_reg_last_0 has been removed Register match_inst22_matching_memory13_reg_last_1 equivalent to match_inst23_matching_memory13_reg_last_1 has been removed Register match_inst21_matching_memory13_reg_last_1 equivalent to match_inst23_matching_memory13_reg_last_1 has been removed Register match_inst22_matching_memory13_reg_last_2 equivalent to match_inst23_matching_memory13_reg_last_2 has been removed Register match_inst21_matching_memory13_reg_last_2 equivalent to match_inst23_matching_memory13_reg_last_2 has been removed Register match_inst22_matching_memory12_reg_last_5 equivalent to match_inst23_matching_memory12_reg_last_5 has been removed Register match_inst21_matching_memory12_reg_last_5 equivalent to match_inst23_matching_memory12_reg_last_5 has been removed Register match_inst22_matching_memory12_reg_last_4 equivalent to match_inst23_matching_memory12_reg_last_4 has been removed Register match_inst21_matching_memory12_reg_last_4 equivalent to match_inst23_matching_memory12_reg_last_4 has been removed Register match_inst22_matching_memory12_reg_last_3 equivalent to match_inst23_matching_memory12_reg_last_3 has been removed Register match_inst21_matching_memory12_reg_last_3 equivalent to match_inst23_matching_memory12_reg_last_3 has been removed Register match_inst22_matching_memory12_reg_last_0 equivalent to match_inst23_matching_memory12_reg_last_0 has been removed Register match_inst21_matching_memory12_reg_last_0 equivalent to match_inst23_matching_memory12_reg_last_0 has been removed Register match_inst22_matching_memory12_reg_last_1 equivalent to match_inst23_matching_memory12_reg_last_1 has been removed Register match_inst21_matching_memory12_reg_last_1 equivalent to match_inst23_matching_memory12_reg_last_1 has been removed Register match_inst22_matching_memory12_reg_last_2 equivalent to match_inst23_matching_memory12_reg_last_2 has been removed Register match_inst21_matching_memory12_reg_last_2 equivalent to match_inst23_matching_memory12_reg_last_2 has been removed Register match_inst22_matching_memory11_reg_last_5 equivalent to match_inst23_matching_memory11_reg_last_5 has been removed Register match_inst21_matching_memory11_reg_last_5 equivalent to match_inst23_matching_memory11_reg_last_5 has been removed Register match_inst22_matching_memory11_reg_last_4 equivalent to match_inst23_matching_memory11_reg_last_4 has been removed Register match_inst21_matching_memory11_reg_last_4 equivalent to match_inst23_matching_memory11_reg_last_4 has been removed Register match_inst22_matching_memory11_reg_last_3 equivalent to match_inst23_matching_memory11_reg_last_3 has been removed Register match_inst21_matching_memory11_reg_last_3 equivalent to match_inst23_matching_memory11_reg_last_3 has been removed Register match_inst22_matching_memory11_reg_last_0 equivalent to match_inst23_matching_memory11_reg_last_0 has been removed Register match_inst21_matching_memory11_reg_last_0 equivalent to match_inst23_matching_memory11_reg_last_0 has been removed Register match_inst22_matching_memory11_reg_last_1 equivalent to match_inst23_matching_memory11_reg_last_1 has been removed Register match_inst21_matching_memory11_reg_last_1 equivalent to match_inst23_matching_memory11_reg_last_1 has been removed Register match_inst22_matching_memory11_reg_last_2 equivalent to match_inst23_matching_memory11_reg_last_2 has been removed Register match_inst21_matching_memory11_reg_last_2 equivalent to match_inst23_matching_memory11_reg_last_2 has been removed Register match_inst22_matching_memory10_reg_last_5 equivalent to match_inst23_matching_memory10_reg_last_5 has been removed Register match_inst21_matching_memory10_reg_last_5 equivalent to match_inst23_matching_memory10_reg_last_5 has been removed Register match_inst22_matching_memory10_reg_last_4 equivalent to match_inst23_matching_memory10_reg_last_4 has been removed Register match_inst21_matching_memory10_reg_last_4 equivalent to match_inst23_matching_memory10_reg_last_4 has been removed Register match_inst22_matching_memory10_reg_last_3 equivalent to match_inst23_matching_memory10_reg_last_3 has been removed Register match_inst21_matching_memory10_reg_last_3 equivalent to match_inst23_matching_memory10_reg_last_3 has been removed Register match_inst22_matching_memory10_reg_last_0 equivalent to match_inst23_matching_memory10_reg_last_0 has been removed Register match_inst21_matching_memory10_reg_last_0 equivalent to match_inst23_matching_memory10_reg_last_0 has been removed Register match_inst22_matching_memory10_reg_last_1 equivalent to match_inst23_matching_memory10_reg_last_1 has been removed Register match_inst21_matching_memory10_reg_last_1 equivalent to match_inst23_matching_memory10_reg_last_1 has been removed Register match_inst22_matching_memory10_reg_last_2 equivalent to match_inst23_matching_memory10_reg_last_2 has been removed Register match_inst21_matching_memory10_reg_last_2 equivalent to match_inst23_matching_memory10_reg_last_2 has been removed Register match_inst12_matching_memory15_reg_last_5 equivalent to match_inst13_matching_memory15_reg_last_5 has been removed Register match_inst11_matching_memory15_reg_last_5 equivalent to match_inst13_matching_memory15_reg_last_5 has been removed Register match_inst12_matching_memory15_reg_last_4 equivalent to match_inst13_matching_memory15_reg_last_4 has been removed Register match_inst11_matching_memory15_reg_last_4 equivalent to match_inst13_matching_memory15_reg_last_4 has been removed Register match_inst12_matching_memory15_reg_last_3 equivalent to match_inst13_matching_memory15_reg_last_3 has been removed Register match_inst11_matching_memory15_reg_last_3 equivalent to match_inst13_matching_memory15_reg_last_3 has been removed Register match_inst12_matching_memory15_reg_last_0 equivalent to match_inst13_matching_memory15_reg_last_0 has been removed Register match_inst11_matching_memory15_reg_last_0 equivalent to match_inst13_matching_memory15_reg_last_0 has been removed Register match_inst12_matching_memory15_reg_last_1 equivalent to match_inst13_matching_memory15_reg_last_1 has been removed Register match_inst11_matching_memory15_reg_last_1 equivalent to match_inst13_matching_memory15_reg_last_1 has been removed Register match_inst12_matching_memory15_reg_last_2 equivalent to match_inst13_matching_memory15_reg_last_2 has been removed Register match_inst11_matching_memory15_reg_last_2 equivalent to match_inst13_matching_memory15_reg_last_2 has been removed Register match_inst12_matching_memory14_reg_last_5 equivalent to match_inst13_matching_memory14_reg_last_5 has been removed Register match_inst11_matching_memory14_reg_last_5 equivalent to match_inst13_matching_memory14_reg_last_5 has been removed Register match_inst12_matching_memory14_reg_last_4 equivalent to match_inst13_matching_memory14_reg_last_4 has been removed Register match_inst11_matching_memory14_reg_last_4 equivalent to match_inst13_matching_memory14_reg_last_4 has been removed Register match_inst12_matching_memory14_reg_last_3 equivalent to match_inst13_matching_memory14_reg_last_3 has been removed Register match_inst11_matching_memory14_reg_last_3 equivalent to match_inst13_matching_memory14_reg_last_3 has been removed Register match_inst12_matching_memory14_reg_last_0 equivalent to match_inst13_matching_memory14_reg_last_0 has been removed Register match_inst11_matching_memory14_reg_last_0 equivalent to match_inst13_matching_memory14_reg_last_0 has been removed Register match_inst12_matching_memory14_reg_last_1 equivalent to match_inst13_matching_memory14_reg_last_1 has been removed Register match_inst11_matching_memory14_reg_last_1 equivalent to match_inst13_matching_memory14_reg_last_1 has been removed Register match_inst12_matching_memory14_reg_last_2 equivalent to match_inst13_matching_memory14_reg_last_2 has been removed Register match_inst11_matching_memory14_reg_last_2 equivalent to match_inst13_matching_memory14_reg_last_2 has been removed Register match_inst12_matching_memory13_reg_last_5 equivalent to match_inst13_matching_memory13_reg_last_5 has been removed Register match_inst11_matching_memory13_reg_last_5 equivalent to match_inst13_matching_memory13_reg_last_5 has been removed Register match_inst12_matching_memory13_reg_last_4 equivalent to match_inst13_matching_memory13_reg_last_4 has been removed Register match_inst11_matching_memory13_reg_last_4 equivalent to match_inst13_matching_memory13_reg_last_4 has been removed Register match_inst12_matching_memory13_reg_last_3 equivalent to match_inst13_matching_memory13_reg_last_3 has been removed Register match_inst11_matching_memory13_reg_last_3 equivalent to match_inst13_matching_memory13_reg_last_3 has been removed Register match_inst12_matching_memory13_reg_last_0 equivalent to match_inst13_matching_memory13_reg_last_0 has been removed Register match_inst11_matching_memory13_reg_last_0 equivalent to match_inst13_matching_memory13_reg_last_0 has been removed Register match_inst12_matching_memory13_reg_last_1 equivalent to match_inst13_matching_memory13_reg_last_1 has been removed Register match_inst11_matching_memory13_reg_last_1 equivalent to match_inst13_matching_memory13_reg_last_1 has been removed Register match_inst12_matching_memory13_reg_last_2 equivalent to match_inst13_matching_memory13_reg_last_2 has been removed Register match_inst11_matching_memory13_reg_last_2 equivalent to match_inst13_matching_memory13_reg_last_2 has been removed Register match_inst12_matching_memory12_reg_last_5 equivalent to match_inst13_matching_memory12_reg_last_5 has been removed Register match_inst11_matching_memory12_reg_last_5 equivalent to match_inst13_matching_memory12_reg_last_5 has been removed Register match_inst12_matching_memory12_reg_last_4 equivalent to match_inst13_matching_memory12_reg_last_4 has been removed Register match_inst11_matching_memory12_reg_last_4 equivalent to match_inst13_matching_memory12_reg_last_4 has been removed Register match_inst12_matching_memory12_reg_last_3 equivalent to match_inst13_matching_memory12_reg_last_3 has been removed Register match_inst11_matching_memory12_reg_last_3 equivalent to match_inst13_matching_memory12_reg_last_3 has been removed Register match_inst12_matching_memory12_reg_last_0 equivalent to match_inst13_matching_memory12_reg_last_0 has been removed Register match_inst11_matching_memory12_reg_last_0 equivalent to match_inst13_matching_memory12_reg_last_0 has been removed Register match_inst12_matching_memory12_reg_last_1 equivalent to match_inst13_matching_memory12_reg_last_1 has been removed Register match_inst11_matching_memory12_reg_last_1 equivalent to match_inst13_matching_memory12_reg_last_1 has been removed Register match_inst12_matching_memory12_reg_last_2 equivalent to match_inst13_matching_memory12_reg_last_2 has been removed Register match_inst11_matching_memory12_reg_last_2 equivalent to match_inst13_matching_memory12_reg_last_2 has been removed Register match_inst12_matching_memory11_reg_last_5 equivalent to match_inst13_matching_memory11_reg_last_5 has been removed Register match_inst11_matching_memory11_reg_last_5 equivalent to match_inst13_matching_memory11_reg_last_5 has been removed Register match_inst12_matching_memory11_reg_last_4 equivalent to match_inst13_matching_memory11_reg_last_4 has been removed Register match_inst11_matching_memory11_reg_last_4 equivalent to match_inst13_matching_memory11_reg_last_4 has been removed Register match_inst12_matching_memory11_reg_last_3 equivalent to match_inst13_matching_memory11_reg_last_3 has been removed Register match_inst11_matching_memory11_reg_last_3 equivalent to match_inst13_matching_memory11_reg_last_3 has been removed Register match_inst12_matching_memory11_reg_last_0 equivalent to match_inst13_matching_memory11_reg_last_0 has been removed Register match_inst11_matching_memory11_reg_last_0 equivalent to match_inst13_matching_memory11_reg_last_0 has been removed Register match_inst12_matching_memory11_reg_last_1 equivalent to match_inst13_matching_memory11_reg_last_1 has been removed Register match_inst11_matching_memory11_reg_last_1 equivalent to match_inst13_matching_memory11_reg_last_1 has been removed Register match_inst12_matching_memory11_reg_last_2 equivalent to match_inst13_matching_memory11_reg_last_2 has been removed Register match_inst11_matching_memory11_reg_last_2 equivalent to match_inst13_matching_memory11_reg_last_2 has been removed Register match_inst12_matching_memory10_reg_last_5 equivalent to match_inst13_matching_memory10_reg_last_5 has been removed Register match_inst11_matching_memory10_reg_last_5 equivalent to match_inst13_matching_memory10_reg_last_5 has been removed Register match_inst12_matching_memory10_reg_last_4 equivalent to match_inst13_matching_memory10_reg_last_4 has been removed Register match_inst11_matching_memory10_reg_last_4 equivalent to match_inst13_matching_memory10_reg_last_4 has been removed Register match_inst12_matching_memory10_reg_last_3 equivalent to match_inst13_matching_memory10_reg_last_3 has been removed Register match_inst11_matching_memory10_reg_last_3 equivalent to match_inst13_matching_memory10_reg_last_3 has been removed Register match_inst12_matching_memory10_reg_last_0 equivalent to match_inst13_matching_memory10_reg_last_0 has been removed Register match_inst11_matching_memory10_reg_last_0 equivalent to match_inst13_matching_memory10_reg_last_0 has been removed Register match_inst12_matching_memory10_reg_last_1 equivalent to match_inst13_matching_memory10_reg_last_1 has been removed Register match_inst11_matching_memory10_reg_last_1 equivalent to match_inst13_matching_memory10_reg_last_1 has been removed Register match_inst12_matching_memory10_reg_last_2 equivalent to match_inst13_matching_memory10_reg_last_2 has been removed Register match_inst11_matching_memory10_reg_last_2 equivalent to match_inst13_matching_memory10_reg_last_2 has been removed Register match_inst02_matching_memory15_reg_last_5 equivalent to match_inst03_matching_memory15_reg_last_5 has been removed Register match_inst01_matching_memory15_reg_last_5 equivalent to match_inst03_matching_memory15_reg_last_5 has been removed Register match_inst02_matching_memory15_reg_last_4 equivalent to match_inst03_matching_memory15_reg_last_4 has been removed Register match_inst01_matching_memory15_reg_last_4 equivalent to match_inst03_matching_memory15_reg_last_4 has been removed Register match_inst02_matching_memory15_reg_last_3 equivalent to match_inst03_matching_memory15_reg_last_3 has been removed Register match_inst01_matching_memory15_reg_last_3 equivalent to match_inst03_matching_memory15_reg_last_3 has been removed Register match_inst02_matching_memory15_reg_last_0 equivalent to match_inst03_matching_memory15_reg_last_0 has been removed Register match_inst01_matching_memory15_reg_last_0 equivalent to match_inst03_matching_memory15_reg_last_0 has been removed Register match_inst02_matching_memory15_reg_last_1 equivalent to match_inst03_matching_memory15_reg_last_1 has been removed Register match_inst01_matching_memory15_reg_last_1 equivalent to match_inst03_matching_memory15_reg_last_1 has been removed Register match_inst02_matching_memory15_reg_last_2 equivalent to match_inst03_matching_memory15_reg_last_2 has been removed Register match_inst01_matching_memory15_reg_last_2 equivalent to match_inst03_matching_memory15_reg_last_2 has been removed Register match_inst02_matching_memory14_reg_last_5 equivalent to match_inst03_matching_memory14_reg_last_5 has been removed Register match_inst01_matching_memory14_reg_last_5 equivalent to match_inst03_matching_memory14_reg_last_5 has been removed Register match_inst02_matching_memory14_reg_last_4 equivalent to match_inst03_matching_memory14_reg_last_4 has been removed Register match_inst01_matching_memory14_reg_last_4 equivalent to match_inst03_matching_memory14_reg_last_4 has been removed Register match_inst02_matching_memory14_reg_last_3 equivalent to match_inst03_matching_memory14_reg_last_3 has been removed Register match_inst01_matching_memory14_reg_last_3 equivalent to match_inst03_matching_memory14_reg_last_3 has been removed Register match_inst02_matching_memory14_reg_last_0 equivalent to match_inst03_matching_memory14_reg_last_0 has been removed Register match_inst01_matching_memory14_reg_last_0 equivalent to match_inst03_matching_memory14_reg_last_0 has been removed Register match_inst02_matching_memory14_reg_last_1 equivalent to match_inst03_matching_memory14_reg_last_1 has been removed Register match_inst01_matching_memory14_reg_last_1 equivalent to match_inst03_matching_memory14_reg_last_1 has been removed Register match_inst02_matching_memory14_reg_last_2 equivalent to match_inst03_matching_memory14_reg_last_2 has been removed Register match_inst01_matching_memory14_reg_last_2 equivalent to match_inst03_matching_memory14_reg_last_2 has been removed Register match_inst02_matching_memory13_reg_last_5 equivalent to match_inst03_matching_memory13_reg_last_5 has been removed Register match_inst01_matching_memory13_reg_last_5 equivalent to match_inst03_matching_memory13_reg_last_5 has been removed Register match_inst02_matching_memory13_reg_last_4 equivalent to match_inst03_matching_memory13_reg_last_4 has been removed Register match_inst01_matching_memory13_reg_last_4 equivalent to match_inst03_matching_memory13_reg_last_4 has been removed Register match_inst02_matching_memory13_reg_last_3 equivalent to match_inst03_matching_memory13_reg_last_3 has been removed Register match_inst01_matching_memory13_reg_last_3 equivalent to match_inst03_matching_memory13_reg_last_3 has been removed Register match_inst02_matching_memory13_reg_last_0 equivalent to match_inst03_matching_memory13_reg_last_0 has been removed Register match_inst01_matching_memory13_reg_last_0 equivalent to match_inst03_matching_memory13_reg_last_0 has been removed Register match_inst02_matching_memory13_reg_last_1 equivalent to match_inst03_matching_memory13_reg_last_1 has been removed Register match_inst01_matching_memory13_reg_last_1 equivalent to match_inst03_matching_memory13_reg_last_1 has been removed Register match_inst02_matching_memory13_reg_last_2 equivalent to match_inst03_matching_memory13_reg_last_2 has been removed Register match_inst01_matching_memory13_reg_last_2 equivalent to match_inst03_matching_memory13_reg_last_2 has been removed Register match_inst02_matching_memory12_reg_last_5 equivalent to match_inst03_matching_memory12_reg_last_5 has been removed Register match_inst01_matching_memory12_reg_last_5 equivalent to match_inst03_matching_memory12_reg_last_5 has been removed Register match_inst02_matching_memory12_reg_last_4 equivalent to match_inst03_matching_memory12_reg_last_4 has been removed Register match_inst01_matching_memory12_reg_last_4 equivalent to match_inst03_matching_memory12_reg_last_4 has been removed Register match_inst02_matching_memory12_reg_last_3 equivalent to match_inst03_matching_memory12_reg_last_3 has been removed Register match_inst01_matching_memory12_reg_last_3 equivalent to match_inst03_matching_memory12_reg_last_3 has been removed Register match_inst02_matching_memory12_reg_last_0 equivalent to match_inst03_matching_memory12_reg_last_0 has been removed Register match_inst01_matching_memory12_reg_last_0 equivalent to match_inst03_matching_memory12_reg_last_0 has been removed Register match_inst02_matching_memory12_reg_last_1 equivalent to match_inst03_matching_memory12_reg_last_1 has been removed Register match_inst01_matching_memory12_reg_last_1 equivalent to match_inst03_matching_memory12_reg_last_1 has been removed Register match_inst02_matching_memory12_reg_last_2 equivalent to match_inst03_matching_memory12_reg_last_2 has been removed Register match_inst01_matching_memory12_reg_last_2 equivalent to match_inst03_matching_memory12_reg_last_2 has been removed Register match_inst02_matching_memory11_reg_last_5 equivalent to match_inst03_matching_memory11_reg_last_5 has been removed Register match_inst01_matching_memory11_reg_last_5 equivalent to match_inst03_matching_memory11_reg_last_5 has been removed Register match_inst02_matching_memory11_reg_last_4 equivalent to match_inst03_matching_memory11_reg_last_4 has been removed Register match_inst01_matching_memory11_reg_last_4 equivalent to match_inst03_matching_memory11_reg_last_4 has been removed Register match_inst02_matching_memory11_reg_last_3 equivalent to match_inst03_matching_memory11_reg_last_3 has been removed Register match_inst01_matching_memory11_reg_last_3 equivalent to match_inst03_matching_memory11_reg_last_3 has been removed Register match_inst02_matching_memory11_reg_last_0 equivalent to match_inst03_matching_memory11_reg_last_0 has been removed Register match_inst01_matching_memory11_reg_last_0 equivalent to match_inst03_matching_memory11_reg_last_0 has been removed Register match_inst02_matching_memory11_reg_last_1 equivalent to match_inst03_matching_memory11_reg_last_1 has been removed Register match_inst01_matching_memory11_reg_last_1 equivalent to match_inst03_matching_memory11_reg_last_1 has been removed Register match_inst02_matching_memory11_reg_last_2 equivalent to match_inst03_matching_memory11_reg_last_2 has been removed Register match_inst01_matching_memory11_reg_last_2 equivalent to match_inst03_matching_memory11_reg_last_2 has been removed Register match_inst02_matching_memory10_reg_last_5 equivalent to match_inst03_matching_memory10_reg_last_5 has been removed Register match_inst01_matching_memory10_reg_last_5 equivalent to match_inst03_matching_memory10_reg_last_5 has been removed Register match_inst02_matching_memory10_reg_last_4 equivalent to match_inst03_matching_memory10_reg_last_4 has been removed Register match_inst01_matching_memory10_reg_last_4 equivalent to match_inst03_matching_memory10_reg_last_4 has been removed Register match_inst02_matching_memory10_reg_last_3 equivalent to match_inst03_matching_memory10_reg_last_3 has been removed Register match_inst01_matching_memory10_reg_last_3 equivalent to match_inst03_matching_memory10_reg_last_3 has been removed Register match_inst02_matching_memory10_reg_last_0 equivalent to match_inst03_matching_memory10_reg_last_0 has been removed Register match_inst01_matching_memory10_reg_last_0 equivalent to match_inst03_matching_memory10_reg_last_0 has been removed Register match_inst02_matching_memory10_reg_last_1 equivalent to match_inst03_matching_memory10_reg_last_1 has been removed Register match_inst01_matching_memory10_reg_last_1 equivalent to match_inst03_matching_memory10_reg_last_1 has been removed Register match_inst02_matching_memory10_reg_last_2 equivalent to match_inst03_matching_memory10_reg_last_2 has been removed Register match_inst01_matching_memory10_reg_last_2 equivalent to match_inst03_matching_memory10_reg_last_2 has been removed Found area constraint ratio of 100 (+ 5) on block toplevel, actual ratio is 145. Optimizing block to meet ratio 100 (+ 5) of 19392 slices : WARNING:Xst - Area constraint could not be met for block , final ratio is 142. WARNING:Xst:382 - Register BU1253 is equivalent to BU1217 Register match_inst21_matching_memory15_invalid_reg equivalent to match_inst22_matching_memory15_invalid_reg has been removed Register match_inst21_matching_memory14_invalid_reg equivalent to match_inst22_matching_memory14_invalid_reg has been removed Register match_inst21_matching_memory13_invalid_reg equivalent to match_inst22_matching_memory13_invalid_reg has been removed Register match_inst21_matching_memory12_invalid_reg equivalent to match_inst22_matching_memory12_invalid_reg has been removed Register match_inst21_matching_memory11_invalid_reg equivalent to match_inst22_matching_memory11_invalid_reg has been removed Register match_inst21_matching_memory10_invalid_reg equivalent to match_inst22_matching_memory10_invalid_reg has been removed Register match_inst11_matching_memory15_invalid_reg equivalent to match_inst12_matching_memory15_invalid_reg has been removed Register match_inst11_matching_memory14_invalid_reg equivalent to match_inst12_matching_memory14_invalid_reg has been removed Register match_inst11_matching_memory13_invalid_reg equivalent to match_inst12_matching_memory13_invalid_reg has been removed Register match_inst11_matching_memory12_invalid_reg equivalent to match_inst12_matching_memory12_invalid_reg has been removed Register match_inst11_matching_memory11_invalid_reg equivalent to match_inst12_matching_memory11_invalid_reg has been removed Register match_inst11_matching_memory10_invalid_reg equivalent to match_inst12_matching_memory10_invalid_reg has been removed Register match_inst01_matching_memory15_invalid_reg equivalent to match_inst02_matching_memory15_invalid_reg has been removed Register match_inst01_matching_memory14_invalid_reg equivalent to match_inst02_matching_memory14_invalid_reg has been removed Register match_inst01_matching_memory13_invalid_reg equivalent to match_inst02_matching_memory13_invalid_reg has been removed Register match_inst01_matching_memory12_invalid_reg equivalent to match_inst02_matching_memory12_invalid_reg has been removed Register match_inst01_matching_memory11_invalid_reg equivalent to match_inst02_matching_memory11_invalid_reg has been removed Register match_inst01_matching_memory10_invalid_reg equivalent to match_inst02_matching_memory10_invalid_reg has been removed WARNING:Xst:382 - Register BU1253 is equivalent to BU1217 Register match_inst22_matching_memory15_invalid_reg equivalent to match_inst23_matching_memory15_invalid_reg has been removed Register match_inst22_matching_memory14_invalid_reg equivalent to match_inst23_matching_memory14_invalid_reg has been removed Register match_inst22_matching_memory13_invalid_reg equivalent to match_inst23_matching_memory13_invalid_reg has been removed Register match_inst22_matching_memory12_invalid_reg equivalent to match_inst23_matching_memory12_invalid_reg has been removed Register match_inst22_matching_memory11_invalid_reg equivalent to match_inst23_matching_memory11_invalid_reg has been removed Register match_inst22_matching_memory10_invalid_reg equivalent to match_inst23_matching_memory10_invalid_reg has been removed Register match_inst12_matching_memory15_invalid_reg equivalent to match_inst13_matching_memory15_invalid_reg has been removed Register match_inst12_matching_memory14_invalid_reg equivalent to match_inst13_matching_memory14_invalid_reg has been removed Register match_inst12_matching_memory13_invalid_reg equivalent to match_inst13_matching_memory13_invalid_reg has been removed Register match_inst12_matching_memory12_invalid_reg equivalent to match_inst13_matching_memory12_invalid_reg has been removed Register match_inst12_matching_memory11_invalid_reg equivalent to match_inst13_matching_memory11_invalid_reg has been removed Register match_inst12_matching_memory10_invalid_reg equivalent to match_inst13_matching_memory10_invalid_reg has been removed Register match_inst02_matching_memory15_invalid_reg equivalent to match_inst03_matching_memory15_invalid_reg has been removed Register match_inst02_matching_memory14_invalid_reg equivalent to match_inst03_matching_memory14_invalid_reg has been removed Register match_inst02_matching_memory13_invalid_reg equivalent to match_inst03_matching_memory13_invalid_reg has been removed Register match_inst02_matching_memory12_invalid_reg equivalent to match_inst03_matching_memory12_invalid_reg has been removed Register match_inst02_matching_memory11_invalid_reg equivalent to match_inst03_matching_memory11_invalid_reg has been removed Register match_inst02_matching_memory10_invalid_reg equivalent to match_inst03_matching_memory10_invalid_reg has been removed WARNING:Xst:382 - Register BU1253 is equivalent to BU1217 FlipFlop match_inst21_matching_memory11_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory11_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory11_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory11_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory11_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory11_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory11_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory11_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory11_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory11_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory11_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory11_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop unique_inst_zch_merger_i_rd_addr_reg_0_0 has been replicated 1 time(s) FlipFlop unique_inst_zch_merger_i_rd_addr_reg_1_0 has been replicated 1 time(s) FlipFlop unique_inst_zch_merger_i_rd_addr_reg_0_1 has been replicated 1 time(s) FlipFlop unique_inst_zch_merger_i_rd_addr_reg_1_1 has been replicated 1 time(s) FlipFlop unique_inst_zch_merger_i_rd_addr_reg_0_2 has been replicated 1 time(s) FlipFlop unique_inst_zch_merger_i_rd_addr_reg_1_2 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory13_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory13_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory13_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory15_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory14_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory15_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory14_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory15_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory14_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory10_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory12_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory10_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory10_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory12_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory12_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst23_matching_memory15_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory14_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory15_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory14_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory15_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory14_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory12_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory11_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory12_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory11_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory12_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory11_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory13_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst13_matching_memory13_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst03_matching_memory13_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory12_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory12_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory12_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory13_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory13_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory13_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory15_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory14_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory15_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory14_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory15_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory14_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory10_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory12_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory13_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory13_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory13_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory15_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory15_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory15_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory14_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory14_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory14_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory10_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory10_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory10_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory11_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory11_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory11_reg_a_1 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory10_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory10_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory12_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory12_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst23_matching_memory15_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory14_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory15_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory14_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory15_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory14_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory12_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory11_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory12_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory11_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory12_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory11_reg_b_2 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory13_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory13_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory15_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory14_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory15_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory14_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory15_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory14_reg_b_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory15_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory13_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory15_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory13_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory14_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory14_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory13_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory15_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory14_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory10_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory10_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory10_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory12_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory14_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory14_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory14_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory15_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory15_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory15_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory12_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory12_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory12_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory10_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory10_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory10_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory11_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory11_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory11_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory12_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory12_reg_a_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory13_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst13_matching_memory13_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst03_matching_memory13_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory12_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory12_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory12_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory13_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory13_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory13_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory15_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory14_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory15_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory14_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory15_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory14_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory10_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory12_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory10_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory10_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory12_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory12_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst23_matching_memory15_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory14_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory15_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory14_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory15_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory14_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory12_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory11_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory12_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory11_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory12_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory11_reg_b_3 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory13_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory13_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory15_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory14_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory15_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory14_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory15_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory14_reg_b_3 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory15_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory13_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory15_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory13_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory14_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory14_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory13_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory15_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory14_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory10_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory10_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory10_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory12_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst23_matching_memory14_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory14_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory14_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory15_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory15_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory15_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory13_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory13_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory13_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory13_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory13_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory15_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory15_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory12_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory12_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory12_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory15_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory15_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory15_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory14_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory14_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory14_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory14_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory14_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory10_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory10_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory10_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory10_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory10_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory10_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory10_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory10_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory10_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory11_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory11_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory11_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory11_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory11_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory11_reg_a_2 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory12_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory12_reg_a_2 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory13_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory13_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory15_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory14_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory15_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory14_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory15_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory14_reg_b_1 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory11_reg_b_1 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory13_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory13_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory13_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory12_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory12_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory12_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory15_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory13_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory15_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory13_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory14_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory14_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory13_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory15_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory14_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory10_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory10_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory10_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory13_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory13_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory13_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory15_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory14_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory15_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory14_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory15_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory14_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory10_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory12_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst01_matching_memory12_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory14_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory14_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory14_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst23_matching_memory15_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory15_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory15_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst12_matching_memory13_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst02_matching_memory13_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst22_matching_memory13_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst12_matching_memory15_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst23_matching_memory12_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory12_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory12_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst02_matching_memory15_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst22_matching_memory15_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst12_matching_memory14_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst02_matching_memory14_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst22_matching_memory14_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst23_matching_memory10_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory10_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory10_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst12_matching_memory10_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst02_matching_memory10_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst22_matching_memory10_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst23_matching_memory11_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory11_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory11_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst12_matching_memory11_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst02_matching_memory11_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst22_matching_memory11_reg_a_3 has been replicated 4 time(s) FlipFlop match_inst21_matching_memory12_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory12_reg_a_3 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory10_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory10_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory12_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst11_matching_memory12_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory15_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst23_matching_memory14_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory15_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory14_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory15_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory14_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst23_matching_memory12_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst23_matching_memory11_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory12_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst13_matching_memory11_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory12_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst03_matching_memory11_reg_b_0 has been replicated 4 time(s) FlipFlop match_inst22_matching_memory13_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory13_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory15_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory14_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory15_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory14_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory15_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory14_reg_b_0 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory13_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst13_matching_memory13_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst03_matching_memory13_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst12_matching_memory12_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst02_matching_memory12_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst22_matching_memory12_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory15_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory13_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory15_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory13_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory14_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory14_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory13_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory15_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory14_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory10_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst21_matching_memory10_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory10_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst01_matching_memory12_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst23_matching_memory14_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory14_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory14_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory15_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory15_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory15_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory13_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory12_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory12_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory12_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory15_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory14_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory10_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory10_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory10_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst23_matching_memory11_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst13_matching_memory11_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst03_matching_memory11_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst12_matching_memory11_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst02_matching_memory11_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst22_matching_memory11_reg_a_0 has been replicated 5 time(s) FlipFlop match_inst21_matching_memory12_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst11_matching_memory12_reg_a_0 has been replicated 6 time(s) FlipFlop match_inst13_matching_memory13_invalid_reg has been replicated 4 time(s) FlipFlop match_inst23_matching_memory11_invalid_reg has been replicated 3 time(s) FlipFlop match_inst13_matching_memory11_invalid_reg has been replicated 3 time(s) FlipFlop match_inst03_matching_memory11_invalid_reg has been replicated 3 time(s) FlipFlop match_inst23_matching_memory13_invalid_reg has been replicated 4 time(s) FlipFlop match_inst03_matching_memory13_invalid_reg has been replicated 4 time(s) FlipFlop match_inst23_matching_memory13_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst13_matching_memory13_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst03_matching_memory13_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory12_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory12_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory12_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst21_matching_memory11_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst11_matching_memory11_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst01_matching_memory11_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst23_matching_memory15_invalid_reg has been replicated 2 time(s) FlipFlop match_inst23_matching_memory14_invalid_reg has been replicated 2 time(s) FlipFlop match_inst13_matching_memory15_invalid_reg has been replicated 2 time(s) FlipFlop match_inst13_matching_memory14_invalid_reg has been replicated 2 time(s) FlipFlop match_inst03_matching_memory15_invalid_reg has been replicated 2 time(s) FlipFlop match_inst03_matching_memory14_invalid_reg has been replicated 2 time(s) FlipFlop match_inst21_matching_memory11_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory11_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory11_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory13_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory13_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory13_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory15_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory14_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory15_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory14_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory15_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory14_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory10_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory12_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory10_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory10_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory12_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory12_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory15_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory14_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory15_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory14_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory15_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory14_reg_b_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory13_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory15_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory14_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory10_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory11_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory11_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory11_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory11_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory11_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst12_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst02_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst22_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory13_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory13_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory13_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst22_matching_memory12_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst12_matching_memory12_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst02_matching_memory12_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory11_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory11_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory11_reg_b_0 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory13_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst13_matching_memory13_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst03_matching_memory13_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory12_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory12_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory12_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst21_matching_memory11_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst11_matching_memory11_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst01_matching_memory11_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst21_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst01_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst12_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst02_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst22_matching_memory13_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst12_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst02_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst22_matching_memory15_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst12_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst02_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst22_matching_memory14_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst12_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst02_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst22_matching_memory10_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst13_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst03_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst12_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst02_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst22_matching_memory11_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst21_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst11_matching_memory12_reg_a_4 has been replicated 2 time(s) FlipFlop match_inst23_matching_memory13_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst13_matching_memory13_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst03_matching_memory13_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory12_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory12_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory12_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst21_matching_memory11_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst11_matching_memory11_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst01_matching_memory11_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst23_matching_memory13_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory13_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory13_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory12_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory12_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory12_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory13_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory13_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory13_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory15_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory14_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory15_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory14_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory15_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory14_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory10_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory12_reg_b_5 has been replicated 1 time(s) FlipFlop match_inst21_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst01_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory11_invalid_reg has been replicated 1 time(s) FlipFlop match_inst13_matching_memory11_invalid_reg has been replicated 1 time(s) FlipFlop match_inst03_matching_memory11_invalid_reg has been replicated 1 time(s) FlipFlop match_inst21_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst11_matching_memory12_reg_a_5 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory10_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst13_matching_memory10_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst03_matching_memory10_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory10_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory10_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory10_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory11_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory11_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory13_reg_b_1 has been replicated 3 time(s) FlipFlop match_inst23_matching_memory10_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst13_matching_memory10_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst03_matching_memory10_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory11_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory10_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory10_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory10_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory11_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory11_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory13_reg_b_2 has been replicated 3 time(s) FlipFlop match_inst23_matching_memory10_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst13_matching_memory10_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst03_matching_memory10_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory11_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory10_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory10_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory10_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory11_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory11_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory13_reg_b_3 has been replicated 3 time(s) FlipFlop match_inst23_matching_memory10_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst13_matching_memory10_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst03_matching_memory10_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory11_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory10_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory10_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst02_matching_memory10_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst22_matching_memory11_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory11_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst12_matching_memory13_reg_b_0 has been replicated 3 time(s) FlipFlop match_inst03_matching_memory12_invalid_reg has been replicated 2 time(s) FlipFlop match_inst13_matching_memory12_invalid_reg has been replicated 2 time(s) FlipFlop match_inst23_matching_memory12_invalid_reg has been replicated 2 time(s) FlipFlop match_inst03_matching_memory10_invalid_reg has been replicated 1 time(s) FlipFlop match_inst23_matching_memory10_invalid_reg has been replicated 1 time(s) FlipFlop match_inst13_matching_memory10_invalid_reg has been replicated 1 time(s) FlipFlop match_inst23_matching_memory12_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory12_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory12_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory13_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory13_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory15_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory14_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory15_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory14_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory15_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory14_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst23_matching_memory10_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst13_matching_memory10_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst03_matching_memory10_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory10_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory10_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst02_matching_memory10_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst22_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory11_reg_b_4 has been replicated 1 time(s) FlipFlop match_inst12_matching_memory13_reg_b_4 has been replicated 1 time(s) FlipFlop z_channel_inst52_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst51_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst50_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst42_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst41_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst40_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst32_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst31_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst30_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst22_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst21_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst20_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst12_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst11_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst10_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst02_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst01_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst00_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst00_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst00_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst00_addr2_cnt_92 has been replicated 3 time(s) FlipFlop z_channel_inst01_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst01_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst01_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst02_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst02_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst02_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst10_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst10_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst10_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst11_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst11_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst11_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst12_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst12_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst12_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst20_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst20_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst20_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst21_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst21_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst21_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst22_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst22_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst22_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst30_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst30_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst30_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst31_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst31_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst31_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst32_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst32_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst32_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst40_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst40_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst40_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst41_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst41_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst41_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst42_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst42_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst42_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst50_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst50_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst50_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst51_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst51_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst51_addr2_cnt_91 has been replicated 3 time(s) FlipFlop z_channel_inst52_addr2_cnt_89 has been replicated 3 time(s) FlipFlop z_channel_inst52_addr2_cnt_90 has been replicated 3 time(s) FlipFlop z_channel_inst52_addr2_cnt_91 has been replicated 3 time(s) ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : toplevel.ngr Top Level Output File Name : toplevel Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 186 Macro Statistics : # RAM : 146 # 16x52-bit dual-port distributed RAM: 2 # 64x21-bit dual-port distributed RAM: 6 # 64x26-bit dual-port distributed RAM: 108 # 64x7-bit dual-port distributed RAM: 18 # 8x52-bit dual-port distributed RAM: 12 # ROMs : 13 # 22x13-bit ROM : 7 # 77x11-bit ROM : 1 # 78x11-bit ROM : 1 # 80x11-bit ROM : 4 # Registers : 2243 # 1-bit register : 1605 # 10-bit register : 6 # 13-bit register : 13 # 16-bit register : 25 # 18-bit register : 6 # 19-bit register : 6 # 2-bit register : 6 # 21-bit register : 1 # 3-bit register : 202 # 32-bit register : 12 # 4-bit register : 8 # 42-bit register : 11 # 6-bit register : 312 # 7-bit register : 6 # 8-bit register : 24 # Counters : 24 # 6-bit up counter : 24 # Shift Registers : 89 # 3-bit shift register : 5 # 5-bit shift register : 42 # 7-bit shift register : 42 # Multiplexers : 693 # 10-bit 4-to-1 multiplexer : 144 # 2-to-1 multiplexer : 261 # 3-bit 4-to-1 multiplexer : 144 # 6-bit 4-to-1 multiplexer : 144 # Adders/Subtractors : 141 # 10-bit adder : 18 # 10-bit subtractor : 18 # 11-bit adder : 6 # 12-bit adder : 1 # 13-bit adder : 12 # 17-bit subtractor : 1 # 18-bit adder : 6 # 19-bit adder : 6 # 32-bit adder : 30 # 33-bit adder : 10 # 6-bit adder : 12 # 7-bit subtractor : 9 # 8-bit adder : 6 # 8-bit subtractor : 6 # Multipliers : 15 # 4x3-bit multiplier : 3 # 7x8-bit multiplier : 6 # 9x9-bit multiplier : 6 # Comparators : 1489 # 10-bit comparator greater : 135 # 10-bit comparator less : 180 # 10-bit comparator lessequal : 144 # 3-bit comparator equal : 334 # 3-bit comparator greatequal : 9 # 3-bit comparator greater : 135 # 3-bit comparator less : 190 # 3-bit comparator not equal : 12 # 32-bit comparator greatequal: 5 # 4-bit comparator equal : 3 # 4-bit comparator less : 9 # 4-bit comparator not equal : 2 # 6-bit comparator equal : 84 # 6-bit comparator not equal : 54 # 7-bit comparator greater : 90 # 7-bit comparator less : 103 Cell Usage : # BELS : 41014 # BUF : 2 # GND : 14 # LUT1 : 586 # LUT1_D : 1 # LUT1_L : 590 # LUT2 : 2692 # LUT2_D : 339 # LUT2_L : 4434 # LUT3 : 7041 # LUT3_D : 169 # LUT3_L : 230 # LUT4 : 8028 # LUT4_D : 1782 # LUT4_L : 3283 # MUXCY : 7815 # MUXCY_D : 24 # MUXCY_L : 48 # MUXF5 : 2292 # MUXF6 : 66 # MUXF7 : 66 # VCC : 14 # XORCY : 1498 # FlipFlops/Latches : 9663 # FD : 717 # FDC : 903 # FDC_1 : 96 # FDCE : 971 # FDCE_1 : 396 # FDCPE : 360 # FDE : 299 # FDP : 5599 # FDPE : 240 # FDR : 28 # FDS : 54 # RAMS : 3635 # RAM16X1D : 728 # RAM64X1D : 2895 # RAMB16_S36_S36 : 12 # Shifters : 89 # SRL16E : 89 # Clock Buffers : 13 # BUFGP : 13 # IO Buffers : 173 # IBUF : 113 # OBUF : 60 # MULTs : 21 # MULT18X18 : 21 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2vp40ff1152-5 Number of Slices: 35347 out of 19392 182% (*) Number of Slice Flip Flops: 9663 out of 38784 24% Number of 4 input LUTs: 41572 out of 38784 107% (*) Number of bonded IOBs: 173 out of 692 25% Number of BRAMs: 12 out of 192 6% Number of MULT18X18s: 21 out of 192 10% Number of GCLKs: 13 out of 16 81% WARNING:Xst:1336 - (*) More than 100% of Device resources are used ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 12139 | clk0_in<5> | BUFGP | 103 | clk1_in<5> | BUFGP | 103 | input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE | 2 | input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE | 2 | clk0_in<4> | BUFGP | 103 | clk1_in<4> | BUFGP | 103 | input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE | 2 | input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE | 2 | clk0_in<3> | BUFGP | 103 | clk1_in<3> | BUFGP | 103 | input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE | 2 | input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE | 2 | clk0_in<2> | BUFGP | 103 | clk1_in<2> | BUFGP | 103 | input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE | 2 | input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE | 2 | clk0_in<1> | BUFGP | 103 | clk1_in<1> | BUFGP | 103 | input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE | 2 | input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE | 2 | clk0_in<0> | BUFGP | 103 | clk1_in<0> | BUFGP | 103 | input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE | 2 | input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE | 2 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -5 Minimum period: 19.303ns (Maximum Frequency: 51.805MHz) Minimum input arrival time before clock: 12.891ns Maximum output required time after clock: 7.822ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk' Delay: 19.303ns (Levels of Logic = 22) Source: match_inst21_matching_memory11_reg_a_3 (FF) Destination: match_inst21_matching_memory13_reg_a_0 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: match_inst21_matching_memory11_reg_a_3 to match_inst21_matching_memory13_reg_a_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDP:C->Q 20 0.419 0.962 match_inst21_matching_memory11_reg_a_3 (match_inst21_matching_memory11_reg_a_3) RAM64X1D:DPRA3->DPO 12 1.533 0.832 match_inst21_matching_memory11_Mram_ram_block_a_inst_ramx1d_1 (match_inst21_a_a<1><1>) LUT1_L:I0->LO 1 0.351 0.000 match_inst21_a_a<1><1>_rt (match_inst21_a_a<1><1>_rt) MUXCY:S->O 1 0.422 0.000 match_inst21_matching_logic1_Msub_asa_minus_inst_cy_145 (match_inst21_matching_logic1_Msub_asa_minus_inst_cy_145) MUXCY:CI->O 1 0.044 0.000 match_inst21_matching_logic1_Msub_asa_minus_inst_cy_146 (match_inst21_matching_logic1_Msub_asa_minus_inst_cy_146) MUXCY:CI->O 1 0.044 0.000 match_inst21_matching_logic1_Msub_asa_minus_inst_cy_147 (match_inst21_matching_logic1_Msub_asa_minus_inst_cy_147) MUXCY:CI->O 1 0.044 0.000 match_inst21_matching_logic1_Msub_asa_minus_inst_cy_148 (match_inst21_matching_logic1_Msub_asa_minus_inst_cy_148) MUXCY:CI->O 0 0.044 0.000 match_inst21_matching_logic1_Msub_asa_minus_inst_cy_149 (match_inst21_matching_logic1_Msub_asa_minus_inst_cy_149) XORCY:CI->O 20 0.973 0.962 match_inst21_matching_logic1_Msub_asa_minus_inst_sum_136 (match_inst21_matching_logic1_asa_minus<6>) LUT1:I0->O 0 0.351 0.000 match_inst21_matching_logic1_Mcompar__n0068_inst_inv_41 (match_inst21_matching_logic1_Mcompar__n0068_inst_inv_4) MUXCY:DI->O 2 1.212 0.624 match_inst21_matching_logic1_Mcompar__n0068_inst_cy_197 (match_inst21_matching_logic1_ang_a_ll_a<3>) LUT4:I0->O 1 0.351 0.468 match_inst21_matching_logic1__n006190_SW0 (N594891) LUT4:I0->O 7 0.351 0.702 match_inst21_matching_logic1__n04111 (match_inst21_matching_logic1_a_matches<3>) LUT4_D:I2->LO 1 0.351 0.100 match_inst21_matching_logic1__n0417 (N619429) LUT3:I0->O 3 0.351 0.637 match_inst21_matching_logic1_Mmux__n0002_Result<0>1 (match_inst21_matching_logic1__n0295<0>) LUT4:I2->O 1 0.351 0.468 match_inst21_matching_logic1_Madd_num_possible_match__n000172 (CHOICE20543) LUT4_D:I0->LO 1 0.351 0.100 match_inst21_matching_logic1_Madd_num_possible_match__n000191 (N625588) LUT4:I0->O 10 0.351 0.780 match_inst21_matching_logic1__n009941 (match_inst21_matching_logic1__n0099) LUT4_D:I0->O 10 0.351 0.780 match_inst21_matching_logic1__n0485<0>145 (match_inst21_inc<4><0>) LUT2:I0->O 2 0.351 0.624 match_inst21_matching_memory14_Ker2655481 (match_inst21_matching_memory14_N265550) LUT4:I3->O 6 0.351 0.676 match_inst21_matching_memory14_Ker2653341 (match_inst21_matching_memory14_N265336) LUT4_D:I0->O 6 0.351 0.676 match_inst21_matching_memory14__n0037<0>22 (match_inst21_matching_memory14_CHOICE5759) LUT4_L:I1->LO 1 0.351 0.000 match_inst21_matching_memory14__n0037<0>38_5 (N605167) FDP:D 0.263 match_inst21_matching_memory14_reg_a_0_5 ---------------------------------------- Total 19.303ns (9.912ns logic, 9.391ns route) (51.3% logic, 48.7% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk0_in<5>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst5_inputcontrol0_stage_a_end (FF) Destination: input_inst5_inputcontrol0_d_out_reg_31 (FF) Source Clock: clk0_in<5> falling Destination Clock: clk0_in<5> rising Data Path: input_inst5_inputcontrol0_stage_a_end to input_inst5_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst5_inputcontrol0_stage_a_end (input_inst5_inputcontrol0_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst5_inputcontrol0_enable1 (input_inst5_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst5_inputcontrol0__n0017<16>1 (input_inst5_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst5_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk1_in<5>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst5_inputcontrol1_stage_a_end (FF) Destination: input_inst5_inputcontrol1_d_out_reg_31 (FF) Source Clock: clk1_in<5> falling Destination Clock: clk1_in<5> rising Data Path: input_inst5_inputcontrol1_stage_a_end to input_inst5_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst5_inputcontrol1_stage_a_end (input_inst5_inputcontrol1_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst5_inputcontrol1_enable1 (input_inst5_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst5_inputcontrol1__n0017<16>1 (input_inst5_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst5_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk0_in<4>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst4_inputcontrol0_stage_a_end (FF) Destination: input_inst4_inputcontrol0_d_out_reg_31 (FF) Source Clock: clk0_in<4> falling Destination Clock: clk0_in<4> rising Data Path: input_inst4_inputcontrol0_stage_a_end to input_inst4_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst4_inputcontrol0_stage_a_end (input_inst4_inputcontrol0_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst4_inputcontrol0_enable1 (input_inst4_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst4_inputcontrol0__n0017<16>1 (input_inst4_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst4_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk1_in<4>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst4_inputcontrol1_stage_a_end (FF) Destination: input_inst4_inputcontrol1_d_out_reg_31 (FF) Source Clock: clk1_in<4> falling Destination Clock: clk1_in<4> rising Data Path: input_inst4_inputcontrol1_stage_a_end to input_inst4_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst4_inputcontrol1_stage_a_end (input_inst4_inputcontrol1_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst4_inputcontrol1_enable1 (input_inst4_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst4_inputcontrol1__n0017<16>1 (input_inst4_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst4_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk0_in<3>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst3_inputcontrol0_stage_a_end (FF) Destination: input_inst3_inputcontrol0_d_out_reg_31 (FF) Source Clock: clk0_in<3> falling Destination Clock: clk0_in<3> rising Data Path: input_inst3_inputcontrol0_stage_a_end to input_inst3_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst3_inputcontrol0_stage_a_end (input_inst3_inputcontrol0_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst3_inputcontrol0_enable1 (input_inst3_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst3_inputcontrol0__n0017<16>1 (input_inst3_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst3_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk1_in<3>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst3_inputcontrol1_stage_a_end (FF) Destination: input_inst3_inputcontrol1_d_out_reg_31 (FF) Source Clock: clk1_in<3> falling Destination Clock: clk1_in<3> rising Data Path: input_inst3_inputcontrol1_stage_a_end to input_inst3_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst3_inputcontrol1_stage_a_end (input_inst3_inputcontrol1_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst3_inputcontrol1_enable1 (input_inst3_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst3_inputcontrol1__n0017<16>1 (input_inst3_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst3_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk0_in<2>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst2_inputcontrol0_stage_a_end (FF) Destination: input_inst2_inputcontrol0_d_out_reg_31 (FF) Source Clock: clk0_in<2> falling Destination Clock: clk0_in<2> rising Data Path: input_inst2_inputcontrol0_stage_a_end to input_inst2_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst2_inputcontrol0_stage_a_end (input_inst2_inputcontrol0_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst2_inputcontrol0_enable1 (input_inst2_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst2_inputcontrol0__n0017<16>1 (input_inst2_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst2_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk1_in<2>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst2_inputcontrol1_stage_a_end (FF) Destination: input_inst2_inputcontrol1_d_out_reg_31 (FF) Source Clock: clk1_in<2> falling Destination Clock: clk1_in<2> rising Data Path: input_inst2_inputcontrol1_stage_a_end to input_inst2_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst2_inputcontrol1_stage_a_end (input_inst2_inputcontrol1_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst2_inputcontrol1_enable1 (input_inst2_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst2_inputcontrol1__n0017<16>1 (input_inst2_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst2_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk0_in<1>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst1_inputcontrol0_stage_a_end (FF) Destination: input_inst1_inputcontrol0_d_out_reg_31 (FF) Source Clock: clk0_in<1> falling Destination Clock: clk0_in<1> rising Data Path: input_inst1_inputcontrol0_stage_a_end to input_inst1_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst1_inputcontrol0_stage_a_end (input_inst1_inputcontrol0_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst1_inputcontrol0_enable1 (input_inst1_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst1_inputcontrol0__n0017<16>1 (input_inst1_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst1_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk1_in<1>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst1_inputcontrol1_stage_a_end (FF) Destination: input_inst1_inputcontrol1_d_out_reg_31 (FF) Source Clock: clk1_in<1> falling Destination Clock: clk1_in<1> rising Data Path: input_inst1_inputcontrol1_stage_a_end to input_inst1_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst1_inputcontrol1_stage_a_end (input_inst1_inputcontrol1_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst1_inputcontrol1_enable1 (input_inst1_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst1_inputcontrol1__n0017<16>1 (input_inst1_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst1_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk0_in<0>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst0_inputcontrol0_stage_a_end (FF) Destination: input_inst0_inputcontrol0_d_out_reg_31 (FF) Source Clock: clk0_in<0> falling Destination Clock: clk0_in<0> rising Data Path: input_inst0_inputcontrol0_stage_a_end to input_inst0_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst0_inputcontrol0_stage_a_end (input_inst0_inputcontrol0_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst0_inputcontrol0_enable1 (input_inst0_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst0_inputcontrol0__n0017<16>1 (input_inst0_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst0_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk1_in<0>' Delay: 2.970ns (Levels of Logic = 2) Source: input_inst0_inputcontrol1_stage_a_end (FF) Destination: input_inst0_inputcontrol1_d_out_reg_31 (FF) Source Clock: clk1_in<0> falling Destination Clock: clk1_in<0> rising Data Path: input_inst0_inputcontrol1_stage_a_end to input_inst0_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE_1:C->Q 5 0.419 0.663 input_inst0_inputcontrol1_stage_a_end (input_inst0_inputcontrol1_stage_a_end) LUT4:I1->O 17 0.351 0.923 input_inst0_inputcontrol1_enable1 (input_inst0_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst0_inputcontrol1__n0017<16>1 (input_inst0_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst0_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 2.970ns (1.384ns logic, 1.586ns route) (46.6% logic, 53.4% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 12.891ns (Levels of Logic = 12) Source: chamber<1> (PAD) Destination: z_channel_inst00_sorter1_idx_5_2 (FF) Destination Clock: clk rising Data Path: chamber<1> to z_channel_inst00_sorter1_idx_5_2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 236 0.969 1.238 chamber_1_IBUF (chamber_1_IBUF) LUT2:I0->O 1 0.351 0.468 z_channel_inst51_zch_table1_index<1>34 (CHOICE10329) LUT4:I3->O 1 0.351 0.468 z_channel_inst51_zch_table1_index<1>44 (CHOICE10333) LUT4:I2->O 1 0.351 0.468 z_channel_inst51_zch_table1_index<1>67 (CHOICE10336) LUT4:I0->O 9 0.351 0.754 z_channel_inst51_zch_table1_index<1>180 (z_channel_inst51_idx<1>) LUT2:I0->O 27 0.351 1.031 z_channel_inst51_sorter1_idx_in_i<1>1 (z_channel_inst51_sorter1_idx_in_i<1>) LUT4:I0->O 1 0.351 0.468 z_channel_inst51_sorter1__n00735 (z_channel_inst51_sorter1_CHOICE5657) LUT4:I2->O 1 0.351 0.468 z_channel_inst51_sorter1__n007388 (z_channel_inst51_sorter1_CHOICE5677) LUT4:I1->O 6 0.351 0.676 z_channel_inst51_sorter1__n0073193 (z_channel_inst51_sorter1_lower_as<2>) LUT3:I2->O 1 0.351 0.468 z_channel_inst51_sorter1__n0212<1>20 (z_channel_inst51_sorter1_CHOICE5345) LUT3:I0->O 19 0.351 0.949 z_channel_inst51_sorter1__n0212<1>22 (z_channel_inst51_sorter1_action<2><1>) MUXF5:S->O 1 0.693 0.000 z_channel_inst51_sorter1_Mmux__n0058_inst_mux_f5_270111 (z_channel_inst51_sorter1__n0058<8>) FDP:D 0.263 z_channel_inst51_sorter1_y_3_8 ---------------------------------------- Total 12.891ns (5.435ns logic, 7.456ns route) (42.2% logic, 57.8% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk0_in<5>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst5_inputcontrol0_d_out_reg_31 (FF) Destination Clock: clk0_in<5> rising Data Path: pretrigger to input_inst5_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst5_inputcontrol0_Ker2517671 (input_inst5_inputcontrol0_N251769) LUT4:I3->O 17 0.351 0.923 input_inst5_inputcontrol0_enable1 (input_inst5_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst5_inputcontrol0__n0017<16>1 (input_inst5_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst5_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1_in<5>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst5_inputcontrol1_d_out_reg_31 (FF) Destination Clock: clk1_in<5> rising Data Path: pretrigger to input_inst5_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst5_inputcontrol1_Ker2517671 (input_inst5_inputcontrol1_N251769) LUT4:I3->O 17 0.351 0.923 input_inst5_inputcontrol1_enable1 (input_inst5_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst5_inputcontrol1__n0017<16>1 (input_inst5_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst5_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk0_in<4>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst4_inputcontrol0_d_out_reg_31 (FF) Destination Clock: clk0_in<4> rising Data Path: pretrigger to input_inst4_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst4_inputcontrol0_Ker2517671 (input_inst4_inputcontrol0_N251769) LUT4:I3->O 17 0.351 0.923 input_inst4_inputcontrol0_enable1 (input_inst4_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst4_inputcontrol0__n0017<16>1 (input_inst4_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst4_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1_in<4>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst4_inputcontrol1_d_out_reg_31 (FF) Destination Clock: clk1_in<4> rising Data Path: pretrigger to input_inst4_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst4_inputcontrol1_Ker2517671 (input_inst4_inputcontrol1_N251769) LUT4:I3->O 17 0.351 0.923 input_inst4_inputcontrol1_enable1 (input_inst4_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst4_inputcontrol1__n0017<16>1 (input_inst4_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst4_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk0_in<3>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst3_inputcontrol0_d_out_reg_31 (FF) Destination Clock: clk0_in<3> rising Data Path: pretrigger to input_inst3_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst3_inputcontrol0_Ker2517671 (input_inst3_inputcontrol0_N251769) LUT4:I3->O 17 0.351 0.923 input_inst3_inputcontrol0_enable1 (input_inst3_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst3_inputcontrol0__n0017<16>1 (input_inst3_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst3_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1_in<3>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst3_inputcontrol1_d_out_reg_31 (FF) Destination Clock: clk1_in<3> rising Data Path: pretrigger to input_inst3_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst3_inputcontrol1_Ker2517671 (input_inst3_inputcontrol1_N251769) LUT4:I3->O 17 0.351 0.923 input_inst3_inputcontrol1_enable1 (input_inst3_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst3_inputcontrol1__n0017<16>1 (input_inst3_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst3_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk0_in<2>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst2_inputcontrol0_d_out_reg_31 (FF) Destination Clock: clk0_in<2> rising Data Path: pretrigger to input_inst2_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst2_inputcontrol0_Ker2517671 (input_inst2_inputcontrol0_N251769) LUT4:I3->O 17 0.351 0.923 input_inst2_inputcontrol0_enable1 (input_inst2_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst2_inputcontrol0__n0017<16>1 (input_inst2_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst2_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1_in<2>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst2_inputcontrol1_d_out_reg_31 (FF) Destination Clock: clk1_in<2> rising Data Path: pretrigger to input_inst2_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst2_inputcontrol1_Ker2517671 (input_inst2_inputcontrol1_N251769) LUT4:I3->O 17 0.351 0.923 input_inst2_inputcontrol1_enable1 (input_inst2_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst2_inputcontrol1__n0017<16>1 (input_inst2_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst2_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk0_in<1>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst1_inputcontrol0_d_out_reg_31 (FF) Destination Clock: clk0_in<1> rising Data Path: pretrigger to input_inst1_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst1_inputcontrol0_Ker2517671 (input_inst1_inputcontrol0_N251769) LUT4:I3->O 17 0.351 0.923 input_inst1_inputcontrol0_enable1 (input_inst1_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst1_inputcontrol0__n0017<16>1 (input_inst1_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst1_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1_in<1>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst1_inputcontrol1_d_out_reg_31 (FF) Destination Clock: clk1_in<1> rising Data Path: pretrigger to input_inst1_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst1_inputcontrol1_Ker2517671 (input_inst1_inputcontrol1_N251769) LUT4:I3->O 17 0.351 0.923 input_inst1_inputcontrol1_enable1 (input_inst1_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst1_inputcontrol1__n0017<16>1 (input_inst1_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst1_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk0_in<0>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst0_inputcontrol0_d_out_reg_31 (FF) Destination Clock: clk0_in<0> rising Data Path: pretrigger to input_inst0_inputcontrol0_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst0_inputcontrol0_Ker2517671 (input_inst0_inputcontrol0_N251769) LUT4:I3->O 17 0.351 0.923 input_inst0_inputcontrol0_enable1 (input_inst0_inputcontrol0_enable) LUT2:I0->O 1 0.351 0.000 input_inst0_inputcontrol0__n0017<16>1 (input_inst0_inputcontrol0__n0017<16>) FDC:D 0.263 input_inst0_inputcontrol0_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1_in<0>' Offset: 5.083ns (Levels of Logic = 4) Source: pretrigger (PAD) Destination: input_inst0_inputcontrol1_d_out_reg_31 (FF) Destination Clock: clk1_in<0> rising Data Path: pretrigger to input_inst0_inputcontrol1_d_out_reg_31 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 351 0.969 1.238 pretrigger_IBUF (pretrigger_IBUF) LUT2:I0->O 3 0.351 0.637 input_inst0_inputcontrol1_Ker2517671 (input_inst0_inputcontrol1_N251769) LUT4:I3->O 17 0.351 0.923 input_inst0_inputcontrol1_enable1 (input_inst0_inputcontrol1_enable) LUT2:I0->O 1 0.351 0.000 input_inst0_inputcontrol1__n0017<16>1 (input_inst0_inputcontrol1__n0017<16>) FDC:D 0.263 input_inst0_inputcontrol1_d_out_reg_16 ---------------------------------------- Total 5.083ns (2.285ns logic, 2.798ns route) (45.0% logic, 55.0% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 7.822ns (Levels of Logic = 19) Source: reconst_inst_pt_raw_stage4_1 (FF) Destination: pt_out<15> (PAD) Source Clock: clk rising Data Path: reconst_inst_pt_raw_stage4_1 to pt_out<15> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.419 0.624 reconst_inst_pt_raw_stage4_1 (reconst_inst_pt_raw_stage4_1) LUT1:I0->O 1 0.351 0.000 reconst_inst_Msub__n0002_inst_lut2_781 (reconst_inst_Msub__n0002_inst_lut2_78) MUXCY:S->O 1 0.422 0.000 reconst_inst_Msub__n0002_inst_cy_76 (reconst_inst_Msub__n0002_inst_cy_76) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_77 (reconst_inst_Msub__n0002_inst_cy_77) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_78 (reconst_inst_Msub__n0002_inst_cy_78) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_79 (reconst_inst_Msub__n0002_inst_cy_79) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_80 (reconst_inst_Msub__n0002_inst_cy_80) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_81 (reconst_inst_Msub__n0002_inst_cy_81) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_82 (reconst_inst_Msub__n0002_inst_cy_82) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_83 (reconst_inst_Msub__n0002_inst_cy_83) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_84 (reconst_inst_Msub__n0002_inst_cy_84) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_85 (reconst_inst_Msub__n0002_inst_cy_85) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_86 (reconst_inst_Msub__n0002_inst_cy_86) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_87 (reconst_inst_Msub__n0002_inst_cy_87) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_88 (reconst_inst_Msub__n0002_inst_cy_88) MUXCY:CI->O 1 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_89 (reconst_inst_Msub__n0002_inst_cy_89) MUXCY:CI->O 0 0.044 0.000 reconst_inst_Msub__n0002_inst_cy_90 (reconst_inst_Msub__n0002_inst_cy_90) XORCY:CI->O 1 0.973 0.468 reconst_inst_Msub__n0002_inst_sum_93 (reconst_inst__n0271<33>) LUT3:I2->O 1 0.351 0.468 reconst_inst_Mmux_pt_ext_comb4_Result<16>1 (pt_out_15_OBUF) OBUF:I->O 3.130 pt_out_15_OBUF (pt_out<15>) ---------------------------------------- Total 7.822ns (6.262ns logic, 1.560ns route) (80.1% logic, 19.9% route) ========================================================================= CPU : 1113.55 / 1116.13 s | Elapsed : 1162.00 / 1162.00 s --> Total memory usage is 563912 kilobytes