vhdl work ../src/gtu_types.vhd
vhdl work ../src/inputcontrol.vhd
vhdl work cg_fifo_dc.vhd
vhdl work ../src/fifo_dc_wrapper_xilinx.vhd
vhdl work ../src/buffer_merger.vhd
vhdl work ../src/proj_d.vhd
vhdl work ../src/proj_y.vhd
vhdl work ../src/rec_tables.vhd
vhdl work ../src/input.vhd
vhdl work ../src/zch_table.vhd
vhdl work ../src/sorter.vhd
vhdl work ../src/z_channel.vhd
vhdl work ../src/matching_memory.vhd
vhdl work ../src/matching_logic.vhd
vhdl work ../src/track_types.vhd
vhdl work ../src/match.vhd
vhdl work ../src/seed_merger.vhd
vhdl work ../src/uniquifier.vhd
vhdl work ../src/zch_merger.vhd
vhdl work ../src/zch_resorter.vhd
vhdl work ../src/unique.vhd
vhdl work ../src/mult_wrapper_xilinx.vhd
vhdl work cg_divide.vhd
vhdl work ../src/divide_wrapper_xilinx.vhd
vhdl work ../src/reconst.vhd
vhdl work ../src/toplevel.vhd