JDF G
// Created by Project Navigator ver 1.0
PROJECT syn_ise
DESIGN syn_ise
DEVFAM virtex2p
DEVFAMTIME 0
DEVICE xc2vp40
DEVICETIME 1083159142
DEVPKG ff1152
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ../src/buffer_merger.vhd
SOURCE ../src/divide_wrapper_xilinx.vhd
SOURCE ../src/fifo_dc_wrapper_xilinx.vhd
SOURCE ../src/gtu_types.vhd
SOURCE ../src/input.vhd
SOURCE ../src/inputcontrol.vhd
SOURCE ../src/match.vhd
SOURCE ../src/matching_logic.vhd
SOURCE ../src/matching_memory.vhd
SOURCE ../src/mult_wrapper_xilinx.vhd
SOURCE ../src/proj_d.vhd
SOURCE ../src/proj_y.vhd
SOURCE ../src/rec_tables.vhd
SOURCE ../src/reconst.vhd
SOURCE ../src/seed_merger.vhd
SOURCE ../src/sorter.vhd
SOURCE ../src/toplevel.vhd
SOURCE ../src/track_types.vhd
SOURCE ../src/unique.vhd
SOURCE ../src/uniquifier.vhd
SOURCE ../src/z_channel.vhd
SOURCE ../src/zch_merger.vhd
SOURCE ../src/zch_resorter.vhd
SOURCE ../src/zch_table.vhd
SOURCE cg_fifo_dc.xco
SOURCE cg_divide.xco
SOURCE delme.vhd
SOURCE downgrade.vhd
DEPASSOC toplevel toplevel.ucf
[STATUS-ALL]
downgrade.ngcFile=WARNINGS,1084890141
mult_wrapper.ngcFile=WARNINGS,1083162043
z_channel.ngcFile=ERRORS,0
[STRATEGY-LIST]
cFile=False
el.ngcFile=False
GS,1083162043=False
Normal=True
toplevel.ngdFile=False