Release 6.2i - xst G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 2.39 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 2.39 s | Elapsed : 0.00 / 1.00 s --> Reading design: mult_wrapper.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : mult_wrapper.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : mult_wrapper Output Format : NGC Target Device : xc2vp40-5-ff1152 ---- Source Options Top Module Name : mult_wrapper Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : mult_wrapper.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES Optimize Instantiated Primitives : NO tristate2logic : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:766 - /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd line 60: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 19-bit register for signal . Found 19-bit adder for signal . Summary: inferred 19 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 19-bit adder : 1 # Registers : 1 19-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block mult_wrapper, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : mult_wrapper.ngr Top Level Output File Name : mult_wrapper Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 46 Macro Statistics : # Registers : 1 # 19-bit register : 1 # Adders/Subtractors : 1 # 19-bit adder : 1 Cell Usage : # BELS : 56 # GND : 1 # LUT1 : 18 # MUXCY : 18 # VCC : 1 # XORCY : 18 # FlipFlops/Latches : 19 # FDC : 19 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 45 # IBUF : 27 # OBUF : 18 # MULTs : 1 # MULT18X18 : 1 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2vp40ff1152-5 Number of Slices: 21 out of 19392 0% Number of Slice Flip Flops: 19 out of 38784 0% Number of 4 input LUTs: 18 out of 38784 0% Number of bonded IOBs: 45 out of 692 6% Number of MULT18X18s: 1 out of 192 0% Number of GCLKs: 1 out of 16 6% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 19 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: 6.523ns Maximum output required time after clock: 6.979ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 6.523ns (Levels of Logic = 2) Source: a<12> (PAD) Destination: product_reg_18 (FF) Destination Clock: clk rising Data Path: a<12> to product_reg_18 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 6 0.969 0.676 a_12_IBUF (a_12_IBUF) MULT18X18:A12->P25 1 4.147 0.468 mult_inst (product<25>) FDC:D 0.263 product_reg_18 ---------------------------------------- Total 6.523ns (5.379ns logic, 1.144ns route) (82.5% logic, 17.5% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 6.979ns (Levels of Logic = 21) Source: product_reg_0 (FF) Destination: result<17> (PAD) Source Clock: clk rising Data Path: product_reg_0 to result<17> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 1 0.419 0.468 product_reg_0 (product_reg_0) LUT1:I0->O 1 0.351 0.000 Madd_result_ext_inst_lut2_01 (Madd_result_ext_inst_lut2_0) MUXCY:S->O 1 0.422 0.000 Madd_result_ext_inst_cy_0 (Madd_result_ext_inst_cy_0) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_1 (Madd_result_ext_inst_cy_1) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_2 (Madd_result_ext_inst_cy_2) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_3 (Madd_result_ext_inst_cy_3) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_4 (Madd_result_ext_inst_cy_4) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_5 (Madd_result_ext_inst_cy_5) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_6 (Madd_result_ext_inst_cy_6) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_7 (Madd_result_ext_inst_cy_7) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_8 (Madd_result_ext_inst_cy_8) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_9 (Madd_result_ext_inst_cy_9) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_10 (Madd_result_ext_inst_cy_10) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_11 (Madd_result_ext_inst_cy_11) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_12 (Madd_result_ext_inst_cy_12) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_13 (Madd_result_ext_inst_cy_13) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_14 (Madd_result_ext_inst_cy_14) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_15 (Madd_result_ext_inst_cy_15) MUXCY:CI->O 1 0.044 0.000 Madd_result_ext_inst_cy_16 (Madd_result_ext_inst_cy_16) MUXCY:CI->O 0 0.044 0.000 Madd_result_ext_inst_cy_17 (Madd_result_ext_inst_cy_17) XORCY:CI->O 1 0.973 0.468 Madd_result_ext_inst_sum_18 (result_17_OBUF) OBUF:I->O 3.130 result_17_OBUF (result<17>) ---------------------------------------- Total 6.979ns (6.043ns logic, 0.936ns route) (86.6% logic, 13.4% route) ========================================================================= CPU : 25.81 / 28.78 s | Elapsed : 48.00 / 50.00 s --> Total memory usage is 134256 kilobytes