library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity delme is
    Port ( clk:in std_logic;
	 			wr_addr : in std_logic_vector(3 downto 0);
           rd_addr : in std_logic_vector(3 downto 0);
           wr_data : in std_logic_vector(15 downto 0);
           rd_data : out std_logic_vector(15 downto 0);
           wr_enable : in std_logic);
end delme;

architecture Behavioral of delme is

 type ram_type is array (15 downto 0) of std_logic_vector (15 downto 0); 
 signal RAM : ram_type; 
 signal read_a : std_logic_vector(3 downto 0); 

begin

 process (clk) 
 begin 
 	if (clk'event and clk = '1') then  
 		if (wr_enable = '1') then 
 			RAM(conv_integer(wr_addr)) <= wr_data; 
 		end if; 
 		read_a <= rd_addr; 
 	end if; 
 end process; 
 
 rd_data <= RAM(conv_integer(read_a)); 

end Behavioral;