Release 6.2i - xst G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 2.32 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 2.32 s | Elapsed : 0.00 / 0.00 s --> Reading design: delme.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : delme.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : delme Output Format : NGC Target Device : xc2vp40-5-ff1152 ---- Source Options Top Module Name : delme Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : delme.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES Optimize Instantiated Primitives : NO tristate2logic : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/delme.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/delme.vhd. Found 16x16-bit dual-port block RAM for signal . ----------------------------------------------------------------------- | dual mode | write-first | | | aspect ratio | 16-word x 16-bit | | | clock | connected to signal | rise | | dual clock | connected to signal | rise | | write enable | connected to signal | high | | address | connected to signal | | | dual address | connected to signal | | | data in | connected to signal | | | data out | not connected | | | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- Summary: inferred 1 RAM(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Block RAMs : 1 16x16-bit dual-port block RAM : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block delme, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : delme.ngr Top Level Output File Name : delme Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 42 Macro Statistics : # RAM : 1 # 16x16-bit dual-port block RAM: 1 Cell Usage : # BELS : 2 # GND : 1 # VCC : 1 # RAMS : 1 # RAMB16_S36_S36 : 1 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 41 # IBUF : 25 # OBUF : 16 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2vp40ff1152-5 Number of bonded IOBs: 41 out of 692 5% Number of BRAMs: 1 out of 192 0% Number of GCLKs: 1 out of 16 6% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 1 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: 1.821ns Maximum output required time after clock: 5.278ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 1.821ns (Levels of Logic = 1) Source: wr_enable (PAD) Destination: Mram_RAM_inst_ramb_0 (RAM) Destination Clock: clk rising Data Path: wr_enable to Mram_RAM_inst_ramb_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.969 0.468 wr_enable_IBUF (wr_enable_IBUF) RAMB16_S36_S36:WEA 0.384 Mram_RAM_inst_ramb_0 ---------------------------------------- Total 1.821ns (1.353ns logic, 0.468ns route) (74.3% logic, 25.7% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 5.278ns (Levels of Logic = 1) Source: Mram_RAM_inst_ramb_0 (RAM) Destination: rd_data<15> (PAD) Source Clock: clk rising Data Path: Mram_RAM_inst_ramb_0 to rd_data<15> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAMB16_S36_S36:CLKB->DOB15 1 1.680 0.468 Mram_RAM_inst_ramb_0 (rd_data_15_OBUF) OBUF:I->O 3.130 rd_data_15_OBUF (rd_data<15>) ---------------------------------------- Total 5.278ns (4.810ns logic, 0.468ns route) (91.1% logic, 8.9% route) ========================================================================= CPU : 24.86 / 27.75 s | Elapsed : 31.00 / 32.00 s --> Total memory usage is 124084 kilobytes