# Xilinx CORE Generator 6.2i
# User = cuveland
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in /home/cuveland/nfs/vhdl/gtu/syn_ise/coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=/home/cuveland/nfs/vhdl/gtu/syn_ise
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=/home/cuveland/nfs/vhdl/gtu/syn_ise
SETPROJECT .
Set current Project to /home/cuveland/nfs/vhdl/gtu/syn_ise
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 33106
XIPCPJSENDCORES virtex2p