# Xilinx CORE Generator 6.2i
# Username = cuveland
# COREGenPath = /cad/products/xilinx/6.2i/coregen
# ProjectPath = /home/cuveland/SORTME/ise_test/components
# ExpandedProjectPath = /home/cuveland/SORTME/ise_test/components
# OverwriteFiles = False
# Core name: cg_fifo_dc
# Number of Primitives in design: 114
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 40
# Number of LUTs used in design: 40
# Number of REG used in design: 39
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 1
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET SimulationOutputProducts = VHDL
SET XilinxFamily = Virtex2
SET OutputOption = DesignFlow
SET DesignFlow = VHDL
SET FlowVendor = Other
SET FormalVerification = None
SELECT Asynchronous_FIFO Virtex2 Xilinx,_Inc. 5.1
CSET read_error_sense = active_high
CSET read_count_width = 2
CSET write_acknowledge = false
CSET create_rpm = false
CSET read_acknowledge = false
CSET read_count = false
CSET write_error = false
CSET almost_full_flag = false
CSET almost_empty_flag = false
CSET memory_type = block
CSET read_error = false
CSET fifo_depth = 31
CSET component_name = cg_fifo_dc
CSET input_data_width = 32
CSET write_count = false
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 2
GENERATE