# Xilinx CORE Generator 6.2i
SELECT Pipelined_Divider Virtex2 Xilinx,_Inc. 2.0
CSET dividend_width = 21
CSET signed_b = true
CSET component_name = cg_divide
CSET fractional_b = false
CSET divisor_width = 16
CSET fractional_width = 16
CSET divclk_sel = 8
GENERATE