# Xilinx CORE Generator 6.2i
# Username = cuveland
# COREGenPath = /cad/products/xilinx/6.2i/coregen
# ProjectPath = /home/cuveland/SORTME/ise_test/components
# ExpandedProjectPath = /home/cuveland/SORTME/ise_test/components
# OverwriteFiles = False
# Core name: cg_divide
# Number of Primitives in design: 1063
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 270
# Number of LUTs used in design: 270
# Number of REG used in design: 487
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET SimulationOutputProducts = VHDL
SET XilinxFamily = Virtex2
SET OutputOption = DesignFlow
SET DesignFlow = VHDL
SET FlowVendor = Other
SET FormalVerification = None
SELECT Pipelined_Divider Virtex2 Xilinx,_Inc. 2.0
CSET dividend_width = 21
CSET signed_b = true
CSET component_name = cg_divide
CSET fractional_b = false
CSET divisor_width = 16
CSET fractional_width = 16
CSET divclk_sel = 8
GENERATE