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--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
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-- You must compile the wrapper file cg_divide.vhd when simulating
-- the core, cg_divide. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY cg_divide IS
	port (
	dividend: IN std_logic_VECTOR(20 downto 0);
	divisor: IN std_logic_VECTOR(15 downto 0);
	quot: OUT std_logic_VECTOR(20 downto 0);
	remd: OUT std_logic_VECTOR(15 downto 0);
	c: IN std_logic);
END cg_divide;

ARCHITECTURE cg_divide_a OF cg_divide IS

component wrapped_cg_divide
	port (
	dividend: IN std_logic_VECTOR(20 downto 0);
	divisor: IN std_logic_VECTOR(15 downto 0);
	quot: OUT std_logic_VECTOR(20 downto 0);
	remd: OUT std_logic_VECTOR(15 downto 0);
	c: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_cg_divide use entity XilinxCoreLib.dividervht(behavioral)
		generic map(
			dividend_width => 21,
			signed_b => 1,
			fractional_b => 0,
			divisor_width => 16,
			fractional_width => 16,
			divclk_sel => 8);
BEGIN

U0 : wrapped_cg_divide
		port map (
			dividend => dividend,
			divisor => divisor,
			quot => quot,
			remd => remd,
			c => c);
END cg_divide_a;

-- synopsys translate_on