Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd in Library work.
Entity <mult_wrapper> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mult_wrapper> (Architecture <default>).
WARNING:Xst:766 - /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd line 60: Generating a Black Box for component <mult18x18>.
Entity <mult_wrapper> analyzed. Unit <mult_wrapper> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mult_wrapper>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd.
WARNING:Xst:646 - Signal <product<35:26>> is assigned but never used.
WARNING:Xst:646 - Signal <product<6:0>> is assigned but never used.
WARNING:Xst:646 - Signal <result_ext<0>> is assigned but never used.
    Found 19-bit register for signal <product_reg>.
    Found 19-bit adder for signal <result_ext>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <mult_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 19-bit adder                      : 1
# Registers                        : 1
 19-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mult_wrapper> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mult_wrapper, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                      21  out of  19392     0%  
 Number of Slice Flip Flops:            19  out of  38784     0%  
 Number of 4 input LUTs:                18  out of  38784     0%  
 Number of bonded IOBs:                 45  out of    692     6%  
 Number of MULT18X18s:                   1  out of    192     0%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 19    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: 6.523ns
   Maximum output required time after clock: 6.979ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd in Library work.
Entity <inputcontrol> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/cg_fifo_dc.vhd in Library work.
ERROR:HDLParsers:3264 - Can't read file /electra/cuveland/vhdl/gtu/syn_ise/cg_fifo_dc.vhd: No such file or directory
--> 


Total memory usage is 40796 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file /electra/cuveland/vhdl/gtu/syn_ise/cg_divide.vhd. Ignore this file from project file toplevel_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file /electra/cuveland/vhdl/gtu/syn_ise/cg_fifo_dc.vhd. Ignore this file from project file toplevel_vhdl.prj.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd in Library work.
Entity <fifo_dc_wrapper> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd in Library work.
Entity <mask_id_lut> (Architecture <default>) compiled.
Entity <yt_lut> (Architecture <default>) compiled.
Entity <c1_lut> (Architecture <default>) compiled.
Entity <acoeff_lut> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd in Library work.
Architecture default of Entity mult_wrapper is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd in Library work.
Entity <divide_wrapper> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/seed_merger.vhd in Library work.
Entity <seed_merger> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd in Library work.
Entity <uniquifier> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Entity <zch_merger> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd in Library work.
Entity <zch_resorter> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_memory.vhd in Library work.
Entity <matching_memory> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd in Library work.
Entity <matching_logic> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd in Library work.
Entity <zch_table> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd in Library work.
Entity <sorter> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd in Library work.
Architecture default of Entity inputcontrol is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd in Library work.
Entity <buffer_merger> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd in Library work.
Entity <proj_d> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd in Library work.
Entity <proj_y> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd in Library work.
Entity <input> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd in Library work.
Entity <z_channel> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd in Library work.
Entity <match> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/unique.vhd in Library work.
Entity <unique> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/reconst.vhd in Library work.
Entity <reconst> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/toplevel.vhd in Library work.
Entity <toplevel> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <toplevel> (Architecture <default>).
Entity <toplevel> analyzed. Unit <toplevel> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 5
Entity <input> analyzed. Unit <input> generated.

Analyzing Entity <inputcontrol> (Architecture <default>).
Entity <inputcontrol> analyzed. Unit <inputcontrol> generated.

Analyzing Entity <buffer_merger> (Architecture <default>).
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd line 148: The following signals are missing in the process sensitivity list:
   data<1><23>, data<1><22>, data<1><21>, data<1><20>, data<0><23>, data<0><22>, data<0><21>, data<0><20>.
Entity <buffer_merger> analyzed. Unit <buffer_merger> generated.

Analyzing Entity <fifo_dc_wrapper> (Architecture <default>).
WARNING:Xst:753 - /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Unconnected output port 'full' of component 'cg_fifo_dc'.
WARNING:Xst:766 - /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Generating a Black Box for component <cg_fifo_dc>.
Entity <fifo_dc_wrapper> analyzed. Unit <fifo_dc_wrapper> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 5
Entity <proj_d> analyzed. Unit <proj_d> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 5
Entity <proj_y> analyzed. Unit <proj_y> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 5
Entity <yt_lut> analyzed. Unit <yt_lut> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 4
Entity <input> analyzed. Unit <input0> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 4
Entity <proj_d> analyzed. Unit <proj_d24> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 4
Entity <proj_y> analyzed. Unit <proj_y25> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 4
Entity <yt_lut> analyzed. Unit <yt_lut26> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 3
Entity <input> analyzed. Unit <input1> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 3
Entity <proj_d> analyzed. Unit <proj_d27> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 3
Entity <proj_y> analyzed. Unit <proj_y28> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 3
Entity <yt_lut> analyzed. Unit <yt_lut29> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 2
Entity <input> analyzed. Unit <input2> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 2
Entity <proj_d> analyzed. Unit <proj_d30> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 2
Entity <proj_y> analyzed. Unit <proj_y31> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 2
Entity <yt_lut> analyzed. Unit <yt_lut32> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 1
Entity <input> analyzed. Unit <input3> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 1
Entity <proj_d> analyzed. Unit <proj_d33> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 1
Entity <proj_y> analyzed. Unit <proj_y34> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 1
Entity <yt_lut> analyzed. Unit <yt_lut35> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 0
Entity <input> analyzed. Unit <input4> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 0
Entity <proj_d> analyzed. Unit <proj_d36> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 0
Entity <proj_y> analyzed. Unit <proj_y37> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 0
Entity <yt_lut> analyzed. Unit <yt_lut38> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 5
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 5
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table> generated.

Analyzing generic Entity <sorter> (Architecture <default>).
	depth = 8
ERROR:Xst:1548 - /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd line 60: Negative range in type of signal <y> is not supported.
--> 


Total memory usage is 52292 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file /electra/cuveland/vhdl/gtu/syn_ise/cg_divide.vhd. Ignore this file from project file toplevel_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file /electra/cuveland/vhdl/gtu/syn_ise/cg_fifo_dc.vhd. Ignore this file from project file toplevel_vhdl.prj.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd in Library work.
Architecture default of Entity fifo_dc_wrapper is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd in Library work.
Architecture default of Entity mask_id_lut is up to date.
Architecture default of Entity yt_lut is up to date.
Architecture default of Entity c1_lut is up to date.
Architecture default of Entity acoeff_lut is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd in Library work.
Architecture default of Entity mult_wrapper is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd in Library work.
Architecture default of Entity divide_wrapper is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/seed_merger.vhd in Library work.
Architecture default of Entity seed_merger is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd in Library work.
Architecture default of Entity uniquifier is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Architecture default of Entity zch_merger is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd in Library work.
Architecture default of Entity zch_resorter is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_memory.vhd in Library work.
Architecture default of Entity matching_memory is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd in Library work.
Architecture default of Entity matching_logic is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd in Library work.
Architecture default of Entity zch_table is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd in Library work.
Entity <sorter> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd in Library work.
Architecture default of Entity inputcontrol is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd in Library work.
Architecture default of Entity buffer_merger is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd in Library work.
Architecture default of Entity proj_d is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd in Library work.
Architecture default of Entity proj_y is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd in Library work.
Architecture default of Entity input is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd in Library work.
Architecture default of Entity z_channel is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd in Library work.
Architecture default of Entity match is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/unique.vhd in Library work.
Architecture default of Entity unique is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/reconst.vhd in Library work.
Architecture default of Entity reconst is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/toplevel.vhd in Library work.
Architecture default of Entity toplevel is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <toplevel> (Architecture <default>).
Entity <toplevel> analyzed. Unit <toplevel> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 5
Entity <input> analyzed. Unit <input> generated.

Analyzing Entity <inputcontrol> (Architecture <default>).
Entity <inputcontrol> analyzed. Unit <inputcontrol> generated.

Analyzing Entity <buffer_merger> (Architecture <default>).
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd line 148: The following signals are missing in the process sensitivity list:
   data<1><23>, data<1><22>, data<1><21>, data<1><20>, data<0><23>, data<0><22>, data<0><21>, data<0><20>.
Entity <buffer_merger> analyzed. Unit <buffer_merger> generated.

Analyzing Entity <fifo_dc_wrapper> (Architecture <default>).
WARNING:Xst:753 - /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Unconnected output port 'full' of component 'cg_fifo_dc'.
WARNING:Xst:766 - /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Generating a Black Box for component <cg_fifo_dc>.
Entity <fifo_dc_wrapper> analyzed. Unit <fifo_dc_wrapper> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 5
Entity <proj_d> analyzed. Unit <proj_d> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 5
Entity <proj_y> analyzed. Unit <proj_y> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 5
Entity <yt_lut> analyzed. Unit <yt_lut> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 4
Entity <input> analyzed. Unit <input0> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 4
Entity <proj_d> analyzed. Unit <proj_d24> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 4
Entity <proj_y> analyzed. Unit <proj_y25> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 4
Entity <yt_lut> analyzed. Unit <yt_lut26> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 3
Entity <input> analyzed. Unit <input1> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 3
Entity <proj_d> analyzed. Unit <proj_d27> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 3
Entity <proj_y> analyzed. Unit <proj_y28> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 3
Entity <yt_lut> analyzed. Unit <yt_lut29> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 2
Entity <input> analyzed. Unit <input2> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 2
Entity <proj_d> analyzed. Unit <proj_d30> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 2
Entity <proj_y> analyzed. Unit <proj_y31> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 2
Entity <yt_lut> analyzed. Unit <yt_lut32> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 1
Entity <input> analyzed. Unit <input3> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 1
Entity <proj_d> analyzed. Unit <proj_d33> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 1
Entity <proj_y> analyzed. Unit <proj_y34> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 1
Entity <yt_lut> analyzed. Unit <yt_lut35> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 0
Entity <input> analyzed. Unit <input4> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 0
Entity <proj_d> analyzed. Unit <proj_d36> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 0
Entity <proj_y> analyzed. Unit <proj_y37> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 0
Entity <yt_lut> analyzed. Unit <yt_lut38> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 5
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 5
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table> generated.

Analyzing generic Entity <sorter> (Architecture <default>).
	depth = 8
ERROR:Xst:1548 - /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd line 74: Negative range in type of signal <lower_as> is not supported.
--> 


Total memory usage is 52396 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file /electra/cuveland/vhdl/gtu/syn_ise/cg_divide.vhd. Ignore this file from project file toplevel_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file /electra/cuveland/vhdl/gtu/syn_ise/cg_fifo_dc.vhd. Ignore this file from project file toplevel_vhdl.prj.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd in Library work.
Architecture default of Entity fifo_dc_wrapper is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd in Library work.
Architecture default of Entity mask_id_lut is up to date.
Architecture default of Entity yt_lut is up to date.
Architecture default of Entity c1_lut is up to date.
Architecture default of Entity acoeff_lut is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd in Library work.
Architecture default of Entity mult_wrapper is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd in Library work.
Architecture default of Entity divide_wrapper is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/seed_merger.vhd in Library work.
Architecture default of Entity seed_merger is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd in Library work.
Architecture default of Entity uniquifier is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Architecture default of Entity zch_merger is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd in Library work.
Architecture default of Entity zch_resorter is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_memory.vhd in Library work.
Architecture default of Entity matching_memory is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd in Library work.
Architecture default of Entity matching_logic is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd in Library work.
Architecture default of Entity zch_table is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd in Library work.
Entity <sorter> (Architecture <default>) compiled.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd in Library work.
Architecture default of Entity inputcontrol is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd in Library work.
Architecture default of Entity buffer_merger is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd in Library work.
Architecture default of Entity proj_d is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd in Library work.
Architecture default of Entity proj_y is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd in Library work.
Architecture default of Entity input is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd in Library work.
Architecture default of Entity z_channel is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd in Library work.
Architecture default of Entity match is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/unique.vhd in Library work.
Architecture default of Entity unique is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/reconst.vhd in Library work.
Architecture default of Entity reconst is up to date.
Compiling vhdl file /electra/cuveland/vhdl/gtu/syn_ise/../src/toplevel.vhd in Library work.
Architecture default of Entity toplevel is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <toplevel> (Architecture <default>).
Entity <toplevel> analyzed. Unit <toplevel> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 5
Entity <input> analyzed. Unit <input> generated.

Analyzing Entity <inputcontrol> (Architecture <default>).
Entity <inputcontrol> analyzed. Unit <inputcontrol> generated.

Analyzing Entity <buffer_merger> (Architecture <default>).
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd line 148: The following signals are missing in the process sensitivity list:
   data<1><23>, data<1><22>, data<1><21>, data<1><20>, data<0><23>, data<0><22>, data<0><21>, data<0><20>.
Entity <buffer_merger> analyzed. Unit <buffer_merger> generated.

Analyzing Entity <fifo_dc_wrapper> (Architecture <default>).
WARNING:Xst:753 - /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Unconnected output port 'full' of component 'cg_fifo_dc'.
WARNING:Xst:766 - /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Generating a Black Box for component <cg_fifo_dc>.
Entity <fifo_dc_wrapper> analyzed. Unit <fifo_dc_wrapper> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 5
Entity <proj_d> analyzed. Unit <proj_d> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 5
Entity <proj_y> analyzed. Unit <proj_y> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 5
Entity <yt_lut> analyzed. Unit <yt_lut> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 4
Entity <input> analyzed. Unit <input0> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 4
Entity <proj_d> analyzed. Unit <proj_d24> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 4
Entity <proj_y> analyzed. Unit <proj_y25> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 4
Entity <yt_lut> analyzed. Unit <yt_lut26> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 3
Entity <input> analyzed. Unit <input1> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 3
Entity <proj_d> analyzed. Unit <proj_d27> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 3
Entity <proj_y> analyzed. Unit <proj_y28> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 3
Entity <yt_lut> analyzed. Unit <yt_lut29> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 2
Entity <input> analyzed. Unit <input2> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 2
Entity <proj_d> analyzed. Unit <proj_d30> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 2
Entity <proj_y> analyzed. Unit <proj_y31> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 2
Entity <yt_lut> analyzed. Unit <yt_lut32> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 1
Entity <input> analyzed. Unit <input3> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 1
Entity <proj_d> analyzed. Unit <proj_d33> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 1
Entity <proj_y> analyzed. Unit <proj_y34> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 1
Entity <yt_lut> analyzed. Unit <yt_lut35> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 0
Entity <input> analyzed. Unit <input4> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 0
Entity <proj_d> analyzed. Unit <proj_d36> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 0
Entity <proj_y> analyzed. Unit <proj_y37> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 0
Entity <yt_lut> analyzed. Unit <yt_lut38> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 5
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 5
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table> generated.

Analyzing generic Entity <sorter> (Architecture <default>).
	depth = 8
Entity <sorter> analyzed. Unit <sorter> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 5
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel5> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 5
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table39> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 5
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel6> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 5
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table40> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 4
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel7> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 4
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table41> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 4
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel8> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 4
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table42> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 4
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel9> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 4
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table43> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 3
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel10> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 3
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table44> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 3
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel11> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 3
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table45> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 3
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel12> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 3
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table46> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 2
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel13> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 2
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table47> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 2
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel14> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 2
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table48> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 2
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel15> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 2
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table49> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 1
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel16> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 1
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table50> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 1
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel17> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 1
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table51> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 1
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel18> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 1
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table52> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 0
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel19> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 0
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table53> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 0
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel20> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 0
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table54> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 0
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel21> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 0
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table55> generated.

Analyzing generic Entity <match> (Architecture <default>).
	seedline = 3
	line_mask = 0
Entity <match> analyzed. Unit <match> generated.

Analyzing Entity <matching_memory> (Architecture <default>).
Entity <matching_memory> analyzed. Unit <matching_memory> generated.

Analyzing generic Entity <matching_logic> (Architecture <default>).
	seedline = 3
	line_mask = 0
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
Entity <matching_logic> analyzed. Unit <matching_logic> generated.

Analyzing generic Entity <match> (Architecture <default>).
	seedline = 2
	line_mask = 8
Entity <match> analyzed. Unit <match22> generated.

Analyzing generic Entity <matching_logic> (Architecture <default>).
	seedline = 2
	line_mask = 8
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
Entity <matching_logic> analyzed. Unit <matching_logic56> generated.

Analyzing generic Entity <match> (Architecture <default>).
	seedline = 1
	line_mask = 12
Entity <match> analyzed. Unit <match23> generated.

Analyzing generic Entity <matching_logic> (Architecture <default>).
	seedline = 1
	line_mask = 12
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
Entity <matching_logic> analyzed. Unit <matching_logic57> generated.

Analyzing Entity <unique> (Architecture <default>).
Entity <unique> analyzed. Unit <unique> generated.

Analyzing Entity <seed_merger> (Architecture <default>).
Entity <seed_merger> analyzed. Unit <seed_merger> generated.

Analyzing generic Entity <uniquifier> (Architecture <default>).
	track_width = 52
WARNING:Xst:1610 - /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 101: Width mismatch. <data_stage0> has a width of 42 bits but assigned expression is 52-bit wide.
WARNING:Xst:1610 - /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 110: Width mismatch. <track_out> has a width of 52 bits but assigned expression is 42-bit wide.
Entity <uniquifier> analyzed. Unit <uniquifier> generated.

Analyzing Entity <zch_merger> (Architecture <default>).
Entity <zch_merger> analyzed. Unit <zch_merger> generated.

Analyzing generic Entity <uniquifier> (Architecture <default>).
	track_width = 53
WARNING:Xst:1610 - /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 101: Width mismatch. <data_stage0> has a width of 42 bits but assigned expression is 53-bit wide.
WARNING:Xst:1610 - /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 110: Width mismatch. <track_out> has a width of 53 bits but assigned expression is 42-bit wide.
Entity <uniquifier> analyzed. Unit <uniquifier58> generated.

Analyzing Entity <zch_resorter> (Architecture <default>).
WARNING:Xst:819 - /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd line 200: The following signals are missing in the process sensitivity list:
   mem_out<1><41>, mem_out<1><40>, mem_out<1><39>, mem_out<1><38>, mem_out<1><37>, mem_out<1><36>, mem_out<1><35>, mem_out<1><34>, mem_out<1><33>, mem_out<1><32>, mem_out<1><31>, mem_out<1><30>, mem_out<1><29>, mem_out<1><28>, mem_out<1><27>, mem_out<1><26>, mem_out<1><25>, mem_out<1><24>, mem_out<1><23>, mem_out<1><22>, mem_out<1><21>, mem_out<1><20>, mem_out<1><19>, mem_out<1><18>, mem_out<1><17>, mem_out<1><16>, mem_out<1><15>, mem_out<1><14>, mem_out<1><13>, mem_out<1><12>, mem_out<1><11>, mem_out<1><10>, mem_out<1><9>, mem_out<1><8>, mem_out<1><7>, mem_out<1><6>, mem_out<1><5>, mem_out<1><4>, mem_out<1><3>, mem_out<1><2>, mem_out<1><1>, mem_out<1><0>, mem_out<0><41>, mem_out<0><40>, mem_out<0><39>, mem_out<0><38>, mem_out<0><37>, mem_out<0><36>, mem_out<0><35>, mem_out<0><34>, mem_out<0><33>, mem_out<0><32>, mem_out<0><31>, mem_out<0><30>, mem_out<0><29>, mem_out<0><28>, mem_out<0><27>, mem_out<0><26>, mem_out<0><25>, mem_out<0><24>, mem_out<0><23>, mem_out<0><22>, mem_out<0><21>, mem_out<0><20>,
   mem_out<0><19>, mem_out<0><18>, mem_out<0><17>, mem_out<0><16>, mem_out<0><15>, mem_out<0><14>, mem_out<0><13>, mem_out<0><12>, mem_out<0><11>, mem_out<0><10>, mem_out<0><9>, mem_out<0><8>, mem_out<0><7>, mem_out<0><6>, mem_out<0><5>, mem_out<0><4>, mem_out<0><3>, mem_out<0><2>, mem_out<0><1>, mem_out<0><0>.
Entity <zch_resorter> analyzed. Unit <zch_resorter> generated.

Analyzing generic Entity <uniquifier> (Architecture <default>).
	track_width = 42
Entity <uniquifier> analyzed. Unit <uniquifier59> generated.

Analyzing Entity <reconst> (Architecture <default>).
Entity <reconst> analyzed. Unit <reconst> generated.

Analyzing Entity <mask_id_lut> (Architecture <default>).
Entity <mask_id_lut> analyzed. Unit <mask_id_lut> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 5
Entity <acoeff_lut> analyzed. Unit <acoeff_lut> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 4
Entity <acoeff_lut> analyzed. Unit <acoeff_lut60> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 3
Entity <acoeff_lut> analyzed. Unit <acoeff_lut61> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 2
Entity <acoeff_lut> analyzed. Unit <acoeff_lut62> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 1
Entity <acoeff_lut> analyzed. Unit <acoeff_lut63> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 0
Entity <acoeff_lut> analyzed. Unit <acoeff_lut64> generated.

Analyzing Entity <c1_lut> (Architecture <default>).
Entity <c1_lut> analyzed. Unit <c1_lut> generated.

Analyzing Entity <mult_wrapper> (Architecture <default>).
WARNING:Xst:766 - /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd line 60: Generating a Black Box for component <mult18x18>.
Entity <mult_wrapper> analyzed. Unit <mult_wrapper> generated.

Analyzing generic Entity <divide_wrapper> (Architecture <default>).
	div_stages = 7
WARNING:Xst:753 - /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd line 58: Unconnected output port 'remd' of component 'cg_divide'.
WARNING:Xst:766 - /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd line 58: Generating a Black Box for component <cg_divide>.
Entity <divide_wrapper> analyzed. Unit <divide_wrapper> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <divide_wrapper>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd.
WARNING:Xst:647 - Input <aclr> is never used.
Unit <divide_wrapper> synthesized.


Synthesizing Unit <mult_wrapper>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd.
WARNING:Xst:646 - Signal <product<35:26>> is assigned but never used.
WARNING:Xst:646 - Signal <product<6:0>> is assigned but never used.
WARNING:Xst:646 - Signal <result_ext<0>> is assigned but never used.
    Found 19-bit register for signal <product_reg>.
    Found 19-bit adder for signal <result_ext>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <mult_wrapper> synthesized.


Synthesizing Unit <c1_lut>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <c1>.
    Summary:
	inferred   1 ROM(s).
Unit <c1_lut> synthesized.


Synthesizing Unit <acoeff_lut64>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut64> synthesized.


Synthesizing Unit <acoeff_lut63>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut63> synthesized.


Synthesizing Unit <acoeff_lut62>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut62> synthesized.


Synthesizing Unit <acoeff_lut61>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut61> synthesized.


Synthesizing Unit <acoeff_lut60>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut60> synthesized.


Synthesizing Unit <acoeff_lut>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut> synthesized.


Synthesizing Unit <mask_id_lut>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
Unit <mask_id_lut> synthesized.


Synthesizing Unit <uniquifier59>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd.
    Using one-hot encoding for signal <drop>.
    Found 2-bit adder for signal <$n0027> created at line 72.
    Found 2-bit adder for signal <$n0029> created at line 72.
    Found 32-bit adder for signal <$n0030> created at line 72.
    Found 32-bit adder for signal <$n0031> created at line 72.
    Found 32-bit comparator greatequal for signal <$n0039> created at line 169.
    Found 32-bit adder for signal <$n0040> created at line 72.
    Found 33-bit adder for signal <$n0043> created at line 72.
    Found 32-bit adder for signal <$n0044> created at line 72.
    Found 33-bit adder for signal <$n0047> created at line 72.
    Found 32-bit adder for signal <$n0062> created at line 72.
    Found 32-bit adder for signal <$n0071> created at line 72.
    Found 6-bit comparator equal for signal <$n0078> created at line 152.
    Found 6-bit comparator equal for signal <$n0079> created at line 152.
    Found 6-bit comparator equal for signal <$n0080> created at line 152.
    Found 6-bit comparator equal for signal <$n0081> created at line 152.
    Found 6-bit comparator equal for signal <$n0082> created at line 152.
    Found 6-bit comparator equal for signal <$n0083> created at line 152.
    Found 1-bit adder carry out for signal <$n0084> created at line 72.
    Found 1-bit adder carry out for signal <$n0085> created at line 72.
    Found 42-bit register for signal <data_stage0>.
    Found 42-bit register for signal <data_stage1>.
    Found 1-bit register for signal <ready_stage0>.
    Found 1-bit register for signal <valid_stage0>.
    Found 1-bit register for signal <valid_stage1>.
    Found 324 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  87 D-type flip-flop(s).
	inferred  12 Adder/Subtracter(s).
	inferred   7 Comparator(s).
	inferred 324 Multiplexer(s).
Unit <uniquifier59> synthesized.


Synthesizing Unit <zch_resorter>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd.
    Found 16x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 16-word x 52-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in_i<1>> | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in_i>    |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 16x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 16-word x 52-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in_i<0>> | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in_i>    |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 4-bit comparator not equal for signal <$n0016> created at line 166.
    Found 4-bit comparator not equal for signal <$n0017> created at line 166.
    Found 3-bit comparator less for signal <$n0029> created at line 184.
    Found 3-bit comparator equal for signal <$n0030> created at line 184.
    Found 7-bit comparator less for signal <$n0031> created at line 184.
    Found 4-bit up counter for signal <rd_addr_reg>.
    Found 1-bit register for signal <ready_in_reg>.
    Found 8-bit register for signal <wr_addr_last>.
    Found 4-bit up counter for signal <wr_addr_reg>.
    Found 42 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 RAM(s).
	inferred   4 Counter(s).
	inferred   9 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred  42 Multiplexer(s).
Unit <zch_resorter> synthesized.


Synthesizing Unit <uniquifier58>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd.
WARNING:Xst:647 - Input <track_in<52:42>> is never used.
    Using one-hot encoding for signal <drop>.
    Found 2-bit adder for signal <$n0027> created at line 72.
    Found 2-bit adder for signal <$n0029> created at line 72.
    Found 32-bit adder for signal <$n0030> created at line 72.
    Found 32-bit adder for signal <$n0031> created at line 72.
    Found 32-bit comparator greatequal for signal <$n0039> created at line 169.
    Found 32-bit adder for signal <$n0040> created at line 72.
    Found 33-bit adder for signal <$n0043> created at line 72.
    Found 32-bit adder for signal <$n0044> created at line 72.
    Found 33-bit adder for signal <$n0047> created at line 72.
    Found 32-bit adder for signal <$n0062> created at line 72.
    Found 32-bit adder for signal <$n0071> created at line 72.
    Found 6-bit comparator equal for signal <$n0078> created at line 152.
    Found 6-bit comparator equal for signal <$n0079> created at line 152.
    Found 6-bit comparator equal for signal <$n0080> created at line 152.
    Found 6-bit comparator equal for signal <$n0081> created at line 152.
    Found 6-bit comparator equal for signal <$n0082> created at line 152.
    Found 6-bit comparator equal for signal <$n0083> created at line 152.
    Found 1-bit adder carry out for signal <$n0084> created at line 72.
    Found 1-bit adder carry out for signal <$n0085> created at line 72.
    Found 42-bit register for signal <data_stage0>.
    Found 42-bit register for signal <data_stage1>.
    Found 1-bit register for signal <ready_stage0>.
    Found 1-bit register for signal <valid_stage0>.
    Found 1-bit register for signal <valid_stage1>.
    Found 324 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  87 D-type flip-flop(s).
	inferred  12 Adder/Subtracter(s).
	inferred   7 Comparator(s).
	inferred 324 Multiplexer(s).
Unit <uniquifier58> synthesized.


Synthesizing Unit <zch_merger>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0004> created at line 103.
    Found 6-bit adder for signal <$n0012> created at line 103.
    Found 6-bit adder for signal <$n0013>.
    Found 4-bit adder for signal <$n0017> created at line 94.
    Found 6-bit adder for signal <$n0022> created at line 103.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0048> created at line 103.
    Found 3-bit adder for signal <$n0049> created at line 94.
    Found 3-bit comparator not equal for signal <$n0053> created at line 178.
    Found 3-bit comparator not equal for signal <$n0057> created at line 178.
    Found 3-bit comparator not equal for signal <$n0061> created at line 178.
    Found 4-bit adder for signal <$n0067>.
    Found 4-bit adder for signal <$n0072>.
    Found 4-bit subtractor for signal <$n0088> created at line 103.
    Found 4-bit subtractor for signal <$n0089> created at line 103.
    Found 4-bit subtractor for signal <$n0090> created at line 103.
    Found 4-bit comparator less for signal <$n0091> created at line 182.
    Found 4-bit comparator equal for signal <$n0092> created at line 182.
    Found 7-bit comparator less for signal <$n0093> created at line 182.
    Found 4-bit comparator less for signal <$n0094> created at line 182.
    Found 4-bit comparator equal for signal <$n0095> created at line 182.
    Found 7-bit comparator less for signal <$n0096> created at line 182.
    Found 4-bit comparator less for signal <$n0097> created at line 182.
    Found 4-bit comparator equal for signal <$n0098> created at line 182.
    Found 7-bit comparator less for signal <$n0099> created at line 182.
    Found 4x3-bit multiplier for signal <$n0103> created at line 103.
    Found 4x3-bit multiplier for signal <$n0104> created at line 103.
    Found 4x3-bit multiplier for signal <$n0105> created at line 103.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  13 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


Synthesizing Unit <uniquifier>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd.
WARNING:Xst:647 - Input <track_in<51:42>> is never used.
    Using one-hot encoding for signal <drop>.
    Found 2-bit adder for signal <$n0027> created at line 72.
    Found 2-bit adder for signal <$n0029> created at line 72.
    Found 32-bit adder for signal <$n0030> created at line 72.
    Found 32-bit adder for signal <$n0031> created at line 72.
    Found 32-bit comparator greatequal for signal <$n0039> created at line 169.
    Found 32-bit adder for signal <$n0040> created at line 72.
    Found 33-bit adder for signal <$n0043> created at line 72.
    Found 32-bit adder for signal <$n0044> created at line 72.
    Found 33-bit adder for signal <$n0047> created at line 72.
    Found 32-bit adder for signal <$n0062> created at line 72.
    Found 32-bit adder for signal <$n0071> created at line 72.
    Found 6-bit comparator equal for signal <$n0078> created at line 152.
    Found 6-bit comparator equal for signal <$n0079> created at line 152.
    Found 6-bit comparator equal for signal <$n0080> created at line 152.
    Found 6-bit comparator equal for signal <$n0081> created at line 152.
    Found 6-bit comparator equal for signal <$n0082> created at line 152.
    Found 6-bit comparator equal for signal <$n0083> created at line 152.
    Found 1-bit adder carry out for signal <$n0084> created at line 72.
    Found 1-bit adder carry out for signal <$n0085> created at line 72.
    Found 42-bit register for signal <data_stage0>.
    Found 42-bit register for signal <data_stage1>.
    Found 1-bit register for signal <ready_stage0>.
    Found 1-bit register for signal <valid_stage0>.
    Found 1-bit register for signal <valid_stage1>.
    Found 324 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  87 D-type flip-flop(s).
	inferred  12 Adder/Subtracter(s).
	inferred   7 Comparator(s).
	inferred 324 Multiplexer(s).
Unit <uniquifier> synthesized.


Synthesizing Unit <seed_merger>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/seed_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 3-bit comparator not equal for signal <$n0024> created at line 149.
    Found 3-bit comparator not equal for signal <$n0026> created at line 149.
    Found 3-bit comparator not equal for signal <$n0028> created at line 149.
    Found 3-bit comparator less for signal <$n0045> created at line 153.
    Found 3-bit comparator equal for signal <$n0046> created at line 153.
    Found 7-bit comparator less for signal <$n0047> created at line 153.
    Found 3-bit comparator less for signal <$n0048> created at line 153.
    Found 3-bit comparator equal for signal <$n0049> created at line 153.
    Found 7-bit comparator less for signal <$n0050> created at line 153.
    Found 3-bit comparator less for signal <$n0051> created at line 153.
    Found 3-bit comparator equal for signal <$n0052> created at line 153.
    Found 7-bit comparator less for signal <$n0053> created at line 153.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  12 Comparator(s).
Unit <seed_merger> synthesized.


Synthesizing Unit <matching_logic57>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd.
WARNING:Xst:646 - Signal <ab<1>> is assigned but never used.
WARNING:Xst:646 - Signal <tinc<1>> is assigned but never used.
WARNING:Xst:646 - Signal <num_possible_match<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_a_ll_b<1>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_b_ll_b<1>> is assigned but never used.
    Found 3-bit adder for signal <$n0004> created at line 193.
    Found 6-bit adder for signal <$n0038> created at line 129.
    Found 7-bit comparator less for signal <$n0046> created at line 172.
    Found 7-bit comparator greater for signal <$n0047> created at line 173.
    Found 7-bit comparator less for signal <$n0048> created at line 174.
    Found 7-bit comparator greater for signal <$n0049> created at line 175.
    Found 7-bit comparator less for signal <$n0057> created at line 172.
    Found 7-bit comparator greater for signal <$n0058> created at line 173.
    Found 7-bit comparator less for signal <$n0059> created at line 174.
    Found 7-bit comparator greater for signal <$n0060> created at line 175.
    Found 7-bit comparator less for signal <$n0068> created at line 172.
    Found 7-bit comparator greater for signal <$n0069> created at line 173.
    Found 7-bit comparator less for signal <$n0070> created at line 174.
    Found 7-bit comparator greater for signal <$n0071> created at line 175.
    Found 7-bit comparator less for signal <$n0079> created at line 172.
    Found 7-bit comparator greater for signal <$n0080> created at line 173.
    Found 7-bit comparator less for signal <$n0081> created at line 174.
    Found 7-bit comparator greater for signal <$n0082> created at line 175.
    Found 7-bit comparator less for signal <$n0090> created at line 172.
    Found 7-bit comparator greater for signal <$n0091> created at line 173.
    Found 7-bit comparator less for signal <$n0092> created at line 174.
    Found 7-bit comparator greater for signal <$n0093> created at line 175.
    Found 3-bit adder for signal <$n0094> created at line 194.
    Found 3-bit adder for signal <$n0096> created at line 206.
    Found 3-bit adder for signal <$n0097> created at line 218.
    Found 3-bit comparator greatequal for signal <$n0100> created at line 238.
    Found 3-bit adder for signal <$n0102> created at line 194.
    Found 3-bit adder for signal <$n0103> created at line 194.
    Found 3-bit adder for signal <$n0104> created at line 194.
    Found 3-bit adder for signal <$n0106> created at line 206.
    Found 3-bit adder for signal <$n0108> created at line 206.
    Found 3-bit adder for signal <$n0110> created at line 206.
    Found 3-bit adder for signal <$n0111> created at line 218.
    Found 3-bit adder for signal <$n0112> created at line 218.
    Found 3-bit adder for signal <$n0113> created at line 218.
    Found 3-bit comparator less for signal <$n0139> created at line 150.
    Found 3-bit comparator equal for signal <$n0140> created at line 150.
    Found 10-bit comparator less for signal <$n0141> created at line 150.
    Found 3-bit comparator greater for signal <$n0142> created at line 153.
    Found 10-bit comparator greater for signal <$n0143> created at line 153.
    Found 3-bit comparator less for signal <$n0144> created at line 156.
    Found 3-bit comparator equal for signal <$n0145> created at line 156.
    Found 10-bit comparator less for signal <$n0146> created at line 156.
    Found 3-bit comparator greater for signal <$n0147> created at line 159.
    Found 10-bit comparator greater for signal <$n0148> created at line 159.
    Found 3-bit comparator less for signal <$n0149> created at line 162.
    Found 3-bit comparator equal for signal <$n0150> created at line 162.
    Found 10-bit comparator less for signal <$n0151> created at line 162.
    Found 3-bit comparator greater for signal <$n0152> created at line 165.
    Found 10-bit comparator greater for signal <$n0153> created at line 165.
    Found 3-bit comparator less for signal <$n0154> created at line 168.
    Found 3-bit comparator equal for signal <$n0155> created at line 168.
    Found 10-bit comparator less for signal <$n0156> created at line 168.
    Found 3-bit comparator less for signal <$n0157> created at line 150.
    Found 3-bit comparator equal for signal <$n0158> created at line 150.
    Found 10-bit comparator less for signal <$n0159> created at line 150.
    Found 3-bit comparator greater for signal <$n0160> created at line 153.
    Found 10-bit comparator greater for signal <$n0161> created at line 153.
    Found 3-bit comparator less for signal <$n0162> created at line 156.
    Found 3-bit comparator equal for signal <$n0163> created at line 156.
    Found 10-bit comparator less for signal <$n0164> created at line 156.
    Found 3-bit comparator greater for signal <$n0165> created at line 159.
    Found 10-bit comparator greater for signal <$n0166> created at line 159.
    Found 3-bit comparator less for signal <$n0167> created at line 162.
    Found 3-bit comparator equal for signal <$n0168> created at line 162.
    Found 10-bit comparator less for signal <$n0169> created at line 162.
    Found 3-bit comparator greater for signal <$n0170> created at line 165.
    Found 10-bit comparator greater for signal <$n0171> created at line 165.
    Found 3-bit comparator less for signal <$n0172> created at line 168.
    Found 3-bit comparator equal for signal <$n0173> created at line 168.
    Found 10-bit comparator less for signal <$n0174> created at line 168.
    Found 3-bit comparator less for signal <$n0175> created at line 150.
    Found 3-bit comparator equal for signal <$n0176> created at line 150.
    Found 10-bit comparator less for signal <$n0177> created at line 150.
    Found 3-bit comparator greater for signal <$n0178> created at line 153.
    Found 10-bit comparator greater for signal <$n0179> created at line 153.
    Found 3-bit comparator less for signal <$n0180> created at line 156.
    Found 3-bit comparator equal for signal <$n0181> created at line 156.
    Found 10-bit comparator less for signal <$n0182> created at line 156.
    Found 3-bit comparator greater for signal <$n0183> created at line 159.
    Found 10-bit comparator greater for signal <$n0184> created at line 159.
    Found 3-bit comparator less for signal <$n0185> created at line 162.
    Found 3-bit comparator equal for signal <$n0186> created at line 162.
    Found 10-bit comparator less for signal <$n0187> created at line 162.
    Found 3-bit comparator greater for signal <$n0188> created at line 165.
    Found 10-bit comparator greater for signal <$n0189> created at line 165.
    Found 3-bit comparator less for signal <$n0190> created at line 168.
    Found 3-bit comparator equal for signal <$n0191> created at line 168.
    Found 10-bit comparator less for signal <$n0192> created at line 168.
    Found 3-bit comparator less for signal <$n0193> created at line 150.
    Found 3-bit comparator equal for signal <$n0194> created at line 150.
    Found 10-bit comparator less for signal <$n0195> created at line 150.
    Found 3-bit comparator greater for signal <$n0196> created at line 153.
    Found 10-bit comparator greater for signal <$n0197> created at line 153.
    Found 3-bit comparator less for signal <$n0198> created at line 156.
    Found 3-bit comparator equal for signal <$n0199> created at line 156.
    Found 10-bit comparator less for signal <$n0200> created at line 156.
    Found 3-bit comparator greater for signal <$n0201> created at line 159.
    Found 10-bit comparator greater for signal <$n0202> created at line 159.
    Found 3-bit comparator less for signal <$n0203> created at line 162.
    Found 3-bit comparator equal for signal <$n0204> created at line 162.
    Found 10-bit comparator less for signal <$n0205> created at line 162.
    Found 3-bit comparator greater for signal <$n0206> created at line 165.
    Found 10-bit comparator greater for signal <$n0207> created at line 165.
    Found 3-bit comparator less for signal <$n0208> created at line 168.
    Found 3-bit comparator equal for signal <$n0209> created at line 168.
    Found 10-bit comparator less for signal <$n0210> created at line 168.
    Found 3-bit comparator less for signal <$n0211> created at line 150.
    Found 3-bit comparator equal for signal <$n0212> created at line 150.
    Found 10-bit comparator less for signal <$n0213> created at line 150.
    Found 3-bit comparator greater for signal <$n0214> created at line 153.
    Found 10-bit comparator greater for signal <$n0215> created at line 153.
    Found 3-bit comparator less for signal <$n0216> created at line 156.
    Found 3-bit comparator equal for signal <$n0217> created at line 156.
    Found 10-bit comparator less for signal <$n0218> created at line 156.
    Found 3-bit comparator greater for signal <$n0219> created at line 159.
    Found 10-bit comparator greater for signal <$n0220> created at line 159.
    Found 3-bit comparator less for signal <$n0221> created at line 162.
    Found 3-bit comparator equal for signal <$n0222> created at line 162.
    Found 10-bit comparator less for signal <$n0223> created at line 162.
    Found 3-bit comparator greater for signal <$n0224> created at line 165.
    Found 10-bit comparator greater for signal <$n0225> created at line 165.
    Found 3-bit comparator less for signal <$n0226> created at line 168.
    Found 3-bit comparator equal for signal <$n0227> created at line 168.
    Found 10-bit comparator less for signal <$n0228> created at line 168.
    Found 7-bit subtractor for signal <asa_minus>.
    Found 3-bit adder for signal <num_possible_match>.
    Found 10-bit subtractor for signal <ysa_minus>.
    Found 10-bit adder for signal <ysa_plus>.
    Found 10-bit subtractor for signal <ysb_minus>.
    Found 10-bit adder for signal <ysb_plus>.
    Found 36 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  20 Adder/Subtracter(s).
	inferred 111 Comparator(s).
	inferred  36 Multiplexer(s).
Unit <matching_logic57> synthesized.


Synthesizing Unit <matching_logic56>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd.
WARNING:Xst:646 - Signal <ab<2>> is assigned but never used.
WARNING:Xst:646 - Signal <tinc<2>> is assigned but never used.
WARNING:Xst:646 - Signal <num_possible_match<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_a_ll_b<2>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_b_ll_b<2>> is assigned but never used.
    Found 3-bit adder for signal <$n0003> created at line 193.
    Found 6-bit adder for signal <$n0038> created at line 129.
    Found 7-bit comparator less for signal <$n0046> created at line 172.
    Found 7-bit comparator greater for signal <$n0047> created at line 173.
    Found 7-bit comparator less for signal <$n0048> created at line 174.
    Found 7-bit comparator greater for signal <$n0049> created at line 175.
    Found 7-bit comparator less for signal <$n0057> created at line 172.
    Found 7-bit comparator greater for signal <$n0058> created at line 173.
    Found 7-bit comparator less for signal <$n0059> created at line 174.
    Found 7-bit comparator greater for signal <$n0060> created at line 175.
    Found 7-bit comparator less for signal <$n0068> created at line 172.
    Found 7-bit comparator greater for signal <$n0069> created at line 173.
    Found 7-bit comparator less for signal <$n0070> created at line 174.
    Found 7-bit comparator greater for signal <$n0071> created at line 175.
    Found 7-bit comparator less for signal <$n0079> created at line 172.
    Found 7-bit comparator greater for signal <$n0080> created at line 173.
    Found 7-bit comparator less for signal <$n0081> created at line 174.
    Found 7-bit comparator greater for signal <$n0082> created at line 175.
    Found 7-bit comparator less for signal <$n0090> created at line 172.
    Found 7-bit comparator greater for signal <$n0091> created at line 173.
    Found 7-bit comparator less for signal <$n0092> created at line 174.
    Found 7-bit comparator greater for signal <$n0093> created at line 175.
    Found 3-bit adder for signal <$n0094> created at line 194.
    Found 3-bit adder for signal <$n0096> created at line 206.
    Found 3-bit adder for signal <$n0097> created at line 218.
    Found 3-bit comparator greatequal for signal <$n0100> created at line 238.
    Found 3-bit adder for signal <$n0102> created at line 194.
    Found 3-bit adder for signal <$n0103> created at line 194.
    Found 3-bit adder for signal <$n0104> created at line 194.
    Found 3-bit adder for signal <$n0106> created at line 206.
    Found 3-bit adder for signal <$n0108> created at line 206.
    Found 3-bit adder for signal <$n0110> created at line 206.
    Found 3-bit adder for signal <$n0111> created at line 218.
    Found 3-bit adder for signal <$n0112> created at line 218.
    Found 3-bit adder for signal <$n0113> created at line 218.
    Found 3-bit comparator less for signal <$n0139> created at line 150.
    Found 3-bit comparator equal for signal <$n0140> created at line 150.
    Found 10-bit comparator less for signal <$n0141> created at line 150.
    Found 3-bit comparator greater for signal <$n0142> created at line 153.
    Found 10-bit comparator greater for signal <$n0143> created at line 153.
    Found 3-bit comparator less for signal <$n0144> created at line 156.
    Found 3-bit comparator equal for signal <$n0145> created at line 156.
    Found 10-bit comparator less for signal <$n0146> created at line 156.
    Found 3-bit comparator greater for signal <$n0147> created at line 159.
    Found 10-bit comparator greater for signal <$n0148> created at line 159.
    Found 3-bit comparator less for signal <$n0149> created at line 162.
    Found 3-bit comparator equal for signal <$n0150> created at line 162.
    Found 10-bit comparator less for signal <$n0151> created at line 162.
    Found 3-bit comparator greater for signal <$n0152> created at line 165.
    Found 10-bit comparator greater for signal <$n0153> created at line 165.
    Found 3-bit comparator less for signal <$n0154> created at line 168.
    Found 3-bit comparator equal for signal <$n0155> created at line 168.
    Found 10-bit comparator less for signal <$n0156> created at line 168.
    Found 3-bit comparator less for signal <$n0157> created at line 150.
    Found 3-bit comparator equal for signal <$n0158> created at line 150.
    Found 10-bit comparator less for signal <$n0159> created at line 150.
    Found 3-bit comparator greater for signal <$n0160> created at line 153.
    Found 10-bit comparator greater for signal <$n0161> created at line 153.
    Found 3-bit comparator less for signal <$n0162> created at line 156.
    Found 3-bit comparator equal for signal <$n0163> created at line 156.
    Found 10-bit comparator less for signal <$n0164> created at line 156.
    Found 3-bit comparator greater for signal <$n0165> created at line 159.
    Found 10-bit comparator greater for signal <$n0166> created at line 159.
    Found 3-bit comparator less for signal <$n0167> created at line 162.
    Found 3-bit comparator equal for signal <$n0168> created at line 162.
    Found 10-bit comparator less for signal <$n0169> created at line 162.
    Found 3-bit comparator greater for signal <$n0170> created at line 165.
    Found 10-bit comparator greater for signal <$n0171> created at line 165.
    Found 3-bit comparator less for signal <$n0172> created at line 168.
    Found 3-bit comparator equal for signal <$n0173> created at line 168.
    Found 10-bit comparator less for signal <$n0174> created at line 168.
    Found 3-bit comparator less for signal <$n0175> created at line 150.
    Found 3-bit comparator equal for signal <$n0176> created at line 150.
    Found 10-bit comparator less for signal <$n0177> created at line 150.
    Found 3-bit comparator greater for signal <$n0178> created at line 153.
    Found 10-bit comparator greater for signal <$n0179> created at line 153.
    Found 3-bit comparator less for signal <$n0180> created at line 156.
    Found 3-bit comparator equal for signal <$n0181> created at line 156.
    Found 10-bit comparator less for signal <$n0182> created at line 156.
    Found 3-bit comparator greater for signal <$n0183> created at line 159.
    Found 10-bit comparator greater for signal <$n0184> created at line 159.
    Found 3-bit comparator less for signal <$n0185> created at line 162.
    Found 3-bit comparator equal for signal <$n0186> created at line 162.
    Found 10-bit comparator less for signal <$n0187> created at line 162.
    Found 3-bit comparator greater for signal <$n0188> created at line 165.
    Found 10-bit comparator greater for signal <$n0189> created at line 165.
    Found 3-bit comparator less for signal <$n0190> created at line 168.
    Found 3-bit comparator equal for signal <$n0191> created at line 168.
    Found 10-bit comparator less for signal <$n0192> created at line 168.
    Found 3-bit comparator less for signal <$n0193> created at line 150.
    Found 3-bit comparator equal for signal <$n0194> created at line 150.
    Found 10-bit comparator less for signal <$n0195> created at line 150.
    Found 3-bit comparator greater for signal <$n0196> created at line 153.
    Found 10-bit comparator greater for signal <$n0197> created at line 153.
    Found 3-bit comparator less for signal <$n0198> created at line 156.
    Found 3-bit comparator equal for signal <$n0199> created at line 156.
    Found 10-bit comparator less for signal <$n0200> created at line 156.
    Found 3-bit comparator greater for signal <$n0201> created at line 159.
    Found 10-bit comparator greater for signal <$n0202> created at line 159.
    Found 3-bit comparator less for signal <$n0203> created at line 162.
    Found 3-bit comparator equal for signal <$n0204> created at line 162.
    Found 10-bit comparator less for signal <$n0205> created at line 162.
    Found 3-bit comparator greater for signal <$n0206> created at line 165.
    Found 10-bit comparator greater for signal <$n0207> created at line 165.
    Found 3-bit comparator less for signal <$n0208> created at line 168.
    Found 3-bit comparator equal for signal <$n0209> created at line 168.
    Found 10-bit comparator less for signal <$n0210> created at line 168.
    Found 3-bit comparator less for signal <$n0211> created at line 150.
    Found 3-bit comparator equal for signal <$n0212> created at line 150.
    Found 10-bit comparator less for signal <$n0213> created at line 150.
    Found 3-bit comparator greater for signal <$n0214> created at line 153.
    Found 10-bit comparator greater for signal <$n0215> created at line 153.
    Found 3-bit comparator less for signal <$n0216> created at line 156.
    Found 3-bit comparator equal for signal <$n0217> created at line 156.
    Found 10-bit comparator less for signal <$n0218> created at line 156.
    Found 3-bit comparator greater for signal <$n0219> created at line 159.
    Found 10-bit comparator greater for signal <$n0220> created at line 159.
    Found 3-bit comparator less for signal <$n0221> created at line 162.
    Found 3-bit comparator equal for signal <$n0222> created at line 162.
    Found 10-bit comparator less for signal <$n0223> created at line 162.
    Found 3-bit comparator greater for signal <$n0224> created at line 165.
    Found 10-bit comparator greater for signal <$n0225> created at line 165.
    Found 3-bit comparator less for signal <$n0226> created at line 168.
    Found 3-bit comparator equal for signal <$n0227> created at line 168.
    Found 10-bit comparator less for signal <$n0228> created at line 168.
    Found 7-bit subtractor for signal <asa_minus>.
    Found 3-bit adder for signal <num_possible_match>.
    Found 10-bit subtractor for signal <ysa_minus>.
    Found 10-bit adder for signal <ysa_plus>.
    Found 10-bit subtractor for signal <ysb_minus>.
    Found 10-bit adder for signal <ysb_plus>.
    Found 36 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  20 Adder/Subtracter(s).
	inferred 111 Comparator(s).
	inferred  36 Multiplexer(s).
Unit <matching_logic56> synthesized.


Synthesizing Unit <matching_logic>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd.
WARNING:Xst:646 - Signal <ab<3>> is assigned but never used.
WARNING:Xst:646 - Signal <tinc<3>> is assigned but never used.
WARNING:Xst:646 - Signal <num_possible_match<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_a_ll_b<3>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_b_ll_b<3>> is assigned but never used.
    Found 3-bit adder for signal <$n0002> created at line 193.
    Found 6-bit adder for signal <$n0038> created at line 129.
    Found 7-bit comparator less for signal <$n0046> created at line 172.
    Found 7-bit comparator greater for signal <$n0047> created at line 173.
    Found 7-bit comparator less for signal <$n0048> created at line 174.
    Found 7-bit comparator greater for signal <$n0049> created at line 175.
    Found 7-bit comparator less for signal <$n0057> created at line 172.
    Found 7-bit comparator greater for signal <$n0058> created at line 173.
    Found 7-bit comparator less for signal <$n0059> created at line 174.
    Found 7-bit comparator greater for signal <$n0060> created at line 175.
    Found 7-bit comparator less for signal <$n0068> created at line 172.
    Found 7-bit comparator greater for signal <$n0069> created at line 173.
    Found 7-bit comparator less for signal <$n0070> created at line 174.
    Found 7-bit comparator greater for signal <$n0071> created at line 175.
    Found 7-bit comparator less for signal <$n0079> created at line 172.
    Found 7-bit comparator greater for signal <$n0080> created at line 173.
    Found 7-bit comparator less for signal <$n0081> created at line 174.
    Found 7-bit comparator greater for signal <$n0082> created at line 175.
    Found 7-bit comparator less for signal <$n0090> created at line 172.
    Found 7-bit comparator greater for signal <$n0091> created at line 173.
    Found 7-bit comparator less for signal <$n0092> created at line 174.
    Found 7-bit comparator greater for signal <$n0093> created at line 175.
    Found 3-bit adder for signal <$n0094> created at line 194.
    Found 3-bit adder for signal <$n0096> created at line 206.
    Found 3-bit adder for signal <$n0097> created at line 218.
    Found 3-bit comparator greatequal for signal <$n0100> created at line 238.
    Found 3-bit adder for signal <$n0102> created at line 194.
    Found 3-bit adder for signal <$n0103> created at line 194.
    Found 3-bit adder for signal <$n0104> created at line 194.
    Found 3-bit adder for signal <$n0106> created at line 206.
    Found 3-bit adder for signal <$n0108> created at line 206.
    Found 3-bit adder for signal <$n0110> created at line 206.
    Found 3-bit adder for signal <$n0111> created at line 218.
    Found 3-bit adder for signal <$n0112> created at line 218.
    Found 3-bit adder for signal <$n0113> created at line 218.
    Found 3-bit comparator less for signal <$n0139> created at line 150.
    Found 3-bit comparator equal for signal <$n0140> created at line 150.
    Found 10-bit comparator less for signal <$n0141> created at line 150.
    Found 3-bit comparator greater for signal <$n0142> created at line 153.
    Found 10-bit comparator greater for signal <$n0143> created at line 153.
    Found 3-bit comparator less for signal <$n0144> created at line 156.
    Found 3-bit comparator equal for signal <$n0145> created at line 156.
    Found 10-bit comparator less for signal <$n0146> created at line 156.
    Found 3-bit comparator greater for signal <$n0147> created at line 159.
    Found 10-bit comparator greater for signal <$n0148> created at line 159.
    Found 3-bit comparator less for signal <$n0149> created at line 162.
    Found 3-bit comparator equal for signal <$n0150> created at line 162.
    Found 10-bit comparator less for signal <$n0151> created at line 162.
    Found 3-bit comparator greater for signal <$n0152> created at line 165.
    Found 10-bit comparator greater for signal <$n0153> created at line 165.
    Found 3-bit comparator less for signal <$n0154> created at line 168.
    Found 3-bit comparator equal for signal <$n0155> created at line 168.
    Found 10-bit comparator less for signal <$n0156> created at line 168.
    Found 3-bit comparator less for signal <$n0157> created at line 150.
    Found 3-bit comparator equal for signal <$n0158> created at line 150.
    Found 10-bit comparator less for signal <$n0159> created at line 150.
    Found 3-bit comparator greater for signal <$n0160> created at line 153.
    Found 10-bit comparator greater for signal <$n0161> created at line 153.
    Found 3-bit comparator less for signal <$n0162> created at line 156.
    Found 3-bit comparator equal for signal <$n0163> created at line 156.
    Found 10-bit comparator less for signal <$n0164> created at line 156.
    Found 3-bit comparator greater for signal <$n0165> created at line 159.
    Found 10-bit comparator greater for signal <$n0166> created at line 159.
    Found 3-bit comparator less for signal <$n0167> created at line 162.
    Found 3-bit comparator equal for signal <$n0168> created at line 162.
    Found 10-bit comparator less for signal <$n0169> created at line 162.
    Found 3-bit comparator greater for signal <$n0170> created at line 165.
    Found 10-bit comparator greater for signal <$n0171> created at line 165.
    Found 3-bit comparator less for signal <$n0172> created at line 168.
    Found 3-bit comparator equal for signal <$n0173> created at line 168.
    Found 10-bit comparator less for signal <$n0174> created at line 168.
    Found 3-bit comparator less for signal <$n0175> created at line 150.
    Found 3-bit comparator equal for signal <$n0176> created at line 150.
    Found 10-bit comparator less for signal <$n0177> created at line 150.
    Found 3-bit comparator greater for signal <$n0178> created at line 153.
    Found 10-bit comparator greater for signal <$n0179> created at line 153.
    Found 3-bit comparator less for signal <$n0180> created at line 156.
    Found 3-bit comparator equal for signal <$n0181> created at line 156.
    Found 10-bit comparator less for signal <$n0182> created at line 156.
    Found 3-bit comparator greater for signal <$n0183> created at line 159.
    Found 10-bit comparator greater for signal <$n0184> created at line 159.
    Found 3-bit comparator less for signal <$n0185> created at line 162.
    Found 3-bit comparator equal for signal <$n0186> created at line 162.
    Found 10-bit comparator less for signal <$n0187> created at line 162.
    Found 3-bit comparator greater for signal <$n0188> created at line 165.
    Found 10-bit comparator greater for signal <$n0189> created at line 165.
    Found 3-bit comparator less for signal <$n0190> created at line 168.
    Found 3-bit comparator equal for signal <$n0191> created at line 168.
    Found 10-bit comparator less for signal <$n0192> created at line 168.
    Found 3-bit comparator less for signal <$n0193> created at line 150.
    Found 3-bit comparator equal for signal <$n0194> created at line 150.
    Found 10-bit comparator less for signal <$n0195> created at line 150.
    Found 3-bit comparator greater for signal <$n0196> created at line 153.
    Found 10-bit comparator greater for signal <$n0197> created at line 153.
    Found 3-bit comparator less for signal <$n0198> created at line 156.
    Found 3-bit comparator equal for signal <$n0199> created at line 156.
    Found 10-bit comparator less for signal <$n0200> created at line 156.
    Found 3-bit comparator greater for signal <$n0201> created at line 159.
    Found 10-bit comparator greater for signal <$n0202> created at line 159.
    Found 3-bit comparator less for signal <$n0203> created at line 162.
    Found 3-bit comparator equal for signal <$n0204> created at line 162.
    Found 10-bit comparator less for signal <$n0205> created at line 162.
    Found 3-bit comparator greater for signal <$n0206> created at line 165.
    Found 10-bit comparator greater for signal <$n0207> created at line 165.
    Found 3-bit comparator less for signal <$n0208> created at line 168.
    Found 3-bit comparator equal for signal <$n0209> created at line 168.
    Found 10-bit comparator less for signal <$n0210> created at line 168.
    Found 3-bit comparator less for signal <$n0211> created at line 150.
    Found 3-bit comparator equal for signal <$n0212> created at line 150.
    Found 10-bit comparator less for signal <$n0213> created at line 150.
    Found 3-bit comparator greater for signal <$n0214> created at line 153.
    Found 10-bit comparator greater for signal <$n0215> created at line 153.
    Found 3-bit comparator less for signal <$n0216> created at line 156.
    Found 3-bit comparator equal for signal <$n0217> created at line 156.
    Found 10-bit comparator less for signal <$n0218> created at line 156.
    Found 3-bit comparator greater for signal <$n0219> created at line 159.
    Found 10-bit comparator greater for signal <$n0220> created at line 159.
    Found 3-bit comparator less for signal <$n0221> created at line 162.
    Found 3-bit comparator equal for signal <$n0222> created at line 162.
    Found 10-bit comparator less for signal <$n0223> created at line 162.
    Found 3-bit comparator greater for signal <$n0224> created at line 165.
    Found 10-bit comparator greater for signal <$n0225> created at line 165.
    Found 3-bit comparator less for signal <$n0226> created at line 168.
    Found 3-bit comparator equal for signal <$n0227> created at line 168.
    Found 10-bit comparator less for signal <$n0228> created at line 168.
    Found 7-bit subtractor for signal <asa_minus>.
    Found 3-bit adder for signal <num_possible_match>.
    Found 10-bit subtractor for signal <ysa_minus>.
    Found 10-bit adder for signal <ysa_plus>.
    Found 10-bit subtractor for signal <ysb_minus>.
    Found 10-bit adder for signal <ysb_plus>.
    Found 36 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  20 Adder/Subtracter(s).
	inferred 111 Comparator(s).
	inferred  36 Multiplexer(s).
Unit <matching_logic> synthesized.


Synthesizing Unit <matching_memory>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_memory.vhd.
    Found 64x26-bit dual-port distributed RAM for signal <ram_block_a>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 26-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr2_in>      |          |
    | dual address       | connected to signal <reg_a>         |          |
    | data in            | connected to signal <ram_in>        |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <ram_a_out>     |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 64x26-bit dual-port distributed RAM for signal <ram_block_b>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 26-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr2_in>      |          |
    | dual address       | connected to signal <reg_b>         |          |
    | data in            | connected to signal <ram_in>        |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <ram_b_out>     |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 5-bit adder for signal <$n0039> created at line 147.
    Found 5-bit adder for signal <$n0040> created at line 148.
    Found 6-bit comparator not equal for signal <$n0048> created at line 186.
    Found 6-bit comparator equal for signal <$n0049> created at line 190.
    Found 1-bit register for signal <invalid_reg>.
    Found 6-bit register for signal <reg_a>.
    Found 6-bit register for signal <reg_b>.
    Found 6-bit register for signal <reg_last>.
    Found 6 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 RAM(s).
	inferred  19 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   2 Comparator(s).
	inferred   6 Multiplexer(s).
Unit <matching_memory> synthesized.


Synthesizing Unit <zch_table55>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table55> synthesized.


Synthesizing Unit <zch_table54>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table54> synthesized.


Synthesizing Unit <zch_table53>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table53> synthesized.


Synthesizing Unit <zch_table52>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table52> synthesized.


Synthesizing Unit <zch_table51>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table51> synthesized.


Synthesizing Unit <zch_table50>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table50> synthesized.


Synthesizing Unit <zch_table49>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table49> synthesized.


Synthesizing Unit <zch_table48>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table48> synthesized.


Synthesizing Unit <zch_table47>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table47> synthesized.


Synthesizing Unit <zch_table46>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table46> synthesized.


Synthesizing Unit <zch_table45>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table45> synthesized.


Synthesizing Unit <zch_table44>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table44> synthesized.


Synthesizing Unit <zch_table43>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table43> synthesized.


Synthesizing Unit <zch_table42>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table42> synthesized.


Synthesizing Unit <zch_table41>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table41> synthesized.


Synthesizing Unit <zch_table40>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table40> synthesized.


Synthesizing Unit <zch_table39>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table39> synthesized.


Synthesizing Unit <sorter>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd.
    Found 10-bit 4-to-1 multiplexer for signal <$n0043>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0044>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0045>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0046>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0047>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0048>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0049>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0051>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0052>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0053>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0054>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0055>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0056>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0057>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0058>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0059>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0060>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0061>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0062>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0063>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0064>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0065>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0066>.
    Found 10-bit comparator lessequal for signal <$n0080> created at line 129.
    Found 3-bit comparator equal for signal <$n0081> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0083> created at line 129.
    Found 3-bit comparator equal for signal <$n0084> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0086> created at line 129.
    Found 3-bit comparator equal for signal <$n0087> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0089> created at line 129.
    Found 3-bit comparator equal for signal <$n0090> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0092> created at line 129.
    Found 3-bit comparator equal for signal <$n0093> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0095> created at line 129.
    Found 3-bit comparator equal for signal <$n0096> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0098> created at line 129.
    Found 3-bit comparator equal for signal <$n0099> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0101> created at line 129.
    Found 3-bit comparator equal for signal <$n0102> created at line 129.
    Found 48-bit register for signal <addr<8:1>>.
    Found 24-bit register for signal <idx<8:1>>.
    Found 3-bit register for signal <last_idx_in>.
    Found 80-bit register for signal <y<8:1>>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred  16 Comparator(s).
	inferred 152 Multiplexer(s).
Unit <sorter> synthesized.


Synthesizing Unit <zch_table>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table> synthesized.


Synthesizing Unit <yt_lut38>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 80x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut38> synthesized.


Synthesizing Unit <proj_y37>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y37> synthesized.


Synthesizing Unit <proj_d36>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d36> synthesized.


Synthesizing Unit <yt_lut35>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 80x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut35> synthesized.


Synthesizing Unit <proj_y34>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y34> synthesized.


Synthesizing Unit <proj_d33>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d33> synthesized.


Synthesizing Unit <yt_lut32>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 80x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut32> synthesized.


Synthesizing Unit <proj_y31>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y31> synthesized.


Synthesizing Unit <proj_d30>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d30> synthesized.


Synthesizing Unit <yt_lut29>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 80x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut29> synthesized.


Synthesizing Unit <proj_y28>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y28> synthesized.


Synthesizing Unit <proj_d27>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d27> synthesized.


Synthesizing Unit <yt_lut26>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 78x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut26> synthesized.


Synthesizing Unit <proj_y25>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y25> synthesized.


Synthesizing Unit <proj_d24>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d24> synthesized.


Synthesizing Unit <fifo_dc_wrapper>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd.
Unit <fifo_dc_wrapper> synthesized.


Synthesizing Unit <yt_lut>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 77x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut> synthesized.


Synthesizing Unit <proj_y>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y> synthesized.


Synthesizing Unit <proj_d>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d> synthesized.


Synthesizing Unit <buffer_merger>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd.
    Found 4-bit comparator less for signal <$n0030> created at line 173.
    Found 1-bit register for signal <state<0>>.
    Found 2-bit register for signal <valid>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <buffer_merger> synthesized.


Synthesizing Unit <inputcontrol>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 3                                              |
    | Outputs            | 2                                              |
    | Clock              | clk_in (rising_edge)                           |
    | Reset              | rst_n (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <d_out_reg>.
    Found 8-bit register for signal <i_hi>.
    Found 8-bit register for signal <i_lo>.
    Found 1-bit register for signal <i_valid>.
    Found 16-bit register for signal <stage_a>.
    Found 1-bit register for signal <stage_a_end>.
    Found 16-bit register for signal <stage_b>.
    Found 1-bit register for signal <valid_out_reg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  83 D-type flip-flop(s).
Unit <inputcontrol> synthesized.


Synthesizing Unit <reconst>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/reconst.vhd.
WARNING:Xst:646 - Signal <pt_ext_comb4<0>> is assigned but never used.
WARNING:Xst:646 - Signal <pid_stage1a> is assigned but never used.
WARNING:Xst:646 - Signal <pt_raw_stage4<20:17>> is assigned but never used.
WARNING:Xst:646 - Signal <a_ext_comb2<1:0>> is assigned but never used.
INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal <ready_sreg<7>> and currently occupies 7 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal <valid_sreg<7>> and currently occupies 7 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <ready_stage4> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <valid_stage4> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 7-bit shift register for signal <track_sreg<7><41>>.
    Found 7-bit shift register for signal <track_sreg<7><40>>.
    Found 7-bit shift register for signal <track_sreg<7><39>>.
    Found 7-bit shift register for signal <track_sreg<7><38>>.
    Found 7-bit shift register for signal <track_sreg<7><37>>.
    Found 7-bit shift register for signal <track_sreg<7><36>>.
    Found 7-bit shift register for signal <track_sreg<7><35>>.
    Found 7-bit shift register for signal <track_sreg<7><34>>.
    Found 7-bit shift register for signal <track_sreg<7><33>>.
    Found 7-bit shift register for signal <track_sreg<7><32>>.
    Found 7-bit shift register for signal <track_sreg<7><31>>.
    Found 7-bit shift register for signal <track_sreg<7><30>>.
    Found 7-bit shift register for signal <track_sreg<7><29>>.
    Found 7-bit shift register for signal <track_sreg<7><28>>.
    Found 7-bit shift register for signal <track_sreg<7><27>>.
    Found 7-bit shift register for signal <track_sreg<7><26>>.
    Found 7-bit shift register for signal <track_sreg<7><25>>.
    Found 7-bit shift register for signal <track_sreg<7><24>>.
    Found 7-bit shift register for signal <track_sreg<7><23>>.
    Found 7-bit shift register for signal <track_sreg<7><22>>.
    Found 7-bit shift register for signal <track_sreg<7><21>>.
    Found 7-bit shift register for signal <track_sreg<7><20>>.
    Found 7-bit shift register for signal <track_sreg<7><19>>.
    Found 7-bit shift register for signal <track_sreg<7><18>>.
    Found 7-bit shift register for signal <track_sreg<7><17>>.
    Found 7-bit shift register for signal <track_sreg<7><16>>.
    Found 7-bit shift register for signal <track_sreg<7><15>>.
    Found 7-bit shift register for signal <track_sreg<7><14>>.
    Found 7-bit shift register for signal <track_sreg<7><13>>.
    Found 7-bit shift register for signal <track_sreg<7><12>>.
    Found 7-bit shift register for signal <track_sreg<7><11>>.
    Found 7-bit shift register for signal <track_sreg<7><10>>.
    Found 7-bit shift register for signal <track_sreg<7><9>>.
    Found 7-bit shift register for signal <track_sreg<7><8>>.
    Found 7-bit shift register for signal <track_sreg<7><7>>.
    Found 7-bit shift register for signal <track_sreg<7><6>>.
    Found 7-bit shift register for signal <track_sreg<7><5>>.
    Found 7-bit shift register for signal <track_sreg<7><4>>.
    Found 7-bit shift register for signal <track_sreg<7><3>>.
    Found 7-bit shift register for signal <track_sreg<7><2>>.
    Found 7-bit shift register for signal <track_sreg<7><1>>.
    Found 7-bit shift register for signal <track_sreg<7><0>>.
    Found 12-bit adder for signal <$n0000> created at line 206.
    Found 18-bit adder for signal <$n0001> created at line 198.
    Found 17-bit subtractor for signal <$n0002> created at line 206.
    Found 18-bit adder for signal <$n0004>.
    Found 18-bit adder for signal <$n0005>.
    Found 18-bit adder for signal <$n0006>.
    Found 18-bit adder for signal <$n0007>.
    Found 18-bit adder for signal <a_full_comb2>.
    Found 16-bit register for signal <a_stage3>.
    Found 78-bit register for signal <acoeff_stage1a>.
    Found 108-bit register for signal <ai_stage2>.
    Found 13-bit register for signal <c1_stage3>.
    Found 3-bit shift register for signal <mask_id_stage2>.
    Found 21-bit register for signal <pt_raw_stage4>.
    Found 7-bit register for signal <ready_sreg<7:1>>.
    Found 1-bit register for signal <ready_stage0>.
    Found 1-bit register for signal <ready_stage1a>.
    Found 1-bit register for signal <ready_stage1b>.
    Found 1-bit register for signal <ready_stage2>.
    Found 1-bit register for signal <ready_stage3>.
    Found 1-bit register for signal <ready_stage4>.
    Found 42-bit register for signal <track_stage0>.
    Found 5-bit shift register for signal <track_stage4>.
    Found 7-bit register for signal <valid_sreg<7:1>>.
    Found 1-bit register for signal <valid_stage0>.
    Found 1-bit register for signal <valid_stage1a>.
    Found 1-bit register for signal <valid_stage1b>.
    Found 1-bit register for signal <valid_stage2>.
    Found 1-bit register for signal <valid_stage3>.
    Found 1-bit register for signal <valid_stage4>.
    Found 78-bit register for signal <ys_stage1a>.
    Found 35 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 382 D-type flip-flop(s).
	inferred   8 Adder/Subtracter(s).
	inferred  35 Multiplexer(s).
	inferred  89 Shift register(s).
Unit <reconst> synthesized.


Synthesizing Unit <unique>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/unique.vhd.
Unit <unique> synthesized.


Synthesizing Unit <match23>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd.
    Found 1-bit register for signal <all_ready>.
    Found 10 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <match23> synthesized.


Synthesizing Unit <match22>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd.
    Found 1-bit register for signal <all_ready>.
    Found 10 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <match22> synthesized.


Synthesizing Unit <match>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd.
    Found 1-bit register for signal <all_ready>.
    Found 10 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <match> synthesized.


Synthesizing Unit <z_channel21>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel21> synthesized.


Synthesizing Unit <z_channel20>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel20> synthesized.


Synthesizing Unit <z_channel19>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel19> synthesized.


Synthesizing Unit <z_channel18>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel18> synthesized.


Synthesizing Unit <z_channel17>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel17> synthesized.


Synthesizing Unit <z_channel16>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel16> synthesized.


Synthesizing Unit <z_channel15>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel15> synthesized.


Synthesizing Unit <z_channel14>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel14> synthesized.


Synthesizing Unit <z_channel13>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel13> synthesized.


Synthesizing Unit <z_channel12>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel12> synthesized.


Synthesizing Unit <z_channel11>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel11> synthesized.


Synthesizing Unit <z_channel10>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel10> synthesized.


Synthesizing Unit <z_channel9>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel9> synthesized.


Synthesizing Unit <z_channel8>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel8> synthesized.


Synthesizing Unit <z_channel7>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel7> synthesized.


Synthesizing Unit <z_channel6>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel6> synthesized.


Synthesizing Unit <z_channel5>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel5> synthesized.


Synthesizing Unit <z_channel>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel> synthesized.


Synthesizing Unit <input4>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input4> synthesized.


Synthesizing Unit <input3>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input3> synthesized.


Synthesizing Unit <input2>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input2> synthesized.


Synthesizing Unit <input1>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input1> synthesized.


Synthesizing Unit <input0>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input0> synthesized.


Synthesizing Unit <input>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input> synthesized.


Synthesizing Unit <toplevel>.
    Related source file is /electra/cuveland/vhdl/gtu/syn_ise/../src/toplevel.vhd.
Unit <toplevel> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# LUT RAMs                         : 146
 64x21-bit dual-port distributed RAM: 6
 64x7-bit dual-port distributed RAM: 18
 64x26-bit dual-port distributed RAM: 108
 8x52-bit dual-port distributed RAM: 12
 16x52-bit dual-port distributed RAM: 2
# ROMs                             : 13
 77x11-bit ROM                     : 1
 78x11-bit ROM                     : 1
 80x11-bit ROM                     : 4
 22x13-bit ROM                     : 7
# Multipliers                      : 15
 9x9-bit multiplier                : 6
 7x8-bit multiplier                : 6
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 405
 17-bit subtractor                 : 1
 18-bit adder                      : 6
 12-bit adder                      : 1
 8-bit subtractor                  : 6
 8-bit adder                       : 6
 11-bit adder                      : 6
 13-bit adder                      : 12
 6-bit adder                       : 13
 7-bit subtractor                  : 9
 10-bit subtractor                 : 18
 10-bit adder                      : 18
 33-bit adder                      : 10
 32-bit adder                      : 30
 19-bit adder                      : 6
 1-bit adder carry out             : 10
 5-bit adder                       : 109
 3-bit adder                       : 127
 4-bit subtractor                  : 3
 4-bit adder                       : 4
 2-bit adder                       : 10
# Counters                         : 52
 6-bit up counter                  : 24
 3-bit up counter                  : 24
 4-bit up counter                  : 4
# Registers                        : 955
 6-bit register                    : 312
 4-bit register                    : 8
 7-bit register                    : 6
 10-bit register                   : 150
 1-bit register                    : 201
 21-bit register                   : 1
 16-bit register                   : 25
 18-bit register                   : 6
 13-bit register                   : 13
 32-bit register                   : 12
 8-bit register                    : 24
 2-bit register                    : 6
 3-bit register                    : 174
 42-bit register                   : 11
 19-bit register                   : 6
# Shift Registers                  : 89
 3-bit shift register              : 5
 5-bit shift register              : 42
 7-bit shift register              : 42
# Comparators                      : 1489
 10-bit comparator lessequal       : 144
 6-bit comparator not equal        : 54
 10-bit comparator greater         : 135
 3-bit comparator greater          : 135
 10-bit comparator less            : 180
 3-bit comparator greatequal       : 9
 7-bit comparator greater          : 90
 4-bit comparator equal            : 3
 4-bit comparator less             : 9
 3-bit comparator not equal        : 12
 7-bit comparator less             : 103
 3-bit comparator equal            : 334
 3-bit comparator less             : 190
 4-bit comparator not equal        : 2
 6-bit comparator equal            : 84
 32-bit comparator greatequal      : 5
# Multiplexers                     : 665
 7-bit 2-to-1 multiplexer          : 9
 3-bit 2-to-1 multiplexer          : 117
 17-bit 2-to-1 multiplexer         : 1
 18-bit 2-to-1 multiplexer         : 1
 6-bit 4-to-1 multiplexer          : 144
 3-bit 4-to-1 multiplexer          : 144
 10-bit 4-to-1 multiplexer         : 144
 6-bit 2-to-1 multiplexer          : 54
 33-bit 2-to-1 multiplexer         : 20
 32-bit 2-to-1 multiplexer         : 30
 42-bit 2-to-1 multiplexer         : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "cg_fifo_dc.edn" "cg_fifo_dc.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "cg_fifo_dc.ngo"...
Launcher: Executing edif2ngd -noa "cg_divide.edn" "cg_divide.ngo"
INFO:NgdBuild - Release 6.2i - edif2ngd G.28
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "cg_divide.ngo"...
Loading core <cg_fifo_dc> for timing and area information for instance <fifo_dc_inst>.
Loading core <cg_divide> for timing and area information for instance <divide_inst>.
WARNING:Xst:1291 - FF/Latch <pt_raw_stage4_20> is unconnected in block <reconst>.
WARNING:Xst:1291 - FF/Latch <pt_raw_stage4_17> is unconnected in block <reconst>.
WARNING:Xst:1291 - FF/Latch <pt_raw_stage4_18> is unconnected in block <reconst>.
WARNING:Xst:1291 - FF/Latch <pt_raw_stage4_19> is unconnected in block <reconst>.

Process interrupted by the user.
ERROR: XST failed
WARNING: Unable to make process Check Syntax out of date
Reason: error deleting "toplevel.stx": I/O error
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/TOPLEVEL is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/toplevel.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/toplevel.vhd
WARNING:HDLParsers:3215 - Unit work/TOPLEVEL/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/toplevel.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/toplevel.vhd
WARNING:HDLParsers:3215 - Unit work/RECONST is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/reconst.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/reconst.vhd
WARNING:HDLParsers:3215 - Unit work/RECONST/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/reconst.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/reconst.vhd
WARNING:HDLParsers:3215 - Unit work/DIVIDE_WRAPPER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd
WARNING:HDLParsers:3215 - Unit work/DIVIDE_WRAPPER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd
WARNING:HDLParsers:3481 - No primary, secondary unit in the file /home/cuveland/nfs/vhdl/gtu/syn_ise/cg_divide.vhd. Ignore this file from project file toplevel_vhdl.prj.
WARNING:HDLParsers:3215 - Unit work/MULT_WRAPPER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd
WARNING:HDLParsers:3215 - Unit work/MULT_WRAPPER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd
WARNING:HDLParsers:3215 - Unit work/UNIQUE is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/unique.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/unique.vhd
WARNING:HDLParsers:3215 - Unit work/UNIQUE/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/unique.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/unique.vhd
WARNING:HDLParsers:3215 - Unit work/ZCH_RESORTER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd
WARNING:HDLParsers:3215 - Unit work/ZCH_RESORTER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_resorter.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd
WARNING:HDLParsers:3215 - Unit work/ZCH_MERGER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd
WARNING:HDLParsers:3215 - Unit work/ZCH_MERGER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd
WARNING:HDLParsers:3215 - Unit work/UNIQUIFIER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd
WARNING:HDLParsers:3215 - Unit work/UNIQUIFIER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/uniquifier.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd
WARNING:HDLParsers:3215 - Unit work/SEED_MERGER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/seed_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/seed_merger.vhd
WARNING:HDLParsers:3215 - Unit work/SEED_MERGER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/seed_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/seed_merger.vhd
WARNING:HDLParsers:3215 - Unit work/MATCH is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd
WARNING:HDLParsers:3215 - Unit work/MATCH/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/match.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd
WARNING:HDLParsers:3215 - Unit work/TRACK_TYPES is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/track_types.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd
WARNING:HDLParsers:3215 - Unit work/MATCHING_LOGIC is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd
WARNING:HDLParsers:3215 - Unit work/MATCHING_LOGIC/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_logic.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd
WARNING:HDLParsers:3215 - Unit work/MATCHING_MEMORY is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_memory.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_memory.vhd
WARNING:HDLParsers:3215 - Unit work/MATCHING_MEMORY/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/matching_memory.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_memory.vhd
WARNING:HDLParsers:3215 - Unit work/Z_CHANNEL is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd
WARNING:HDLParsers:3215 - Unit work/Z_CHANNEL/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/z_channel.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd
WARNING:HDLParsers:3215 - Unit work/SORTER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd
WARNING:HDLParsers:3215 - Unit work/SORTER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/sorter.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd
WARNING:HDLParsers:3215 - Unit work/ZCH_TABLE is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd
WARNING:HDLParsers:3215 - Unit work/ZCH_TABLE/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/zch_table.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd
WARNING:HDLParsers:3215 - Unit work/INPUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd
WARNING:HDLParsers:3215 - Unit work/INPUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/input.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd
WARNING:HDLParsers:3215 - Unit work/MASK_ID_LUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd
WARNING:HDLParsers:3215 - Unit work/MASK_ID_LUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd
WARNING:HDLParsers:3215 - Unit work/YT_LUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd
WARNING:HDLParsers:3215 - Unit work/YT_LUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd
WARNING:HDLParsers:3215 - Unit work/C1_LUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd
WARNING:HDLParsers:3215 - Unit work/C1_LUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd
WARNING:HDLParsers:3215 - Unit work/ACOEFF_LUT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd
WARNING:HDLParsers:3215 - Unit work/ACOEFF_LUT/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/rec_tables.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd
WARNING:HDLParsers:3215 - Unit work/PROJ_Y is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd
WARNING:HDLParsers:3215 - Unit work/PROJ_Y/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_y.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd
WARNING:HDLParsers:3215 - Unit work/PROJ_D is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd
WARNING:HDLParsers:3215 - Unit work/PROJ_D/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/proj_d.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd
WARNING:HDLParsers:3215 - Unit work/BUFFER_MERGER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd
WARNING:HDLParsers:3215 - Unit work/BUFFER_MERGER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/buffer_merger.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd
WARNING:HDLParsers:3215 - Unit work/FIFO_DC_WRAPPER is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd
WARNING:HDLParsers:3215 - Unit work/FIFO_DC_WRAPPER/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd
WARNING:HDLParsers:3481 - No primary, secondary unit in the file /home/cuveland/nfs/vhdl/gtu/syn_ise/cg_fifo_dc.vhd. Ignore this file from project file toplevel_vhdl.prj.
WARNING:HDLParsers:3215 - Unit work/INPUTCONTROL is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/inputcontrol.vhd
WARNING:HDLParsers:3215 - Unit work/INPUTCONTROL/DEFAULT is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/inputcontrol.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/inputcontrol.vhd
WARNING:HDLParsers:3215 - Unit work/GTU_TYPES is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/gtu_types.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd
WARNING:HDLParsers:3215 - Unit work/GTU_TYPES is now defined in a different file: was /electra/cuveland/vhdl/gtu/syn_ise/../src/gtu_types.vhd, now is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd in Library work.
Architecture default of Entity fifo_dc_wrapper is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd in Library work.
Architecture default of Entity mask_id_lut is up to date.
Architecture default of Entity yt_lut is up to date.
Architecture default of Entity c1_lut is up to date.
Architecture default of Entity acoeff_lut is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd in Library work.
Architecture default of Entity mult_wrapper is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd in Library work.
Architecture default of Entity divide_wrapper is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/seed_merger.vhd in Library work.
Architecture default of Entity seed_merger is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd in Library work.
Architecture default of Entity uniquifier is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Architecture default of Entity zch_merger is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd in Library work.
Architecture default of Entity zch_resorter is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_memory.vhd in Library work.
Architecture default of Entity matching_memory is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd in Library work.
Architecture default of Entity matching_logic is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd in Library work.
Architecture default of Entity zch_table is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd in Library work.
Architecture default of Entity sorter is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/inputcontrol.vhd in Library work.
Architecture default of Entity inputcontrol is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd in Library work.
Architecture default of Entity buffer_merger is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd in Library work.
Architecture default of Entity proj_d is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd in Library work.
Architecture default of Entity proj_y is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd in Library work.
Architecture default of Entity input is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd in Library work.
Architecture default of Entity z_channel is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd in Library work.
Architecture default of Entity match is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/unique.vhd in Library work.
Architecture default of Entity unique is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/reconst.vhd in Library work.
Architecture default of Entity reconst is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/toplevel.vhd in Library work.
Architecture default of Entity toplevel is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <toplevel> (Architecture <default>).
Entity <toplevel> analyzed. Unit <toplevel> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 5
Entity <input> analyzed. Unit <input> generated.

Analyzing Entity <inputcontrol> (Architecture <default>).
Entity <inputcontrol> analyzed. Unit <inputcontrol> generated.

Analyzing Entity <buffer_merger> (Architecture <default>).
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd line 148: The following signals are missing in the process sensitivity list:
   data<1><23>, data<1><22>, data<1><21>, data<1><20>, data<0><23>, data<0><22>, data<0><21>, data<0><20>.
Entity <buffer_merger> analyzed. Unit <buffer_merger> generated.

Analyzing Entity <fifo_dc_wrapper> (Architecture <default>).
WARNING:Xst:753 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Unconnected output port 'full' of component 'cg_fifo_dc'.
WARNING:Xst:766 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd line 60: Generating a Black Box for component <cg_fifo_dc>.
Entity <fifo_dc_wrapper> analyzed. Unit <fifo_dc_wrapper> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 5
Entity <proj_d> analyzed. Unit <proj_d> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 5
Entity <proj_y> analyzed. Unit <proj_y> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 5
Entity <yt_lut> analyzed. Unit <yt_lut> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 4
Entity <input> analyzed. Unit <input0> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 4
Entity <proj_d> analyzed. Unit <proj_d24> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 4
Entity <proj_y> analyzed. Unit <proj_y25> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 4
Entity <yt_lut> analyzed. Unit <yt_lut26> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 3
Entity <input> analyzed. Unit <input1> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 3
Entity <proj_d> analyzed. Unit <proj_d27> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 3
Entity <proj_y> analyzed. Unit <proj_y28> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 3
Entity <yt_lut> analyzed. Unit <yt_lut29> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 2
Entity <input> analyzed. Unit <input2> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 2
Entity <proj_d> analyzed. Unit <proj_d30> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 2
Entity <proj_y> analyzed. Unit <proj_y31> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 2
Entity <yt_lut> analyzed. Unit <yt_lut32> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 1
Entity <input> analyzed. Unit <input3> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 1
Entity <proj_d> analyzed. Unit <proj_d33> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 1
Entity <proj_y> analyzed. Unit <proj_y34> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 1
Entity <yt_lut> analyzed. Unit <yt_lut35> generated.

Analyzing generic Entity <input> (Architecture <default>).
	plane = 0
Entity <input> analyzed. Unit <input4> generated.

Analyzing generic Entity <proj_d> (Architecture <default>).
	plane = 0
Entity <proj_d> analyzed. Unit <proj_d36> generated.

Analyzing generic Entity <proj_y> (Architecture <default>).
	plane = 0
Entity <proj_y> analyzed. Unit <proj_y37> generated.

Analyzing generic Entity <yt_lut> (Architecture <default>).
	plane = 0
Entity <yt_lut> analyzed. Unit <yt_lut38> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 5
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 5
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table> generated.

Analyzing generic Entity <sorter> (Architecture <default>).
	depth = 8
Entity <sorter> analyzed. Unit <sorter> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 5
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel5> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 5
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table39> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 5
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel6> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 5
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table40> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 4
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel7> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 4
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table41> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 4
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel8> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 4
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table42> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 4
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel9> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 4
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table43> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 3
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel10> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 3
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table44> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 3
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel11> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 3
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table45> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 3
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel12> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 3
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table46> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 2
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel13> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 2
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table47> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 2
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel14> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 2
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table48> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 2
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel15> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 2
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table49> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 1
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel16> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 1
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table50> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 1
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel17> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 1
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table51> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 1
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel18> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 1
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table52> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 0
	channel_index = 2
Entity <z_channel> analyzed. Unit <z_channel19> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 0
	zunit = 2
Entity <zch_table> analyzed. Unit <zch_table53> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 0
	channel_index = 1
Entity <z_channel> analyzed. Unit <z_channel20> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 0
	zunit = 1
Entity <zch_table> analyzed. Unit <zch_table54> generated.

Analyzing generic Entity <z_channel> (Architecture <default>).
	plane = 0
	channel_index = 0
Entity <z_channel> analyzed. Unit <z_channel21> generated.

Analyzing generic Entity <zch_table> (Architecture <default>).
	plane = 0
	zunit = 0
Entity <zch_table> analyzed. Unit <zch_table55> generated.

Analyzing generic Entity <match> (Architecture <default>).
	seedline = 3
	line_mask = 0
Entity <match> analyzed. Unit <match> generated.

Analyzing Entity <matching_memory> (Architecture <default>).
Entity <matching_memory> analyzed. Unit <matching_memory> generated.

Analyzing generic Entity <matching_logic> (Architecture <default>).
	seedline = 3
	line_mask = 0
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<3><1>, inc<3><0>.
Entity <matching_logic> analyzed. Unit <matching_logic> generated.

Analyzing generic Entity <match> (Architecture <default>).
	seedline = 2
	line_mask = 8
Entity <match> analyzed. Unit <match22> generated.

Analyzing generic Entity <matching_logic> (Architecture <default>).
	seedline = 2
	line_mask = 8
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<2><1>, inc<2><0>.
Entity <matching_logic> analyzed. Unit <matching_logic56> generated.

Analyzing generic Entity <match> (Architecture <default>).
	seedline = 1
	line_mask = 12
Entity <match> analyzed. Unit <match23> generated.

Analyzing generic Entity <matching_logic> (Architecture <default>).
	seedline = 1
	line_mask = 12
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd line 263: The following signals are missing in the process sensitivity list:
   inc<1><1>, inc<1><0>.
Entity <matching_logic> analyzed. Unit <matching_logic57> generated.

Analyzing Entity <unique> (Architecture <default>).
Entity <unique> analyzed. Unit <unique> generated.

Analyzing Entity <seed_merger> (Architecture <default>).
Entity <seed_merger> analyzed. Unit <seed_merger> generated.

Analyzing generic Entity <uniquifier> (Architecture <default>).
	track_width = 52
WARNING:Xst:1610 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 101: Width mismatch. <data_stage0> has a width of 42 bits but assigned expression is 52-bit wide.
WARNING:Xst:1610 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 110: Width mismatch. <track_out> has a width of 52 bits but assigned expression is 42-bit wide.
Entity <uniquifier> analyzed. Unit <uniquifier> generated.

Analyzing Entity <zch_merger> (Architecture <default>).
Entity <zch_merger> analyzed. Unit <zch_merger> generated.

Analyzing generic Entity <uniquifier> (Architecture <default>).
	track_width = 53
WARNING:Xst:1610 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 101: Width mismatch. <data_stage0> has a width of 42 bits but assigned expression is 53-bit wide.
WARNING:Xst:1610 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd line 110: Width mismatch. <track_out> has a width of 53 bits but assigned expression is 42-bit wide.
Entity <uniquifier> analyzed. Unit <uniquifier58> generated.

Analyzing Entity <zch_resorter> (Architecture <default>).
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd line 200: The following signals are missing in the process sensitivity list:
   mem_out<1><41>, mem_out<1><40>, mem_out<1><39>, mem_out<1><38>, mem_out<1><37>, mem_out<1><36>, mem_out<1><35>, mem_out<1><34>, mem_out<1><33>, mem_out<1><32>, mem_out<1><31>, mem_out<1><30>, mem_out<1><29>, mem_out<1><28>, mem_out<1><27>, mem_out<1><26>, mem_out<1><25>, mem_out<1><24>, mem_out<1><23>, mem_out<1><22>, mem_out<1><21>, mem_out<1><20>, mem_out<1><19>, mem_out<1><18>, mem_out<1><17>, mem_out<1><16>, mem_out<1><15>, mem_out<1><14>, mem_out<1><13>, mem_out<1><12>, mem_out<1><11>, mem_out<1><10>, mem_out<1><9>, mem_out<1><8>, mem_out<1><7>, mem_out<1><6>, mem_out<1><5>, mem_out<1><4>, mem_out<1><3>, mem_out<1><2>, mem_out<1><1>, mem_out<1><0>, mem_out<0><41>, mem_out<0><40>, mem_out<0><39>, mem_out<0><38>, mem_out<0><37>, mem_out<0><36>, mem_out<0><35>, mem_out<0><34>, mem_out<0><33>, mem_out<0><32>, mem_out<0><31>, mem_out<0><30>, mem_out<0><29>, mem_out<0><28>, mem_out<0><27>, mem_out<0><26>, mem_out<0><25>, mem_out<0><24>, mem_out<0><23>, mem_out<0><22>, mem_out<0><21>, mem_out<0><20>,
   mem_out<0><19>, mem_out<0><18>, mem_out<0><17>, mem_out<0><16>, mem_out<0><15>, mem_out<0><14>, mem_out<0><13>, mem_out<0><12>, mem_out<0><11>, mem_out<0><10>, mem_out<0><9>, mem_out<0><8>, mem_out<0><7>, mem_out<0><6>, mem_out<0><5>, mem_out<0><4>, mem_out<0><3>, mem_out<0><2>, mem_out<0><1>, mem_out<0><0>.
Entity <zch_resorter> analyzed. Unit <zch_resorter> generated.

Analyzing generic Entity <uniquifier> (Architecture <default>).
	track_width = 42
Entity <uniquifier> analyzed. Unit <uniquifier59> generated.

Analyzing Entity <reconst> (Architecture <default>).
Entity <reconst> analyzed. Unit <reconst> generated.

Analyzing Entity <mask_id_lut> (Architecture <default>).
Entity <mask_id_lut> analyzed. Unit <mask_id_lut> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 5
Entity <acoeff_lut> analyzed. Unit <acoeff_lut> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 4
Entity <acoeff_lut> analyzed. Unit <acoeff_lut60> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 3
Entity <acoeff_lut> analyzed. Unit <acoeff_lut61> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 2
Entity <acoeff_lut> analyzed. Unit <acoeff_lut62> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 1
Entity <acoeff_lut> analyzed. Unit <acoeff_lut63> generated.

Analyzing generic Entity <acoeff_lut> (Architecture <default>).
	plane = 0
Entity <acoeff_lut> analyzed. Unit <acoeff_lut64> generated.

Analyzing Entity <c1_lut> (Architecture <default>).
Entity <c1_lut> analyzed. Unit <c1_lut> generated.

Analyzing Entity <mult_wrapper> (Architecture <default>).
WARNING:Xst:766 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd line 60: Generating a Black Box for component <mult18x18>.
Entity <mult_wrapper> analyzed. Unit <mult_wrapper> generated.

Analyzing generic Entity <divide_wrapper> (Architecture <default>).
	div_stages = 7
WARNING:Xst:753 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd line 58: Unconnected output port 'remd' of component 'cg_divide'.
WARNING:Xst:766 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd line 58: Generating a Black Box for component <cg_divide>.
Entity <divide_wrapper> analyzed. Unit <divide_wrapper> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <divide_wrapper>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/divide_wrapper_xilinx.vhd.
WARNING:Xst:647 - Input <aclr> is never used.
Unit <divide_wrapper> synthesized.


Synthesizing Unit <mult_wrapper>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/mult_wrapper_xilinx.vhd.
WARNING:Xst:646 - Signal <product<35:26>> is assigned but never used.
WARNING:Xst:646 - Signal <product<6:0>> is assigned but never used.
WARNING:Xst:646 - Signal <result_ext<0>> is assigned but never used.
    Found 19-bit register for signal <product_reg>.
    Found 19-bit adder for signal <result_ext>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <mult_wrapper> synthesized.


Synthesizing Unit <c1_lut>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <c1>.
    Summary:
	inferred   1 ROM(s).
Unit <c1_lut> synthesized.


Synthesizing Unit <acoeff_lut64>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut64> synthesized.


Synthesizing Unit <acoeff_lut63>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut63> synthesized.


Synthesizing Unit <acoeff_lut62>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut62> synthesized.


Synthesizing Unit <acoeff_lut61>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut61> synthesized.


Synthesizing Unit <acoeff_lut60>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut60> synthesized.


Synthesizing Unit <acoeff_lut>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 22x13-bit ROM for signal <acoeff>.
    Summary:
	inferred   1 ROM(s).
Unit <acoeff_lut> synthesized.


Synthesizing Unit <mask_id_lut>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
Unit <mask_id_lut> synthesized.


Synthesizing Unit <uniquifier59>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd.
    Using one-hot encoding for signal <drop>.
    Found 2-bit adder for signal <$n0027> created at line 72.
    Found 2-bit adder for signal <$n0029> created at line 72.
    Found 32-bit adder for signal <$n0030> created at line 72.
    Found 32-bit adder for signal <$n0031> created at line 72.
    Found 32-bit comparator greatequal for signal <$n0039> created at line 169.
    Found 32-bit adder for signal <$n0040> created at line 72.
    Found 33-bit adder for signal <$n0043> created at line 72.
    Found 32-bit adder for signal <$n0044> created at line 72.
    Found 33-bit adder for signal <$n0047> created at line 72.
    Found 32-bit adder for signal <$n0062> created at line 72.
    Found 32-bit adder for signal <$n0071> created at line 72.
    Found 6-bit comparator equal for signal <$n0078> created at line 152.
    Found 6-bit comparator equal for signal <$n0079> created at line 152.
    Found 6-bit comparator equal for signal <$n0080> created at line 152.
    Found 6-bit comparator equal for signal <$n0081> created at line 152.
    Found 6-bit comparator equal for signal <$n0082> created at line 152.
    Found 6-bit comparator equal for signal <$n0083> created at line 152.
    Found 1-bit adder carry out for signal <$n0084> created at line 72.
    Found 1-bit adder carry out for signal <$n0085> created at line 72.
    Found 42-bit register for signal <data_stage0>.
    Found 42-bit register for signal <data_stage1>.
    Found 1-bit register for signal <ready_stage0>.
    Found 1-bit register for signal <valid_stage0>.
    Found 1-bit register for signal <valid_stage1>.
    Found 324 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  87 D-type flip-flop(s).
	inferred  12 Adder/Subtracter(s).
	inferred   7 Comparator(s).
	inferred 324 Multiplexer(s).
Unit <uniquifier59> synthesized.


Synthesizing Unit <zch_resorter>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_resorter.vhd.
    Found 16x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 16-word x 52-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in_i<1>> | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in_i>    |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 16x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 16-word x 52-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in_i<0>> | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in_i>    |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 4-bit comparator not equal for signal <$n0016> created at line 166.
    Found 4-bit comparator not equal for signal <$n0017> created at line 166.
    Found 3-bit comparator less for signal <$n0029> created at line 184.
    Found 3-bit comparator equal for signal <$n0030> created at line 184.
    Found 7-bit comparator less for signal <$n0031> created at line 184.
    Found 4-bit up counter for signal <rd_addr_reg>.
    Found 1-bit register for signal <ready_in_reg>.
    Found 8-bit register for signal <wr_addr_last>.
    Found 4-bit up counter for signal <wr_addr_reg>.
    Found 42 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 RAM(s).
	inferred   4 Counter(s).
	inferred   9 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred  42 Multiplexer(s).
Unit <zch_resorter> synthesized.


Synthesizing Unit <uniquifier58>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd.
WARNING:Xst:647 - Input <track_in<52:42>> is never used.
    Using one-hot encoding for signal <drop>.
    Found 2-bit adder for signal <$n0027> created at line 72.
    Found 2-bit adder for signal <$n0029> created at line 72.
    Found 32-bit adder for signal <$n0030> created at line 72.
    Found 32-bit adder for signal <$n0031> created at line 72.
    Found 32-bit comparator greatequal for signal <$n0039> created at line 169.
    Found 32-bit adder for signal <$n0040> created at line 72.
    Found 33-bit adder for signal <$n0043> created at line 72.
    Found 32-bit adder for signal <$n0044> created at line 72.
    Found 33-bit adder for signal <$n0047> created at line 72.
    Found 32-bit adder for signal <$n0062> created at line 72.
    Found 32-bit adder for signal <$n0071> created at line 72.
    Found 6-bit comparator equal for signal <$n0078> created at line 152.
    Found 6-bit comparator equal for signal <$n0079> created at line 152.
    Found 6-bit comparator equal for signal <$n0080> created at line 152.
    Found 6-bit comparator equal for signal <$n0081> created at line 152.
    Found 6-bit comparator equal for signal <$n0082> created at line 152.
    Found 6-bit comparator equal for signal <$n0083> created at line 152.
    Found 1-bit adder carry out for signal <$n0084> created at line 72.
    Found 1-bit adder carry out for signal <$n0085> created at line 72.
    Found 42-bit register for signal <data_stage0>.
    Found 42-bit register for signal <data_stage1>.
    Found 1-bit register for signal <ready_stage0>.
    Found 1-bit register for signal <valid_stage0>.
    Found 1-bit register for signal <valid_stage1>.
    Found 324 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  87 D-type flip-flop(s).
	inferred  12 Adder/Subtracter(s).
	inferred   7 Comparator(s).
	inferred 324 Multiplexer(s).
Unit <uniquifier58> synthesized.


Synthesizing Unit <zch_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0004> created at line 103.
    Found 6-bit adder for signal <$n0012> created at line 103.
    Found 6-bit adder for signal <$n0013>.
    Found 4-bit adder for signal <$n0017> created at line 94.
    Found 6-bit adder for signal <$n0022> created at line 103.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0048> created at line 103.
    Found 3-bit adder for signal <$n0049> created at line 94.
    Found 3-bit comparator not equal for signal <$n0053> created at line 178.
    Found 3-bit comparator not equal for signal <$n0057> created at line 178.
    Found 3-bit comparator not equal for signal <$n0061> created at line 178.
    Found 4-bit adder for signal <$n0067>.
    Found 4-bit adder for signal <$n0072>.
    Found 4-bit subtractor for signal <$n0088> created at line 103.
    Found 4-bit subtractor for signal <$n0089> created at line 103.
    Found 4-bit subtractor for signal <$n0090> created at line 103.
    Found 4-bit comparator less for signal <$n0091> created at line 182.
    Found 4-bit comparator equal for signal <$n0092> created at line 182.
    Found 7-bit comparator less for signal <$n0093> created at line 182.
    Found 4-bit comparator less for signal <$n0094> created at line 182.
    Found 4-bit comparator equal for signal <$n0095> created at line 182.
    Found 7-bit comparator less for signal <$n0096> created at line 182.
    Found 4-bit comparator less for signal <$n0097> created at line 182.
    Found 4-bit comparator equal for signal <$n0098> created at line 182.
    Found 7-bit comparator less for signal <$n0099> created at line 182.
    Found 4x3-bit multiplier for signal <$n0103> created at line 103.
    Found 4x3-bit multiplier for signal <$n0104> created at line 103.
    Found 4x3-bit multiplier for signal <$n0105> created at line 103.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  13 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


Synthesizing Unit <uniquifier>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/uniquifier.vhd.
WARNING:Xst:647 - Input <track_in<51:42>> is never used.
    Using one-hot encoding for signal <drop>.
    Found 2-bit adder for signal <$n0027> created at line 72.
    Found 2-bit adder for signal <$n0029> created at line 72.
    Found 32-bit adder for signal <$n0030> created at line 72.
    Found 32-bit adder for signal <$n0031> created at line 72.
    Found 32-bit comparator greatequal for signal <$n0039> created at line 169.
    Found 32-bit adder for signal <$n0040> created at line 72.
    Found 33-bit adder for signal <$n0043> created at line 72.
    Found 32-bit adder for signal <$n0044> created at line 72.
    Found 33-bit adder for signal <$n0047> created at line 72.
    Found 32-bit adder for signal <$n0062> created at line 72.
    Found 32-bit adder for signal <$n0071> created at line 72.
    Found 6-bit comparator equal for signal <$n0078> created at line 152.
    Found 6-bit comparator equal for signal <$n0079> created at line 152.
    Found 6-bit comparator equal for signal <$n0080> created at line 152.
    Found 6-bit comparator equal for signal <$n0081> created at line 152.
    Found 6-bit comparator equal for signal <$n0082> created at line 152.
    Found 6-bit comparator equal for signal <$n0083> created at line 152.
    Found 1-bit adder carry out for signal <$n0084> created at line 72.
    Found 1-bit adder carry out for signal <$n0085> created at line 72.
    Found 42-bit register for signal <data_stage0>.
    Found 42-bit register for signal <data_stage1>.
    Found 1-bit register for signal <ready_stage0>.
    Found 1-bit register for signal <valid_stage0>.
    Found 1-bit register for signal <valid_stage1>.
    Found 324 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  87 D-type flip-flop(s).
	inferred  12 Adder/Subtracter(s).
	inferred   7 Comparator(s).
	inferred 324 Multiplexer(s).
Unit <uniquifier> synthesized.


Synthesizing Unit <seed_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/seed_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 3-bit comparator not equal for signal <$n0024> created at line 149.
    Found 3-bit comparator not equal for signal <$n0026> created at line 149.
    Found 3-bit comparator not equal for signal <$n0028> created at line 149.
    Found 3-bit comparator less for signal <$n0045> created at line 153.
    Found 3-bit comparator equal for signal <$n0046> created at line 153.
    Found 7-bit comparator less for signal <$n0047> created at line 153.
    Found 3-bit comparator less for signal <$n0048> created at line 153.
    Found 3-bit comparator equal for signal <$n0049> created at line 153.
    Found 7-bit comparator less for signal <$n0050> created at line 153.
    Found 3-bit comparator less for signal <$n0051> created at line 153.
    Found 3-bit comparator equal for signal <$n0052> created at line 153.
    Found 7-bit comparator less for signal <$n0053> created at line 153.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  12 Comparator(s).
Unit <seed_merger> synthesized.


Synthesizing Unit <matching_logic57>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd.
WARNING:Xst:646 - Signal <ab<1>> is assigned but never used.
WARNING:Xst:646 - Signal <tinc<1>> is assigned but never used.
WARNING:Xst:646 - Signal <num_possible_match<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_a_ll_b<1>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_b_ll_b<1>> is assigned but never used.
    Found 3-bit adder for signal <$n0004> created at line 193.
    Found 6-bit adder for signal <$n0038> created at line 129.
    Found 7-bit comparator less for signal <$n0046> created at line 172.
    Found 7-bit comparator greater for signal <$n0047> created at line 173.
    Found 7-bit comparator less for signal <$n0048> created at line 174.
    Found 7-bit comparator greater for signal <$n0049> created at line 175.
    Found 7-bit comparator less for signal <$n0057> created at line 172.
    Found 7-bit comparator greater for signal <$n0058> created at line 173.
    Found 7-bit comparator less for signal <$n0059> created at line 174.
    Found 7-bit comparator greater for signal <$n0060> created at line 175.
    Found 7-bit comparator less for signal <$n0068> created at line 172.
    Found 7-bit comparator greater for signal <$n0069> created at line 173.
    Found 7-bit comparator less for signal <$n0070> created at line 174.
    Found 7-bit comparator greater for signal <$n0071> created at line 175.
    Found 7-bit comparator less for signal <$n0079> created at line 172.
    Found 7-bit comparator greater for signal <$n0080> created at line 173.
    Found 7-bit comparator less for signal <$n0081> created at line 174.
    Found 7-bit comparator greater for signal <$n0082> created at line 175.
    Found 7-bit comparator less for signal <$n0090> created at line 172.
    Found 7-bit comparator greater for signal <$n0091> created at line 173.
    Found 7-bit comparator less for signal <$n0092> created at line 174.
    Found 7-bit comparator greater for signal <$n0093> created at line 175.
    Found 3-bit adder for signal <$n0094> created at line 194.
    Found 3-bit adder for signal <$n0096> created at line 206.
    Found 3-bit adder for signal <$n0097> created at line 218.
    Found 3-bit comparator greatequal for signal <$n0100> created at line 238.
    Found 3-bit adder for signal <$n0102> created at line 194.
    Found 3-bit adder for signal <$n0103> created at line 194.
    Found 3-bit adder for signal <$n0104> created at line 194.
    Found 3-bit adder for signal <$n0106> created at line 206.
    Found 3-bit adder for signal <$n0108> created at line 206.
    Found 3-bit adder for signal <$n0110> created at line 206.
    Found 3-bit adder for signal <$n0111> created at line 218.
    Found 3-bit adder for signal <$n0112> created at line 218.
    Found 3-bit adder for signal <$n0113> created at line 218.
    Found 3-bit comparator less for signal <$n0139> created at line 150.
    Found 3-bit comparator equal for signal <$n0140> created at line 150.
    Found 10-bit comparator less for signal <$n0141> created at line 150.
    Found 3-bit comparator greater for signal <$n0142> created at line 153.
    Found 10-bit comparator greater for signal <$n0143> created at line 153.
    Found 3-bit comparator less for signal <$n0144> created at line 156.
    Found 3-bit comparator equal for signal <$n0145> created at line 156.
    Found 10-bit comparator less for signal <$n0146> created at line 156.
    Found 3-bit comparator greater for signal <$n0147> created at line 159.
    Found 10-bit comparator greater for signal <$n0148> created at line 159.
    Found 3-bit comparator less for signal <$n0149> created at line 162.
    Found 3-bit comparator equal for signal <$n0150> created at line 162.
    Found 10-bit comparator less for signal <$n0151> created at line 162.
    Found 3-bit comparator greater for signal <$n0152> created at line 165.
    Found 10-bit comparator greater for signal <$n0153> created at line 165.
    Found 3-bit comparator less for signal <$n0154> created at line 168.
    Found 3-bit comparator equal for signal <$n0155> created at line 168.
    Found 10-bit comparator less for signal <$n0156> created at line 168.
    Found 3-bit comparator less for signal <$n0157> created at line 150.
    Found 3-bit comparator equal for signal <$n0158> created at line 150.
    Found 10-bit comparator less for signal <$n0159> created at line 150.
    Found 3-bit comparator greater for signal <$n0160> created at line 153.
    Found 10-bit comparator greater for signal <$n0161> created at line 153.
    Found 3-bit comparator less for signal <$n0162> created at line 156.
    Found 3-bit comparator equal for signal <$n0163> created at line 156.
    Found 10-bit comparator less for signal <$n0164> created at line 156.
    Found 3-bit comparator greater for signal <$n0165> created at line 159.
    Found 10-bit comparator greater for signal <$n0166> created at line 159.
    Found 3-bit comparator less for signal <$n0167> created at line 162.
    Found 3-bit comparator equal for signal <$n0168> created at line 162.
    Found 10-bit comparator less for signal <$n0169> created at line 162.
    Found 3-bit comparator greater for signal <$n0170> created at line 165.
    Found 10-bit comparator greater for signal <$n0171> created at line 165.
    Found 3-bit comparator less for signal <$n0172> created at line 168.
    Found 3-bit comparator equal for signal <$n0173> created at line 168.
    Found 10-bit comparator less for signal <$n0174> created at line 168.
    Found 3-bit comparator less for signal <$n0175> created at line 150.
    Found 3-bit comparator equal for signal <$n0176> created at line 150.
    Found 10-bit comparator less for signal <$n0177> created at line 150.
    Found 3-bit comparator greater for signal <$n0178> created at line 153.
    Found 10-bit comparator greater for signal <$n0179> created at line 153.
    Found 3-bit comparator less for signal <$n0180> created at line 156.
    Found 3-bit comparator equal for signal <$n0181> created at line 156.
    Found 10-bit comparator less for signal <$n0182> created at line 156.
    Found 3-bit comparator greater for signal <$n0183> created at line 159.
    Found 10-bit comparator greater for signal <$n0184> created at line 159.
    Found 3-bit comparator less for signal <$n0185> created at line 162.
    Found 3-bit comparator equal for signal <$n0186> created at line 162.
    Found 10-bit comparator less for signal <$n0187> created at line 162.
    Found 3-bit comparator greater for signal <$n0188> created at line 165.
    Found 10-bit comparator greater for signal <$n0189> created at line 165.
    Found 3-bit comparator less for signal <$n0190> created at line 168.
    Found 3-bit comparator equal for signal <$n0191> created at line 168.
    Found 10-bit comparator less for signal <$n0192> created at line 168.
    Found 3-bit comparator less for signal <$n0193> created at line 150.
    Found 3-bit comparator equal for signal <$n0194> created at line 150.
    Found 10-bit comparator less for signal <$n0195> created at line 150.
    Found 3-bit comparator greater for signal <$n0196> created at line 153.
    Found 10-bit comparator greater for signal <$n0197> created at line 153.
    Found 3-bit comparator less for signal <$n0198> created at line 156.
    Found 3-bit comparator equal for signal <$n0199> created at line 156.
    Found 10-bit comparator less for signal <$n0200> created at line 156.
    Found 3-bit comparator greater for signal <$n0201> created at line 159.
    Found 10-bit comparator greater for signal <$n0202> created at line 159.
    Found 3-bit comparator less for signal <$n0203> created at line 162.
    Found 3-bit comparator equal for signal <$n0204> created at line 162.
    Found 10-bit comparator less for signal <$n0205> created at line 162.
    Found 3-bit comparator greater for signal <$n0206> created at line 165.
    Found 10-bit comparator greater for signal <$n0207> created at line 165.
    Found 3-bit comparator less for signal <$n0208> created at line 168.
    Found 3-bit comparator equal for signal <$n0209> created at line 168.
    Found 10-bit comparator less for signal <$n0210> created at line 168.
    Found 3-bit comparator less for signal <$n0211> created at line 150.
    Found 3-bit comparator equal for signal <$n0212> created at line 150.
    Found 10-bit comparator less for signal <$n0213> created at line 150.
    Found 3-bit comparator greater for signal <$n0214> created at line 153.
    Found 10-bit comparator greater for signal <$n0215> created at line 153.
    Found 3-bit comparator less for signal <$n0216> created at line 156.
    Found 3-bit comparator equal for signal <$n0217> created at line 156.
    Found 10-bit comparator less for signal <$n0218> created at line 156.
    Found 3-bit comparator greater for signal <$n0219> created at line 159.
    Found 10-bit comparator greater for signal <$n0220> created at line 159.
    Found 3-bit comparator less for signal <$n0221> created at line 162.
    Found 3-bit comparator equal for signal <$n0222> created at line 162.
    Found 10-bit comparator less for signal <$n0223> created at line 162.
    Found 3-bit comparator greater for signal <$n0224> created at line 165.
    Found 10-bit comparator greater for signal <$n0225> created at line 165.
    Found 3-bit comparator less for signal <$n0226> created at line 168.
    Found 3-bit comparator equal for signal <$n0227> created at line 168.
    Found 10-bit comparator less for signal <$n0228> created at line 168.
    Found 7-bit subtractor for signal <asa_minus>.
    Found 3-bit adder for signal <num_possible_match>.
    Found 10-bit subtractor for signal <ysa_minus>.
    Found 10-bit adder for signal <ysa_plus>.
    Found 10-bit subtractor for signal <ysb_minus>.
    Found 10-bit adder for signal <ysb_plus>.
    Found 36 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  20 Adder/Subtracter(s).
	inferred 111 Comparator(s).
	inferred  36 Multiplexer(s).
Unit <matching_logic57> synthesized.


Synthesizing Unit <matching_logic56>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd.
WARNING:Xst:646 - Signal <ab<2>> is assigned but never used.
WARNING:Xst:646 - Signal <tinc<2>> is assigned but never used.
WARNING:Xst:646 - Signal <num_possible_match<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_a_ll_b<2>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_b_ll_b<2>> is assigned but never used.
    Found 3-bit adder for signal <$n0003> created at line 193.
    Found 6-bit adder for signal <$n0038> created at line 129.
    Found 7-bit comparator less for signal <$n0046> created at line 172.
    Found 7-bit comparator greater for signal <$n0047> created at line 173.
    Found 7-bit comparator less for signal <$n0048> created at line 174.
    Found 7-bit comparator greater for signal <$n0049> created at line 175.
    Found 7-bit comparator less for signal <$n0057> created at line 172.
    Found 7-bit comparator greater for signal <$n0058> created at line 173.
    Found 7-bit comparator less for signal <$n0059> created at line 174.
    Found 7-bit comparator greater for signal <$n0060> created at line 175.
    Found 7-bit comparator less for signal <$n0068> created at line 172.
    Found 7-bit comparator greater for signal <$n0069> created at line 173.
    Found 7-bit comparator less for signal <$n0070> created at line 174.
    Found 7-bit comparator greater for signal <$n0071> created at line 175.
    Found 7-bit comparator less for signal <$n0079> created at line 172.
    Found 7-bit comparator greater for signal <$n0080> created at line 173.
    Found 7-bit comparator less for signal <$n0081> created at line 174.
    Found 7-bit comparator greater for signal <$n0082> created at line 175.
    Found 7-bit comparator less for signal <$n0090> created at line 172.
    Found 7-bit comparator greater for signal <$n0091> created at line 173.
    Found 7-bit comparator less for signal <$n0092> created at line 174.
    Found 7-bit comparator greater for signal <$n0093> created at line 175.
    Found 3-bit adder for signal <$n0094> created at line 194.
    Found 3-bit adder for signal <$n0096> created at line 206.
    Found 3-bit adder for signal <$n0097> created at line 218.
    Found 3-bit comparator greatequal for signal <$n0100> created at line 238.
    Found 3-bit adder for signal <$n0102> created at line 194.
    Found 3-bit adder for signal <$n0103> created at line 194.
    Found 3-bit adder for signal <$n0104> created at line 194.
    Found 3-bit adder for signal <$n0106> created at line 206.
    Found 3-bit adder for signal <$n0108> created at line 206.
    Found 3-bit adder for signal <$n0110> created at line 206.
    Found 3-bit adder for signal <$n0111> created at line 218.
    Found 3-bit adder for signal <$n0112> created at line 218.
    Found 3-bit adder for signal <$n0113> created at line 218.
    Found 3-bit comparator less for signal <$n0139> created at line 150.
    Found 3-bit comparator equal for signal <$n0140> created at line 150.
    Found 10-bit comparator less for signal <$n0141> created at line 150.
    Found 3-bit comparator greater for signal <$n0142> created at line 153.
    Found 10-bit comparator greater for signal <$n0143> created at line 153.
    Found 3-bit comparator less for signal <$n0144> created at line 156.
    Found 3-bit comparator equal for signal <$n0145> created at line 156.
    Found 10-bit comparator less for signal <$n0146> created at line 156.
    Found 3-bit comparator greater for signal <$n0147> created at line 159.
    Found 10-bit comparator greater for signal <$n0148> created at line 159.
    Found 3-bit comparator less for signal <$n0149> created at line 162.
    Found 3-bit comparator equal for signal <$n0150> created at line 162.
    Found 10-bit comparator less for signal <$n0151> created at line 162.
    Found 3-bit comparator greater for signal <$n0152> created at line 165.
    Found 10-bit comparator greater for signal <$n0153> created at line 165.
    Found 3-bit comparator less for signal <$n0154> created at line 168.
    Found 3-bit comparator equal for signal <$n0155> created at line 168.
    Found 10-bit comparator less for signal <$n0156> created at line 168.
    Found 3-bit comparator less for signal <$n0157> created at line 150.
    Found 3-bit comparator equal for signal <$n0158> created at line 150.
    Found 10-bit comparator less for signal <$n0159> created at line 150.
    Found 3-bit comparator greater for signal <$n0160> created at line 153.
    Found 10-bit comparator greater for signal <$n0161> created at line 153.
    Found 3-bit comparator less for signal <$n0162> created at line 156.
    Found 3-bit comparator equal for signal <$n0163> created at line 156.
    Found 10-bit comparator less for signal <$n0164> created at line 156.
    Found 3-bit comparator greater for signal <$n0165> created at line 159.
    Found 10-bit comparator greater for signal <$n0166> created at line 159.
    Found 3-bit comparator less for signal <$n0167> created at line 162.
    Found 3-bit comparator equal for signal <$n0168> created at line 162.
    Found 10-bit comparator less for signal <$n0169> created at line 162.
    Found 3-bit comparator greater for signal <$n0170> created at line 165.
    Found 10-bit comparator greater for signal <$n0171> created at line 165.
    Found 3-bit comparator less for signal <$n0172> created at line 168.
    Found 3-bit comparator equal for signal <$n0173> created at line 168.
    Found 10-bit comparator less for signal <$n0174> created at line 168.
    Found 3-bit comparator less for signal <$n0175> created at line 150.
    Found 3-bit comparator equal for signal <$n0176> created at line 150.
    Found 10-bit comparator less for signal <$n0177> created at line 150.
    Found 3-bit comparator greater for signal <$n0178> created at line 153.
    Found 10-bit comparator greater for signal <$n0179> created at line 153.
    Found 3-bit comparator less for signal <$n0180> created at line 156.
    Found 3-bit comparator equal for signal <$n0181> created at line 156.
    Found 10-bit comparator less for signal <$n0182> created at line 156.
    Found 3-bit comparator greater for signal <$n0183> created at line 159.
    Found 10-bit comparator greater for signal <$n0184> created at line 159.
    Found 3-bit comparator less for signal <$n0185> created at line 162.
    Found 3-bit comparator equal for signal <$n0186> created at line 162.
    Found 10-bit comparator less for signal <$n0187> created at line 162.
    Found 3-bit comparator greater for signal <$n0188> created at line 165.
    Found 10-bit comparator greater for signal <$n0189> created at line 165.
    Found 3-bit comparator less for signal <$n0190> created at line 168.
    Found 3-bit comparator equal for signal <$n0191> created at line 168.
    Found 10-bit comparator less for signal <$n0192> created at line 168.
    Found 3-bit comparator less for signal <$n0193> created at line 150.
    Found 3-bit comparator equal for signal <$n0194> created at line 150.
    Found 10-bit comparator less for signal <$n0195> created at line 150.
    Found 3-bit comparator greater for signal <$n0196> created at line 153.
    Found 10-bit comparator greater for signal <$n0197> created at line 153.
    Found 3-bit comparator less for signal <$n0198> created at line 156.
    Found 3-bit comparator equal for signal <$n0199> created at line 156.
    Found 10-bit comparator less for signal <$n0200> created at line 156.
    Found 3-bit comparator greater for signal <$n0201> created at line 159.
    Found 10-bit comparator greater for signal <$n0202> created at line 159.
    Found 3-bit comparator less for signal <$n0203> created at line 162.
    Found 3-bit comparator equal for signal <$n0204> created at line 162.
    Found 10-bit comparator less for signal <$n0205> created at line 162.
    Found 3-bit comparator greater for signal <$n0206> created at line 165.
    Found 10-bit comparator greater for signal <$n0207> created at line 165.
    Found 3-bit comparator less for signal <$n0208> created at line 168.
    Found 3-bit comparator equal for signal <$n0209> created at line 168.
    Found 10-bit comparator less for signal <$n0210> created at line 168.
    Found 3-bit comparator less for signal <$n0211> created at line 150.
    Found 3-bit comparator equal for signal <$n0212> created at line 150.
    Found 10-bit comparator less for signal <$n0213> created at line 150.
    Found 3-bit comparator greater for signal <$n0214> created at line 153.
    Found 10-bit comparator greater for signal <$n0215> created at line 153.
    Found 3-bit comparator less for signal <$n0216> created at line 156.
    Found 3-bit comparator equal for signal <$n0217> created at line 156.
    Found 10-bit comparator less for signal <$n0218> created at line 156.
    Found 3-bit comparator greater for signal <$n0219> created at line 159.
    Found 10-bit comparator greater for signal <$n0220> created at line 159.
    Found 3-bit comparator less for signal <$n0221> created at line 162.
    Found 3-bit comparator equal for signal <$n0222> created at line 162.
    Found 10-bit comparator less for signal <$n0223> created at line 162.
    Found 3-bit comparator greater for signal <$n0224> created at line 165.
    Found 10-bit comparator greater for signal <$n0225> created at line 165.
    Found 3-bit comparator less for signal <$n0226> created at line 168.
    Found 3-bit comparator equal for signal <$n0227> created at line 168.
    Found 10-bit comparator less for signal <$n0228> created at line 168.
    Found 7-bit subtractor for signal <asa_minus>.
    Found 3-bit adder for signal <num_possible_match>.
    Found 10-bit subtractor for signal <ysa_minus>.
    Found 10-bit adder for signal <ysa_plus>.
    Found 10-bit subtractor for signal <ysb_minus>.
    Found 10-bit adder for signal <ysb_plus>.
    Found 36 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  20 Adder/Subtracter(s).
	inferred 111 Comparator(s).
	inferred  36 Multiplexer(s).
Unit <matching_logic56> synthesized.


Synthesizing Unit <matching_logic>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_logic.vhd.
WARNING:Xst:646 - Signal <ab<3>> is assigned but never used.
WARNING:Xst:646 - Signal <tinc<3>> is assigned but never used.
WARNING:Xst:646 - Signal <num_possible_match<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_a_ll_b<3>> is assigned but never used.
WARNING:Xst:646 - Signal <cmp_b_ll_b<3>> is assigned but never used.
    Found 3-bit adder for signal <$n0002> created at line 193.
    Found 6-bit adder for signal <$n0038> created at line 129.
    Found 7-bit comparator less for signal <$n0046> created at line 172.
    Found 7-bit comparator greater for signal <$n0047> created at line 173.
    Found 7-bit comparator less for signal <$n0048> created at line 174.
    Found 7-bit comparator greater for signal <$n0049> created at line 175.
    Found 7-bit comparator less for signal <$n0057> created at line 172.
    Found 7-bit comparator greater for signal <$n0058> created at line 173.
    Found 7-bit comparator less for signal <$n0059> created at line 174.
    Found 7-bit comparator greater for signal <$n0060> created at line 175.
    Found 7-bit comparator less for signal <$n0068> created at line 172.
    Found 7-bit comparator greater for signal <$n0069> created at line 173.
    Found 7-bit comparator less for signal <$n0070> created at line 174.
    Found 7-bit comparator greater for signal <$n0071> created at line 175.
    Found 7-bit comparator less for signal <$n0079> created at line 172.
    Found 7-bit comparator greater for signal <$n0080> created at line 173.
    Found 7-bit comparator less for signal <$n0081> created at line 174.
    Found 7-bit comparator greater for signal <$n0082> created at line 175.
    Found 7-bit comparator less for signal <$n0090> created at line 172.
    Found 7-bit comparator greater for signal <$n0091> created at line 173.
    Found 7-bit comparator less for signal <$n0092> created at line 174.
    Found 7-bit comparator greater for signal <$n0093> created at line 175.
    Found 3-bit adder for signal <$n0094> created at line 194.
    Found 3-bit adder for signal <$n0096> created at line 206.
    Found 3-bit adder for signal <$n0097> created at line 218.
    Found 3-bit comparator greatequal for signal <$n0100> created at line 238.
    Found 3-bit adder for signal <$n0102> created at line 194.
    Found 3-bit adder for signal <$n0103> created at line 194.
    Found 3-bit adder for signal <$n0104> created at line 194.
    Found 3-bit adder for signal <$n0106> created at line 206.
    Found 3-bit adder for signal <$n0108> created at line 206.
    Found 3-bit adder for signal <$n0110> created at line 206.
    Found 3-bit adder for signal <$n0111> created at line 218.
    Found 3-bit adder for signal <$n0112> created at line 218.
    Found 3-bit adder for signal <$n0113> created at line 218.
    Found 3-bit comparator less for signal <$n0139> created at line 150.
    Found 3-bit comparator equal for signal <$n0140> created at line 150.
    Found 10-bit comparator less for signal <$n0141> created at line 150.
    Found 3-bit comparator greater for signal <$n0142> created at line 153.
    Found 10-bit comparator greater for signal <$n0143> created at line 153.
    Found 3-bit comparator less for signal <$n0144> created at line 156.
    Found 3-bit comparator equal for signal <$n0145> created at line 156.
    Found 10-bit comparator less for signal <$n0146> created at line 156.
    Found 3-bit comparator greater for signal <$n0147> created at line 159.
    Found 10-bit comparator greater for signal <$n0148> created at line 159.
    Found 3-bit comparator less for signal <$n0149> created at line 162.
    Found 3-bit comparator equal for signal <$n0150> created at line 162.
    Found 10-bit comparator less for signal <$n0151> created at line 162.
    Found 3-bit comparator greater for signal <$n0152> created at line 165.
    Found 10-bit comparator greater for signal <$n0153> created at line 165.
    Found 3-bit comparator less for signal <$n0154> created at line 168.
    Found 3-bit comparator equal for signal <$n0155> created at line 168.
    Found 10-bit comparator less for signal <$n0156> created at line 168.
    Found 3-bit comparator less for signal <$n0157> created at line 150.
    Found 3-bit comparator equal for signal <$n0158> created at line 150.
    Found 10-bit comparator less for signal <$n0159> created at line 150.
    Found 3-bit comparator greater for signal <$n0160> created at line 153.
    Found 10-bit comparator greater for signal <$n0161> created at line 153.
    Found 3-bit comparator less for signal <$n0162> created at line 156.
    Found 3-bit comparator equal for signal <$n0163> created at line 156.
    Found 10-bit comparator less for signal <$n0164> created at line 156.
    Found 3-bit comparator greater for signal <$n0165> created at line 159.
    Found 10-bit comparator greater for signal <$n0166> created at line 159.
    Found 3-bit comparator less for signal <$n0167> created at line 162.
    Found 3-bit comparator equal for signal <$n0168> created at line 162.
    Found 10-bit comparator less for signal <$n0169> created at line 162.
    Found 3-bit comparator greater for signal <$n0170> created at line 165.
    Found 10-bit comparator greater for signal <$n0171> created at line 165.
    Found 3-bit comparator less for signal <$n0172> created at line 168.
    Found 3-bit comparator equal for signal <$n0173> created at line 168.
    Found 10-bit comparator less for signal <$n0174> created at line 168.
    Found 3-bit comparator less for signal <$n0175> created at line 150.
    Found 3-bit comparator equal for signal <$n0176> created at line 150.
    Found 10-bit comparator less for signal <$n0177> created at line 150.
    Found 3-bit comparator greater for signal <$n0178> created at line 153.
    Found 10-bit comparator greater for signal <$n0179> created at line 153.
    Found 3-bit comparator less for signal <$n0180> created at line 156.
    Found 3-bit comparator equal for signal <$n0181> created at line 156.
    Found 10-bit comparator less for signal <$n0182> created at line 156.
    Found 3-bit comparator greater for signal <$n0183> created at line 159.
    Found 10-bit comparator greater for signal <$n0184> created at line 159.
    Found 3-bit comparator less for signal <$n0185> created at line 162.
    Found 3-bit comparator equal for signal <$n0186> created at line 162.
    Found 10-bit comparator less for signal <$n0187> created at line 162.
    Found 3-bit comparator greater for signal <$n0188> created at line 165.
    Found 10-bit comparator greater for signal <$n0189> created at line 165.
    Found 3-bit comparator less for signal <$n0190> created at line 168.
    Found 3-bit comparator equal for signal <$n0191> created at line 168.
    Found 10-bit comparator less for signal <$n0192> created at line 168.
    Found 3-bit comparator less for signal <$n0193> created at line 150.
    Found 3-bit comparator equal for signal <$n0194> created at line 150.
    Found 10-bit comparator less for signal <$n0195> created at line 150.
    Found 3-bit comparator greater for signal <$n0196> created at line 153.
    Found 10-bit comparator greater for signal <$n0197> created at line 153.
    Found 3-bit comparator less for signal <$n0198> created at line 156.
    Found 3-bit comparator equal for signal <$n0199> created at line 156.
    Found 10-bit comparator less for signal <$n0200> created at line 156.
    Found 3-bit comparator greater for signal <$n0201> created at line 159.
    Found 10-bit comparator greater for signal <$n0202> created at line 159.
    Found 3-bit comparator less for signal <$n0203> created at line 162.
    Found 3-bit comparator equal for signal <$n0204> created at line 162.
    Found 10-bit comparator less for signal <$n0205> created at line 162.
    Found 3-bit comparator greater for signal <$n0206> created at line 165.
    Found 10-bit comparator greater for signal <$n0207> created at line 165.
    Found 3-bit comparator less for signal <$n0208> created at line 168.
    Found 3-bit comparator equal for signal <$n0209> created at line 168.
    Found 10-bit comparator less for signal <$n0210> created at line 168.
    Found 3-bit comparator less for signal <$n0211> created at line 150.
    Found 3-bit comparator equal for signal <$n0212> created at line 150.
    Found 10-bit comparator less for signal <$n0213> created at line 150.
    Found 3-bit comparator greater for signal <$n0214> created at line 153.
    Found 10-bit comparator greater for signal <$n0215> created at line 153.
    Found 3-bit comparator less for signal <$n0216> created at line 156.
    Found 3-bit comparator equal for signal <$n0217> created at line 156.
    Found 10-bit comparator less for signal <$n0218> created at line 156.
    Found 3-bit comparator greater for signal <$n0219> created at line 159.
    Found 10-bit comparator greater for signal <$n0220> created at line 159.
    Found 3-bit comparator less for signal <$n0221> created at line 162.
    Found 3-bit comparator equal for signal <$n0222> created at line 162.
    Found 10-bit comparator less for signal <$n0223> created at line 162.
    Found 3-bit comparator greater for signal <$n0224> created at line 165.
    Found 10-bit comparator greater for signal <$n0225> created at line 165.
    Found 3-bit comparator less for signal <$n0226> created at line 168.
    Found 3-bit comparator equal for signal <$n0227> created at line 168.
    Found 10-bit comparator less for signal <$n0228> created at line 168.
    Found 7-bit subtractor for signal <asa_minus>.
    Found 3-bit adder for signal <num_possible_match>.
    Found 10-bit subtractor for signal <ysa_minus>.
    Found 10-bit adder for signal <ysa_plus>.
    Found 10-bit subtractor for signal <ysb_minus>.
    Found 10-bit adder for signal <ysb_plus>.
    Found 36 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  20 Adder/Subtracter(s).
	inferred 111 Comparator(s).
	inferred  36 Multiplexer(s).
Unit <matching_logic> synthesized.


Synthesizing Unit <matching_memory>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/matching_memory.vhd.
    Found 64x26-bit dual-port distributed RAM for signal <ram_block_a>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 26-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr2_in>      |          |
    | dual address       | connected to signal <reg_a>         |          |
    | data in            | connected to signal <ram_in>        |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <ram_a_out>     |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 64x26-bit dual-port distributed RAM for signal <ram_block_b>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 26-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr2_in>      |          |
    | dual address       | connected to signal <reg_b>         |          |
    | data in            | connected to signal <ram_in>        |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <ram_b_out>     |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 5-bit adder for signal <$n0039> created at line 147.
    Found 5-bit adder for signal <$n0040> created at line 148.
    Found 6-bit comparator not equal for signal <$n0048> created at line 186.
    Found 6-bit comparator equal for signal <$n0049> created at line 190.
    Found 1-bit register for signal <invalid_reg>.
    Found 6-bit register for signal <reg_a>.
    Found 6-bit register for signal <reg_b>.
    Found 6-bit register for signal <reg_last>.
    Found 6 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 RAM(s).
	inferred  19 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   2 Comparator(s).
	inferred   6 Multiplexer(s).
Unit <matching_memory> synthesized.


Synthesizing Unit <zch_table55>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table55> synthesized.


Synthesizing Unit <zch_table54>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table54> synthesized.


Synthesizing Unit <zch_table53>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table53> synthesized.


Synthesizing Unit <zch_table52>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table52> synthesized.


Synthesizing Unit <zch_table51>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table51> synthesized.


Synthesizing Unit <zch_table50>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table50> synthesized.


Synthesizing Unit <zch_table49>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table49> synthesized.


Synthesizing Unit <zch_table48>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table48> synthesized.


Synthesizing Unit <zch_table47>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table47> synthesized.


Synthesizing Unit <zch_table46>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table46> synthesized.


Synthesizing Unit <zch_table45>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table45> synthesized.


Synthesizing Unit <zch_table44>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table44> synthesized.


Synthesizing Unit <zch_table43>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table43> synthesized.


Synthesizing Unit <zch_table42>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table42> synthesized.


Synthesizing Unit <zch_table41>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table41> synthesized.


Synthesizing Unit <zch_table40>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table40> synthesized.


Synthesizing Unit <zch_table39>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table39> synthesized.


Synthesizing Unit <sorter>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd.
    Found 10-bit 4-to-1 multiplexer for signal <$n0043>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0044>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0045>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0046>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0047>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0048>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0049>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0051>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0052>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0053>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0054>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0055>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0056>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0057>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0058>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0059>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0060>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0061>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0062>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0063>.
    Found 10-bit 4-to-1 multiplexer for signal <$n0064>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0065>.
    Found 6-bit 4-to-1 multiplexer for signal <$n0066>.
    Found 10-bit comparator lessequal for signal <$n0080> created at line 129.
    Found 3-bit comparator equal for signal <$n0081> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0083> created at line 129.
    Found 3-bit comparator equal for signal <$n0084> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0086> created at line 129.
    Found 3-bit comparator equal for signal <$n0087> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0089> created at line 129.
    Found 3-bit comparator equal for signal <$n0090> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0092> created at line 129.
    Found 3-bit comparator equal for signal <$n0093> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0095> created at line 129.
    Found 3-bit comparator equal for signal <$n0096> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0098> created at line 129.
    Found 3-bit comparator equal for signal <$n0099> created at line 129.
    Found 10-bit comparator lessequal for signal <$n0101> created at line 129.
    Found 3-bit comparator equal for signal <$n0102> created at line 129.
    Found 48-bit register for signal <addr<8:1>>.
    Found 24-bit register for signal <idx<8:1>>.
    Found 3-bit register for signal <last_idx_in>.
    Found 80-bit register for signal <y<8:1>>.
    Summary:
	inferred  75 D-type flip-flop(s).
	inferred  16 Comparator(s).
	inferred 152 Multiplexer(s).
Unit <sorter> synthesized.


Synthesizing Unit <zch_table>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd.
Unit <zch_table> synthesized.


Synthesizing Unit <yt_lut38>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 80x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut38> synthesized.


Synthesizing Unit <proj_y37>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y37> synthesized.


Synthesizing Unit <proj_d36>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d36> synthesized.


Synthesizing Unit <yt_lut35>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 80x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut35> synthesized.


Synthesizing Unit <proj_y34>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y34> synthesized.


Synthesizing Unit <proj_d33>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d33> synthesized.


Synthesizing Unit <yt_lut32>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 80x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut32> synthesized.


Synthesizing Unit <proj_y31>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y31> synthesized.


Synthesizing Unit <proj_d30>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d30> synthesized.


Synthesizing Unit <yt_lut29>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 80x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut29> synthesized.


Synthesizing Unit <proj_y28>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y28> synthesized.


Synthesizing Unit <proj_d27>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d27> synthesized.


Synthesizing Unit <yt_lut26>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 78x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut26> synthesized.


Synthesizing Unit <proj_y25>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y25> synthesized.


Synthesizing Unit <proj_d24>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d24> synthesized.


Synthesizing Unit <fifo_dc_wrapper>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/fifo_dc_wrapper_xilinx.vhd.
Unit <fifo_dc_wrapper> synthesized.


Synthesizing Unit <yt_lut>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/rec_tables.vhd.
    Found 77x11-bit ROM for signal <yt>.
    Summary:
	inferred   1 ROM(s).
Unit <yt_lut> synthesized.


Synthesizing Unit <proj_y>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_y.vhd.
WARNING:Xst:646 - Signal <p<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s_round<0>> is assigned but never used.
    Found 7x8-bit multiplier for signal <p>.
    Found 13-bit adder for signal <s>.
    Found 11-bit adder for signal <s_round>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_y> synthesized.


Synthesizing Unit <proj_d>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/proj_d.vhd.
WARNING:Xst:647 - Input <y<3:0>> is never used.
WARNING:Xst:646 - Signal <p<9:0>> is assigned but never used.
WARNING:Xst:646 - Signal <s<0>> is assigned but never used.
    Found 8-bit subtractor for signal <$n0000> created at line 83.
    Found 9x9-bit multiplier for signal <p>.
    Found 8-bit adder for signal <s>.
    Summary:
	inferred   2 Adder/Subtracter(s).
	inferred   1 Multiplier(s).
Unit <proj_d> synthesized.


Synthesizing Unit <buffer_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/buffer_merger.vhd.
    Found 4-bit comparator less for signal <$n0030> created at line 173.
    Found 1-bit register for signal <state<0>>.
    Found 2-bit register for signal <valid>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <buffer_merger> synthesized.


Synthesizing Unit <inputcontrol>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/inputcontrol.vhd.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 3                                              |
    | Outputs            | 2                                              |
    | Clock              | clk_in (rising_edge)                           |
    | Reset              | rst_n (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <d_out_reg>.
    Found 8-bit register for signal <i_hi>.
    Found 8-bit register for signal <i_lo>.
    Found 1-bit register for signal <i_valid>.
    Found 16-bit register for signal <stage_a>.
    Found 1-bit register for signal <stage_a_end>.
    Found 16-bit register for signal <stage_b>.
    Found 1-bit register for signal <valid_out_reg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  83 D-type flip-flop(s).
Unit <inputcontrol> synthesized.


Synthesizing Unit <reconst>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/reconst.vhd.
WARNING:Xst:646 - Signal <pt_ext_comb4<0>> is assigned but never used.
WARNING:Xst:646 - Signal <pid_stage1a> is assigned but never used.
WARNING:Xst:646 - Signal <pt_raw_stage4<20:17>> is assigned but never used.
WARNING:Xst:646 - Signal <a_ext_comb2<1:0>> is assigned but never used.
INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal <ready_sreg<7>> and currently occupies 7 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal <valid_sreg<7>> and currently occupies 7 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <ready_stage4> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <valid_stage4> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 7-bit shift register for signal <track_sreg<7><41>>.
    Found 7-bit shift register for signal <track_sreg<7><40>>.
    Found 7-bit shift register for signal <track_sreg<7><39>>.
    Found 7-bit shift register for signal <track_sreg<7><38>>.
    Found 7-bit shift register for signal <track_sreg<7><37>>.
    Found 7-bit shift register for signal <track_sreg<7><36>>.
    Found 7-bit shift register for signal <track_sreg<7><35>>.
    Found 7-bit shift register for signal <track_sreg<7><34>>.
    Found 7-bit shift register for signal <track_sreg<7><33>>.
    Found 7-bit shift register for signal <track_sreg<7><32>>.
    Found 7-bit shift register for signal <track_sreg<7><31>>.
    Found 7-bit shift register for signal <track_sreg<7><30>>.
    Found 7-bit shift register for signal <track_sreg<7><29>>.
    Found 7-bit shift register for signal <track_sreg<7><28>>.
    Found 7-bit shift register for signal <track_sreg<7><27>>.
    Found 7-bit shift register for signal <track_sreg<7><26>>.
    Found 7-bit shift register for signal <track_sreg<7><25>>.
    Found 7-bit shift register for signal <track_sreg<7><24>>.
    Found 7-bit shift register for signal <track_sreg<7><23>>.
    Found 7-bit shift register for signal <track_sreg<7><22>>.
    Found 7-bit shift register for signal <track_sreg<7><21>>.
    Found 7-bit shift register for signal <track_sreg<7><20>>.
    Found 7-bit shift register for signal <track_sreg<7><19>>.
    Found 7-bit shift register for signal <track_sreg<7><18>>.
    Found 7-bit shift register for signal <track_sreg<7><17>>.
    Found 7-bit shift register for signal <track_sreg<7><16>>.
    Found 7-bit shift register for signal <track_sreg<7><15>>.
    Found 7-bit shift register for signal <track_sreg<7><14>>.
    Found 7-bit shift register for signal <track_sreg<7><13>>.
    Found 7-bit shift register for signal <track_sreg<7><12>>.
    Found 7-bit shift register for signal <track_sreg<7><11>>.
    Found 7-bit shift register for signal <track_sreg<7><10>>.
    Found 7-bit shift register for signal <track_sreg<7><9>>.
    Found 7-bit shift register for signal <track_sreg<7><8>>.
    Found 7-bit shift register for signal <track_sreg<7><7>>.
    Found 7-bit shift register for signal <track_sreg<7><6>>.
    Found 7-bit shift register for signal <track_sreg<7><5>>.
    Found 7-bit shift register for signal <track_sreg<7><4>>.
    Found 7-bit shift register for signal <track_sreg<7><3>>.
    Found 7-bit shift register for signal <track_sreg<7><2>>.
    Found 7-bit shift register for signal <track_sreg<7><1>>.
    Found 7-bit shift register for signal <track_sreg<7><0>>.
    Found 12-bit adder for signal <$n0000> created at line 206.
    Found 18-bit adder for signal <$n0001> created at line 198.
    Found 17-bit subtractor for signal <$n0002> created at line 206.
    Found 18-bit adder for signal <$n0004>.
    Found 18-bit adder for signal <$n0005>.
    Found 18-bit adder for signal <$n0006>.
    Found 18-bit adder for signal <$n0007>.
    Found 18-bit adder for signal <a_full_comb2>.
    Found 16-bit register for signal <a_stage3>.
    Found 78-bit register for signal <acoeff_stage1a>.
    Found 108-bit register for signal <ai_stage2>.
    Found 13-bit register for signal <c1_stage3>.
    Found 3-bit shift register for signal <mask_id_stage2>.
    Found 21-bit register for signal <pt_raw_stage4>.
    Found 7-bit register for signal <ready_sreg<7:1>>.
    Found 1-bit register for signal <ready_stage0>.
    Found 1-bit register for signal <ready_stage1a>.
    Found 1-bit register for signal <ready_stage1b>.
    Found 1-bit register for signal <ready_stage2>.
    Found 1-bit register for signal <ready_stage3>.
    Found 1-bit register for signal <ready_stage4>.
    Found 42-bit register for signal <track_stage0>.
    Found 5-bit shift register for signal <track_stage4>.
    Found 7-bit register for signal <valid_sreg<7:1>>.
    Found 1-bit register for signal <valid_stage0>.
    Found 1-bit register for signal <valid_stage1a>.
    Found 1-bit register for signal <valid_stage1b>.
    Found 1-bit register for signal <valid_stage2>.
    Found 1-bit register for signal <valid_stage3>.
    Found 1-bit register for signal <valid_stage4>.
    Found 78-bit register for signal <ys_stage1a>.
    Found 35 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 382 D-type flip-flop(s).
	inferred   8 Adder/Subtracter(s).
	inferred  35 Multiplexer(s).
	inferred  89 Shift register(s).
Unit <reconst> synthesized.


Synthesizing Unit <unique>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/unique.vhd.
Unit <unique> synthesized.


Synthesizing Unit <match23>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd.
    Found 1-bit register for signal <all_ready>.
    Found 10 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <match23> synthesized.


Synthesizing Unit <match22>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd.
    Found 1-bit register for signal <all_ready>.
    Found 10 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <match22> synthesized.


Synthesizing Unit <match>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/match.vhd.
    Found 1-bit register for signal <all_ready>.
    Found 10 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <match> synthesized.


Synthesizing Unit <z_channel21>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel21> synthesized.


Synthesizing Unit <z_channel20>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel20> synthesized.


Synthesizing Unit <z_channel19>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel19> synthesized.


Synthesizing Unit <z_channel18>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel18> synthesized.


Synthesizing Unit <z_channel17>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel17> synthesized.


Synthesizing Unit <z_channel16>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel16> synthesized.


Synthesizing Unit <z_channel15>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel15> synthesized.


Synthesizing Unit <z_channel14>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel14> synthesized.


Synthesizing Unit <z_channel13>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel13> synthesized.


Synthesizing Unit <z_channel12>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel12> synthesized.


Synthesizing Unit <z_channel11>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel11> synthesized.


Synthesizing Unit <z_channel10>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel10> synthesized.


Synthesizing Unit <z_channel9>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel9> synthesized.


Synthesizing Unit <z_channel8>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel8> synthesized.


Synthesizing Unit <z_channel7>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel7> synthesized.


Synthesizing Unit <z_channel6>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel6> synthesized.


Synthesizing Unit <z_channel5>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel5> synthesized.


Synthesizing Unit <z_channel>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd.
    Found 64x7-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 7-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in>      | high     |
    | address            | connected to signal <addr_in>       |          |
    | dual address       | connected to signal <addr_out_i>    |          |
    | data in            | connected to signal <a_in>          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <a_out>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 6-bit up counter for signal <addr2_cnt>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
Unit <z_channel> synthesized.


Synthesizing Unit <input4>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input4> synthesized.


Synthesizing Unit <input3>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input3> synthesized.


Synthesizing Unit <input2>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input2> synthesized.


Synthesizing Unit <input1>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input1> synthesized.


Synthesizing Unit <input0>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input0> synthesized.


Synthesizing Unit <input>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/input.vhd.
    Found 64x21-bit dual-port distributed RAM for signal <ram_block>.
    -----------------------------------------------------------------------
    | aspect ratio       | 64-word x 21-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_out_int> | high     |
    | address            | connected to signal <addr_cnt>      |          |
    | dual address       | connected to signal <mem_addr>      |          |
    | data in            | connected to internal node          |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 7-bit register for signal <a_out_reg>.
    Found 6-bit up counter for signal <addr_cnt>.
    Found 6-bit register for signal <addr_out_reg>.
    Found 1-bit register for signal <valid_out_reg>.
    Found 10-bit register for signal <y_out_reg>.
    Found 13-bit adder for signal <ys>.
    Found 4-bit register for signal <z_out_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Counter(s).
	inferred  28 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <input> synthesized.


Synthesizing Unit <toplevel>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/toplevel.vhd.
Unit <toplevel> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# LUT RAMs                         : 146
 64x21-bit dual-port distributed RAM: 6
 64x7-bit dual-port distributed RAM: 18
 64x26-bit dual-port distributed RAM: 108
 8x52-bit dual-port distributed RAM: 12
 16x52-bit dual-port distributed RAM: 2
# ROMs                             : 13
 77x11-bit ROM                     : 1
 78x11-bit ROM                     : 1
 80x11-bit ROM                     : 4
 22x13-bit ROM                     : 7
# Multipliers                      : 15
 9x9-bit multiplier                : 6
 7x8-bit multiplier                : 6
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 405
 17-bit subtractor                 : 1
 18-bit adder                      : 6
 12-bit adder                      : 1
 8-bit subtractor                  : 6
 8-bit adder                       : 6
 11-bit adder                      : 6
 13-bit adder                      : 12
 6-bit adder                       : 13
 7-bit subtractor                  : 9
 10-bit subtractor                 : 18
 10-bit adder                      : 18
 33-bit adder                      : 10
 32-bit adder                      : 30
 19-bit adder                      : 6
 1-bit adder carry out             : 10
 5-bit adder                       : 109
 3-bit adder                       : 127
 4-bit subtractor                  : 3
 4-bit adder                       : 4
 2-bit adder                       : 10
# Counters                         : 52
 6-bit up counter                  : 24
 3-bit up counter                  : 24
 4-bit up counter                  : 4
# Registers                        : 955
 6-bit register                    : 312
 4-bit register                    : 8
 7-bit register                    : 6
 10-bit register                   : 150
 1-bit register                    : 201
 21-bit register                   : 1
 16-bit register                   : 25
 18-bit register                   : 6
 13-bit register                   : 13
 32-bit register                   : 12
 8-bit register                    : 24
 2-bit register                    : 6
 3-bit register                    : 174
 42-bit register                   : 11
 19-bit register                   : 6
# Shift Registers                  : 89
 3-bit shift register              : 5
 5-bit shift register              : 42
 7-bit shift register              : 42
# Comparators                      : 1489
 10-bit comparator lessequal       : 144
 6-bit comparator not equal        : 54
 10-bit comparator greater         : 135
 3-bit comparator greater          : 135
 10-bit comparator less            : 180
 3-bit comparator greatequal       : 9
 7-bit comparator greater          : 90
 4-bit comparator equal            : 3
 4-bit comparator less             : 9
 3-bit comparator not equal        : 12
 7-bit comparator less             : 103
 3-bit comparator equal            : 334
 3-bit comparator less             : 190
 4-bit comparator not equal        : 2
 6-bit comparator equal            : 84
 32-bit comparator greatequal      : 5
# Multiplexers                     : 665
 7-bit 2-to-1 multiplexer          : 9
 3-bit 2-to-1 multiplexer          : 117
 17-bit 2-to-1 multiplexer         : 1
 18-bit 2-to-1 multiplexer         : 1
 6-bit 4-to-1 multiplexer          : 144
 3-bit 4-to-1 multiplexer          : 144
 10-bit 4-to-1 multiplexer         : 144
 6-bit 2-to-1 multiplexer          : 54
 33-bit 2-to-1 multiplexer         : 20
 32-bit 2-to-1 multiplexer         : 30
 42-bit 2-to-1 multiplexer         : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "cg_fifo_dc.ngo" is up to date.
Launcher: "cg_divide.ngo" is up to date.
Loading core <cg_fifo_dc> for timing and area information for instance <fifo_dc_inst>.
Loading core <cg_divide> for timing and area information for instance <divide_inst>.
WARNING:Xst:1291 - FF/Latch <pt_raw_stage4_20> is unconnected in block <reconst>.
WARNING:Xst:1291 - FF/Latch <pt_raw_stage4_17> is unconnected in block <reconst>.
WARNING:Xst:1291 - FF/Latch <pt_raw_stage4_18> is unconnected in block <reconst>.
WARNING:Xst:1291 - FF/Latch <pt_raw_stage4_19> is unconnected in block <reconst>.
WARNING:Xst:1710 - FF/Latch  <acoeff_stage1a_4_12> (without init value) is constant in block <reconst>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <acoeff_stage1a_5_12> (without init value) is constant in block <reconst>.

Optimizing unit <toplevel> ...

Optimizing unit <zch_table> ...

Optimizing unit <zch_table39> ...

Optimizing unit <zch_table40> ...

Optimizing unit <zch_table41> ...

Optimizing unit <zch_table42> ...

Optimizing unit <zch_table43> ...

Optimizing unit <zch_table44> ...

Optimizing unit <zch_table45> ...

Optimizing unit <zch_table46> ...

Optimizing unit <zch_table47> ...

Optimizing unit <zch_table48> ...

Optimizing unit <zch_table49> ...

Optimizing unit <zch_table50> ...

Optimizing unit <zch_table51> ...

Optimizing unit <zch_table52> ...

Optimizing unit <zch_table53> ...

Optimizing unit <zch_table54> ...

Optimizing unit <zch_table55> ...

Optimizing unit <mask_id_lut> ...

Optimizing unit <inputcontrol> ...

Optimizing unit <proj_y> ...

Optimizing unit <proj_y25> ...

Optimizing unit <proj_y28> ...

Optimizing unit <proj_y31> ...

Optimizing unit <proj_y34> ...

Optimizing unit <proj_y37> ...

Optimizing unit <mult_wrapper> ...

Optimizing unit <reconst> ...

Optimizing unit <buffer_merger> ...

Optimizing unit <sorter> ...

Optimizing unit <matching_memory> ...

Optimizing unit <matching_logic> ...

Optimizing unit <matching_logic56> ...

Optimizing unit <matching_logic57> ...

Optimizing unit <uniquifier> ...

Optimizing unit <uniquifier58> ...

Optimizing unit <uniquifier59> ...

Optimizing unit <input> ...

Optimizing unit <input0> ...

Optimizing unit <input1> ...

Optimizing unit <input2> ...

Optimizing unit <input3> ...

Optimizing unit <input4> ...

Optimizing unit <match> ...

Optimizing unit <match22> ...

Optimizing unit <match23> ...

Optimizing unit <seed_merger> ...

Optimizing unit <zch_merger> ...

Optimizing unit <zch_resorter> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/xilinx6.2i.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <input_inst5_Mram_ram_block_inst_ramx1d_44> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst5_Mram_ram_block_inst_ramx1d_43> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst5_Mram_ram_block_inst_ramx1d_42> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst5_Mram_ram_block_inst_ramx1d_41> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst5_Mram_ram_block_inst_ramx1d_40> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst5_Mram_ram_block_inst_ramx1d_39> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst5_Mram_ram_block_inst_ramx1d_45> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst5_Mram_ram_block_inst_ramx1d_46> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst4_Mram_ram_block_inst_ramx1d_44> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst4_Mram_ram_block_inst_ramx1d_43> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst4_Mram_ram_block_inst_ramx1d_42> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst4_Mram_ram_block_inst_ramx1d_41> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst4_Mram_ram_block_inst_ramx1d_40> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst4_Mram_ram_block_inst_ramx1d_45> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst4_Mram_ram_block_inst_ramx1d_46> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst4_Mram_ram_block_inst_ramx1d_39> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst3_Mram_ram_block_inst_ramx1d_44> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst3_Mram_ram_block_inst_ramx1d_43> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst3_Mram_ram_block_inst_ramx1d_42> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst3_Mram_ram_block_inst_ramx1d_41> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst3_Mram_ram_block_inst_ramx1d_40> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst3_Mram_ram_block_inst_ramx1d_45> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst3_Mram_ram_block_inst_ramx1d_46> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst3_Mram_ram_block_inst_ramx1d_39> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst2_Mram_ram_block_inst_ramx1d_44> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst2_Mram_ram_block_inst_ramx1d_43> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst2_Mram_ram_block_inst_ramx1d_42> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst2_Mram_ram_block_inst_ramx1d_41> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst2_Mram_ram_block_inst_ramx1d_40> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst2_Mram_ram_block_inst_ramx1d_45> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst2_Mram_ram_block_inst_ramx1d_46> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst2_Mram_ram_block_inst_ramx1d_39> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst1_Mram_ram_block_inst_ramx1d_44> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst1_Mram_ram_block_inst_ramx1d_43> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst1_Mram_ram_block_inst_ramx1d_42> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst1_Mram_ram_block_inst_ramx1d_41> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst1_Mram_ram_block_inst_ramx1d_40> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst1_Mram_ram_block_inst_ramx1d_45> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst1_Mram_ram_block_inst_ramx1d_46> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst1_Mram_ram_block_inst_ramx1d_39> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst0_Mram_ram_block_inst_ramx1d_44> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst0_Mram_ram_block_inst_ramx1d_43> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst0_Mram_ram_block_inst_ramx1d_42> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst0_Mram_ram_block_inst_ramx1d_41> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst0_Mram_ram_block_inst_ramx1d_40> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst0_Mram_ram_block_inst_ramx1d_45> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst0_Mram_ram_block_inst_ramx1d_46> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <input_inst0_Mram_ram_block_inst_ramx1d_39> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_0> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_1> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_2> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_3> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_4> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_5> is unconnected in block <toplevel>.
WARNING:Xst:1291 - FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_6> is unconnected in block <toplevel>.
Building and optimizing final netlist ...
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst01_matching_memory11_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst02_matching_memory12_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst03_matching_memory13_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst11_matching_memory11_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst12_matching_memory12_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst13_matching_memory13_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst21_matching_memory11_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst22_matching_memory12_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_20> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_21> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_22> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_23> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_24> is unconnected in block <toplevel>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <match_inst23_matching_memory13_Mram_ram_block_b_inst_ramx1d_25> is unconnected in block <toplevel>.
Register match_inst22_matching_memory15_reg_last_5 equivalent to match_inst23_matching_memory15_reg_last_5 has been removed
Register match_inst21_matching_memory15_reg_last_5 equivalent to match_inst23_matching_memory15_reg_last_5 has been removed
Register match_inst22_matching_memory15_reg_last_4 equivalent to match_inst23_matching_memory15_reg_last_4 has been removed
Register match_inst21_matching_memory15_reg_last_4 equivalent to match_inst23_matching_memory15_reg_last_4 has been removed
Register match_inst22_matching_memory15_reg_last_3 equivalent to match_inst23_matching_memory15_reg_last_3 has been removed
Register match_inst21_matching_memory15_reg_last_3 equivalent to match_inst23_matching_memory15_reg_last_3 has been removed
Register match_inst22_matching_memory15_reg_last_0 equivalent to match_inst23_matching_memory15_reg_last_0 has been removed
Register match_inst21_matching_memory15_reg_last_0 equivalent to match_inst23_matching_memory15_reg_last_0 has been removed
Register match_inst22_matching_memory15_reg_last_1 equivalent to match_inst23_matching_memory15_reg_last_1 has been removed
Register match_inst21_matching_memory15_reg_last_1 equivalent to match_inst23_matching_memory15_reg_last_1 has been removed
Register match_inst22_matching_memory15_reg_last_2 equivalent to match_inst23_matching_memory15_reg_last_2 has been removed
Register match_inst21_matching_memory15_reg_last_2 equivalent to match_inst23_matching_memory15_reg_last_2 has been removed
Register match_inst22_matching_memory14_reg_last_5 equivalent to match_inst23_matching_memory14_reg_last_5 has been removed
Register match_inst21_matching_memory14_reg_last_5 equivalent to match_inst23_matching_memory14_reg_last_5 has been removed
Register match_inst22_matching_memory14_reg_last_4 equivalent to match_inst23_matching_memory14_reg_last_4 has been removed
Register match_inst21_matching_memory14_reg_last_4 equivalent to match_inst23_matching_memory14_reg_last_4 has been removed
Register match_inst22_matching_memory14_reg_last_3 equivalent to match_inst23_matching_memory14_reg_last_3 has been removed
Register match_inst21_matching_memory14_reg_last_3 equivalent to match_inst23_matching_memory14_reg_last_3 has been removed
Register match_inst22_matching_memory14_reg_last_0 equivalent to match_inst23_matching_memory14_reg_last_0 has been removed
Register match_inst21_matching_memory14_reg_last_0 equivalent to match_inst23_matching_memory14_reg_last_0 has been removed
Register match_inst22_matching_memory14_reg_last_1 equivalent to match_inst23_matching_memory14_reg_last_1 has been removed
Register match_inst21_matching_memory14_reg_last_1 equivalent to match_inst23_matching_memory14_reg_last_1 has been removed
Register match_inst22_matching_memory14_reg_last_2 equivalent to match_inst23_matching_memory14_reg_last_2 has been removed
Register match_inst21_matching_memory14_reg_last_2 equivalent to match_inst23_matching_memory14_reg_last_2 has been removed
Register match_inst22_matching_memory13_reg_last_5 equivalent to match_inst23_matching_memory13_reg_last_5 has been removed
Register match_inst21_matching_memory13_reg_last_5 equivalent to match_inst23_matching_memory13_reg_last_5 has been removed
Register match_inst22_matching_memory13_reg_last_4 equivalent to match_inst23_matching_memory13_reg_last_4 has been removed
Register match_inst21_matching_memory13_reg_last_4 equivalent to match_inst23_matching_memory13_reg_last_4 has been removed
Register match_inst22_matching_memory13_reg_last_3 equivalent to match_inst23_matching_memory13_reg_last_3 has been removed
Register match_inst21_matching_memory13_reg_last_3 equivalent to match_inst23_matching_memory13_reg_last_3 has been removed
Register match_inst22_matching_memory13_reg_last_0 equivalent to match_inst23_matching_memory13_reg_last_0 has been removed
Register match_inst21_matching_memory13_reg_last_0 equivalent to match_inst23_matching_memory13_reg_last_0 has been removed
Register match_inst22_matching_memory13_reg_last_1 equivalent to match_inst23_matching_memory13_reg_last_1 has been removed
Register match_inst21_matching_memory13_reg_last_1 equivalent to match_inst23_matching_memory13_reg_last_1 has been removed
Register match_inst22_matching_memory13_reg_last_2 equivalent to match_inst23_matching_memory13_reg_last_2 has been removed
Register match_inst21_matching_memory13_reg_last_2 equivalent to match_inst23_matching_memory13_reg_last_2 has been removed
Register match_inst22_matching_memory12_reg_last_5 equivalent to match_inst23_matching_memory12_reg_last_5 has been removed
Register match_inst21_matching_memory12_reg_last_5 equivalent to match_inst23_matching_memory12_reg_last_5 has been removed
Register match_inst22_matching_memory12_reg_last_4 equivalent to match_inst23_matching_memory12_reg_last_4 has been removed
Register match_inst21_matching_memory12_reg_last_4 equivalent to match_inst23_matching_memory12_reg_last_4 has been removed
Register match_inst22_matching_memory12_reg_last_3 equivalent to match_inst23_matching_memory12_reg_last_3 has been removed
Register match_inst21_matching_memory12_reg_last_3 equivalent to match_inst23_matching_memory12_reg_last_3 has been removed
Register match_inst22_matching_memory12_reg_last_0 equivalent to match_inst23_matching_memory12_reg_last_0 has been removed
Register match_inst21_matching_memory12_reg_last_0 equivalent to match_inst23_matching_memory12_reg_last_0 has been removed
Register match_inst22_matching_memory12_reg_last_1 equivalent to match_inst23_matching_memory12_reg_last_1 has been removed
Register match_inst21_matching_memory12_reg_last_1 equivalent to match_inst23_matching_memory12_reg_last_1 has been removed
Register match_inst22_matching_memory12_reg_last_2 equivalent to match_inst23_matching_memory12_reg_last_2 has been removed
Register match_inst21_matching_memory12_reg_last_2 equivalent to match_inst23_matching_memory12_reg_last_2 has been removed
Register match_inst22_matching_memory11_reg_last_5 equivalent to match_inst23_matching_memory11_reg_last_5 has been removed
Register match_inst21_matching_memory11_reg_last_5 equivalent to match_inst23_matching_memory11_reg_last_5 has been removed
Register match_inst22_matching_memory11_reg_last_4 equivalent to match_inst23_matching_memory11_reg_last_4 has been removed
Register match_inst21_matching_memory11_reg_last_4 equivalent to match_inst23_matching_memory11_reg_last_4 has been removed
Register match_inst22_matching_memory11_reg_last_3 equivalent to match_inst23_matching_memory11_reg_last_3 has been removed
Register match_inst21_matching_memory11_reg_last_3 equivalent to match_inst23_matching_memory11_reg_last_3 has been removed
Register match_inst22_matching_memory11_reg_last_0 equivalent to match_inst23_matching_memory11_reg_last_0 has been removed
Register match_inst21_matching_memory11_reg_last_0 equivalent to match_inst23_matching_memory11_reg_last_0 has been removed
Register match_inst22_matching_memory11_reg_last_1 equivalent to match_inst23_matching_memory11_reg_last_1 has been removed
Register match_inst21_matching_memory11_reg_last_1 equivalent to match_inst23_matching_memory11_reg_last_1 has been removed
Register match_inst22_matching_memory11_reg_last_2 equivalent to match_inst23_matching_memory11_reg_last_2 has been removed
Register match_inst21_matching_memory11_reg_last_2 equivalent to match_inst23_matching_memory11_reg_last_2 has been removed
Register match_inst22_matching_memory10_reg_last_5 equivalent to match_inst23_matching_memory10_reg_last_5 has been removed
Register match_inst21_matching_memory10_reg_last_5 equivalent to match_inst23_matching_memory10_reg_last_5 has been removed
Register match_inst22_matching_memory10_reg_last_4 equivalent to match_inst23_matching_memory10_reg_last_4 has been removed
Register match_inst21_matching_memory10_reg_last_4 equivalent to match_inst23_matching_memory10_reg_last_4 has been removed
Register match_inst22_matching_memory10_reg_last_3 equivalent to match_inst23_matching_memory10_reg_last_3 has been removed
Register match_inst21_matching_memory10_reg_last_3 equivalent to match_inst23_matching_memory10_reg_last_3 has been removed
Register match_inst22_matching_memory10_reg_last_0 equivalent to match_inst23_matching_memory10_reg_last_0 has been removed
Register match_inst21_matching_memory10_reg_last_0 equivalent to match_inst23_matching_memory10_reg_last_0 has been removed
Register match_inst22_matching_memory10_reg_last_1 equivalent to match_inst23_matching_memory10_reg_last_1 has been removed
Register match_inst21_matching_memory10_reg_last_1 equivalent to match_inst23_matching_memory10_reg_last_1 has been removed
Register match_inst22_matching_memory10_reg_last_2 equivalent to match_inst23_matching_memory10_reg_last_2 has been removed
Register match_inst21_matching_memory10_reg_last_2 equivalent to match_inst23_matching_memory10_reg_last_2 has been removed
Register match_inst12_matching_memory15_reg_last_5 equivalent to match_inst13_matching_memory15_reg_last_5 has been removed
Register match_inst11_matching_memory15_reg_last_5 equivalent to match_inst13_matching_memory15_reg_last_5 has been removed
Register match_inst12_matching_memory15_reg_last_4 equivalent to match_inst13_matching_memory15_reg_last_4 has been removed
Register match_inst11_matching_memory15_reg_last_4 equivalent to match_inst13_matching_memory15_reg_last_4 has been removed
Register match_inst12_matching_memory15_reg_last_3 equivalent to match_inst13_matching_memory15_reg_last_3 has been removed
Register match_inst11_matching_memory15_reg_last_3 equivalent to match_inst13_matching_memory15_reg_last_3 has been removed
Register match_inst12_matching_memory15_reg_last_0 equivalent to match_inst13_matching_memory15_reg_last_0 has been removed
Register match_inst11_matching_memory15_reg_last_0 equivalent to match_inst13_matching_memory15_reg_last_0 has been removed
Register match_inst12_matching_memory15_reg_last_1 equivalent to match_inst13_matching_memory15_reg_last_1 has been removed
Register match_inst11_matching_memory15_reg_last_1 equivalent to match_inst13_matching_memory15_reg_last_1 has been removed
Register match_inst12_matching_memory15_reg_last_2 equivalent to match_inst13_matching_memory15_reg_last_2 has been removed
Register match_inst11_matching_memory15_reg_last_2 equivalent to match_inst13_matching_memory15_reg_last_2 has been removed
Register match_inst12_matching_memory14_reg_last_5 equivalent to match_inst13_matching_memory14_reg_last_5 has been removed
Register match_inst11_matching_memory14_reg_last_5 equivalent to match_inst13_matching_memory14_reg_last_5 has been removed
Register match_inst12_matching_memory14_reg_last_4 equivalent to match_inst13_matching_memory14_reg_last_4 has been removed
Register match_inst11_matching_memory14_reg_last_4 equivalent to match_inst13_matching_memory14_reg_last_4 has been removed
Register match_inst12_matching_memory14_reg_last_3 equivalent to match_inst13_matching_memory14_reg_last_3 has been removed
Register match_inst11_matching_memory14_reg_last_3 equivalent to match_inst13_matching_memory14_reg_last_3 has been removed
Register match_inst12_matching_memory14_reg_last_0 equivalent to match_inst13_matching_memory14_reg_last_0 has been removed
Register match_inst11_matching_memory14_reg_last_0 equivalent to match_inst13_matching_memory14_reg_last_0 has been removed
Register match_inst12_matching_memory14_reg_last_1 equivalent to match_inst13_matching_memory14_reg_last_1 has been removed
Register match_inst11_matching_memory14_reg_last_1 equivalent to match_inst13_matching_memory14_reg_last_1 has been removed
Register match_inst12_matching_memory14_reg_last_2 equivalent to match_inst13_matching_memory14_reg_last_2 has been removed
Register match_inst11_matching_memory14_reg_last_2 equivalent to match_inst13_matching_memory14_reg_last_2 has been removed
Register match_inst12_matching_memory13_reg_last_5 equivalent to match_inst13_matching_memory13_reg_last_5 has been removed
Register match_inst11_matching_memory13_reg_last_5 equivalent to match_inst13_matching_memory13_reg_last_5 has been removed
Register match_inst12_matching_memory13_reg_last_4 equivalent to match_inst13_matching_memory13_reg_last_4 has been removed
Register match_inst11_matching_memory13_reg_last_4 equivalent to match_inst13_matching_memory13_reg_last_4 has been removed
Register match_inst12_matching_memory13_reg_last_3 equivalent to match_inst13_matching_memory13_reg_last_3 has been removed
Register match_inst11_matching_memory13_reg_last_3 equivalent to match_inst13_matching_memory13_reg_last_3 has been removed
Register match_inst12_matching_memory13_reg_last_0 equivalent to match_inst13_matching_memory13_reg_last_0 has been removed
Register match_inst11_matching_memory13_reg_last_0 equivalent to match_inst13_matching_memory13_reg_last_0 has been removed
Register match_inst12_matching_memory13_reg_last_1 equivalent to match_inst13_matching_memory13_reg_last_1 has been removed
Register match_inst11_matching_memory13_reg_last_1 equivalent to match_inst13_matching_memory13_reg_last_1 has been removed
Register match_inst12_matching_memory13_reg_last_2 equivalent to match_inst13_matching_memory13_reg_last_2 has been removed
Register match_inst11_matching_memory13_reg_last_2 equivalent to match_inst13_matching_memory13_reg_last_2 has been removed
Register match_inst12_matching_memory12_reg_last_5 equivalent to match_inst13_matching_memory12_reg_last_5 has been removed
Register match_inst11_matching_memory12_reg_last_5 equivalent to match_inst13_matching_memory12_reg_last_5 has been removed
Register match_inst12_matching_memory12_reg_last_4 equivalent to match_inst13_matching_memory12_reg_last_4 has been removed
Register match_inst11_matching_memory12_reg_last_4 equivalent to match_inst13_matching_memory12_reg_last_4 has been removed
Register match_inst12_matching_memory12_reg_last_3 equivalent to match_inst13_matching_memory12_reg_last_3 has been removed
Register match_inst11_matching_memory12_reg_last_3 equivalent to match_inst13_matching_memory12_reg_last_3 has been removed
Register match_inst12_matching_memory12_reg_last_0 equivalent to match_inst13_matching_memory12_reg_last_0 has been removed
Register match_inst11_matching_memory12_reg_last_0 equivalent to match_inst13_matching_memory12_reg_last_0 has been removed
Register match_inst12_matching_memory12_reg_last_1 equivalent to match_inst13_matching_memory12_reg_last_1 has been removed
Register match_inst11_matching_memory12_reg_last_1 equivalent to match_inst13_matching_memory12_reg_last_1 has been removed
Register match_inst12_matching_memory12_reg_last_2 equivalent to match_inst13_matching_memory12_reg_last_2 has been removed
Register match_inst11_matching_memory12_reg_last_2 equivalent to match_inst13_matching_memory12_reg_last_2 has been removed
Register match_inst12_matching_memory11_reg_last_5 equivalent to match_inst13_matching_memory11_reg_last_5 has been removed
Register match_inst11_matching_memory11_reg_last_5 equivalent to match_inst13_matching_memory11_reg_last_5 has been removed
Register match_inst12_matching_memory11_reg_last_4 equivalent to match_inst13_matching_memory11_reg_last_4 has been removed
Register match_inst11_matching_memory11_reg_last_4 equivalent to match_inst13_matching_memory11_reg_last_4 has been removed
Register match_inst12_matching_memory11_reg_last_3 equivalent to match_inst13_matching_memory11_reg_last_3 has been removed
Register match_inst11_matching_memory11_reg_last_3 equivalent to match_inst13_matching_memory11_reg_last_3 has been removed
Register match_inst12_matching_memory11_reg_last_0 equivalent to match_inst13_matching_memory11_reg_last_0 has been removed
Register match_inst11_matching_memory11_reg_last_0 equivalent to match_inst13_matching_memory11_reg_last_0 has been removed
Register match_inst12_matching_memory11_reg_last_1 equivalent to match_inst13_matching_memory11_reg_last_1 has been removed
Register match_inst11_matching_memory11_reg_last_1 equivalent to match_inst13_matching_memory11_reg_last_1 has been removed
Register match_inst12_matching_memory11_reg_last_2 equivalent to match_inst13_matching_memory11_reg_last_2 has been removed
Register match_inst11_matching_memory11_reg_last_2 equivalent to match_inst13_matching_memory11_reg_last_2 has been removed
Register match_inst12_matching_memory10_reg_last_5 equivalent to match_inst13_matching_memory10_reg_last_5 has been removed
Register match_inst11_matching_memory10_reg_last_5 equivalent to match_inst13_matching_memory10_reg_last_5 has been removed
Register match_inst12_matching_memory10_reg_last_4 equivalent to match_inst13_matching_memory10_reg_last_4 has been removed
Register match_inst11_matching_memory10_reg_last_4 equivalent to match_inst13_matching_memory10_reg_last_4 has been removed
Register match_inst12_matching_memory10_reg_last_3 equivalent to match_inst13_matching_memory10_reg_last_3 has been removed
Register match_inst11_matching_memory10_reg_last_3 equivalent to match_inst13_matching_memory10_reg_last_3 has been removed
Register match_inst12_matching_memory10_reg_last_0 equivalent to match_inst13_matching_memory10_reg_last_0 has been removed
Register match_inst11_matching_memory10_reg_last_0 equivalent to match_inst13_matching_memory10_reg_last_0 has been removed
Register match_inst12_matching_memory10_reg_last_1 equivalent to match_inst13_matching_memory10_reg_last_1 has been removed
Register match_inst11_matching_memory10_reg_last_1 equivalent to match_inst13_matching_memory10_reg_last_1 has been removed
Register match_inst12_matching_memory10_reg_last_2 equivalent to match_inst13_matching_memory10_reg_last_2 has been removed
Register match_inst11_matching_memory10_reg_last_2 equivalent to match_inst13_matching_memory10_reg_last_2 has been removed
Register match_inst02_matching_memory15_reg_last_5 equivalent to match_inst03_matching_memory15_reg_last_5 has been removed
Register match_inst01_matching_memory15_reg_last_5 equivalent to match_inst03_matching_memory15_reg_last_5 has been removed
Register match_inst02_matching_memory15_reg_last_4 equivalent to match_inst03_matching_memory15_reg_last_4 has been removed
Register match_inst01_matching_memory15_reg_last_4 equivalent to match_inst03_matching_memory15_reg_last_4 has been removed
Register match_inst02_matching_memory15_reg_last_3 equivalent to match_inst03_matching_memory15_reg_last_3 has been removed
Register match_inst01_matching_memory15_reg_last_3 equivalent to match_inst03_matching_memory15_reg_last_3 has been removed
Register match_inst02_matching_memory15_reg_last_0 equivalent to match_inst03_matching_memory15_reg_last_0 has been removed
Register match_inst01_matching_memory15_reg_last_0 equivalent to match_inst03_matching_memory15_reg_last_0 has been removed
Register match_inst02_matching_memory15_reg_last_1 equivalent to match_inst03_matching_memory15_reg_last_1 has been removed
Register match_inst01_matching_memory15_reg_last_1 equivalent to match_inst03_matching_memory15_reg_last_1 has been removed
Register match_inst02_matching_memory15_reg_last_2 equivalent to match_inst03_matching_memory15_reg_last_2 has been removed
Register match_inst01_matching_memory15_reg_last_2 equivalent to match_inst03_matching_memory15_reg_last_2 has been removed
Register match_inst02_matching_memory14_reg_last_5 equivalent to match_inst03_matching_memory14_reg_last_5 has been removed
Register match_inst01_matching_memory14_reg_last_5 equivalent to match_inst03_matching_memory14_reg_last_5 has been removed
Register match_inst02_matching_memory14_reg_last_4 equivalent to match_inst03_matching_memory14_reg_last_4 has been removed
Register match_inst01_matching_memory14_reg_last_4 equivalent to match_inst03_matching_memory14_reg_last_4 has been removed
Register match_inst02_matching_memory14_reg_last_3 equivalent to match_inst03_matching_memory14_reg_last_3 has been removed
Register match_inst01_matching_memory14_reg_last_3 equivalent to match_inst03_matching_memory14_reg_last_3 has been removed
Register match_inst02_matching_memory14_reg_last_0 equivalent to match_inst03_matching_memory14_reg_last_0 has been removed
Register match_inst01_matching_memory14_reg_last_0 equivalent to match_inst03_matching_memory14_reg_last_0 has been removed
Register match_inst02_matching_memory14_reg_last_1 equivalent to match_inst03_matching_memory14_reg_last_1 has been removed
Register match_inst01_matching_memory14_reg_last_1 equivalent to match_inst03_matching_memory14_reg_last_1 has been removed
Register match_inst02_matching_memory14_reg_last_2 equivalent to match_inst03_matching_memory14_reg_last_2 has been removed
Register match_inst01_matching_memory14_reg_last_2 equivalent to match_inst03_matching_memory14_reg_last_2 has been removed
Register match_inst02_matching_memory13_reg_last_5 equivalent to match_inst03_matching_memory13_reg_last_5 has been removed
Register match_inst01_matching_memory13_reg_last_5 equivalent to match_inst03_matching_memory13_reg_last_5 has been removed
Register match_inst02_matching_memory13_reg_last_4 equivalent to match_inst03_matching_memory13_reg_last_4 has been removed
Register match_inst01_matching_memory13_reg_last_4 equivalent to match_inst03_matching_memory13_reg_last_4 has been removed
Register match_inst02_matching_memory13_reg_last_3 equivalent to match_inst03_matching_memory13_reg_last_3 has been removed
Register match_inst01_matching_memory13_reg_last_3 equivalent to match_inst03_matching_memory13_reg_last_3 has been removed
Register match_inst02_matching_memory13_reg_last_0 equivalent to match_inst03_matching_memory13_reg_last_0 has been removed
Register match_inst01_matching_memory13_reg_last_0 equivalent to match_inst03_matching_memory13_reg_last_0 has been removed
Register match_inst02_matching_memory13_reg_last_1 equivalent to match_inst03_matching_memory13_reg_last_1 has been removed
Register match_inst01_matching_memory13_reg_last_1 equivalent to match_inst03_matching_memory13_reg_last_1 has been removed
Register match_inst02_matching_memory13_reg_last_2 equivalent to match_inst03_matching_memory13_reg_last_2 has been removed
Register match_inst01_matching_memory13_reg_last_2 equivalent to match_inst03_matching_memory13_reg_last_2 has been removed
Register match_inst02_matching_memory12_reg_last_5 equivalent to match_inst03_matching_memory12_reg_last_5 has been removed
Register match_inst01_matching_memory12_reg_last_5 equivalent to match_inst03_matching_memory12_reg_last_5 has been removed
Register match_inst02_matching_memory12_reg_last_4 equivalent to match_inst03_matching_memory12_reg_last_4 has been removed
Register match_inst01_matching_memory12_reg_last_4 equivalent to match_inst03_matching_memory12_reg_last_4 has been removed
Register match_inst02_matching_memory12_reg_last_3 equivalent to match_inst03_matching_memory12_reg_last_3 has been removed
Register match_inst01_matching_memory12_reg_last_3 equivalent to match_inst03_matching_memory12_reg_last_3 has been removed
Register match_inst02_matching_memory12_reg_last_0 equivalent to match_inst03_matching_memory12_reg_last_0 has been removed
Register match_inst01_matching_memory12_reg_last_0 equivalent to match_inst03_matching_memory12_reg_last_0 has been removed
Register match_inst02_matching_memory12_reg_last_1 equivalent to match_inst03_matching_memory12_reg_last_1 has been removed
Register match_inst01_matching_memory12_reg_last_1 equivalent to match_inst03_matching_memory12_reg_last_1 has been removed
Register match_inst02_matching_memory12_reg_last_2 equivalent to match_inst03_matching_memory12_reg_last_2 has been removed
Register match_inst01_matching_memory12_reg_last_2 equivalent to match_inst03_matching_memory12_reg_last_2 has been removed
Register match_inst02_matching_memory11_reg_last_5 equivalent to match_inst03_matching_memory11_reg_last_5 has been removed
Register match_inst01_matching_memory11_reg_last_5 equivalent to match_inst03_matching_memory11_reg_last_5 has been removed
Register match_inst02_matching_memory11_reg_last_4 equivalent to match_inst03_matching_memory11_reg_last_4 has been removed
Register match_inst01_matching_memory11_reg_last_4 equivalent to match_inst03_matching_memory11_reg_last_4 has been removed
Register match_inst02_matching_memory11_reg_last_3 equivalent to match_inst03_matching_memory11_reg_last_3 has been removed
Register match_inst01_matching_memory11_reg_last_3 equivalent to match_inst03_matching_memory11_reg_last_3 has been removed
Register match_inst02_matching_memory11_reg_last_0 equivalent to match_inst03_matching_memory11_reg_last_0 has been removed
Register match_inst01_matching_memory11_reg_last_0 equivalent to match_inst03_matching_memory11_reg_last_0 has been removed
Register match_inst02_matching_memory11_reg_last_1 equivalent to match_inst03_matching_memory11_reg_last_1 has been removed
Register match_inst01_matching_memory11_reg_last_1 equivalent to match_inst03_matching_memory11_reg_last_1 has been removed
Register match_inst02_matching_memory11_reg_last_2 equivalent to match_inst03_matching_memory11_reg_last_2 has been removed
Register match_inst01_matching_memory11_reg_last_2 equivalent to match_inst03_matching_memory11_reg_last_2 has been removed
Register match_inst02_matching_memory10_reg_last_5 equivalent to match_inst03_matching_memory10_reg_last_5 has been removed
Register match_inst01_matching_memory10_reg_last_5 equivalent to match_inst03_matching_memory10_reg_last_5 has been removed
Register match_inst02_matching_memory10_reg_last_4 equivalent to match_inst03_matching_memory10_reg_last_4 has been removed
Register match_inst01_matching_memory10_reg_last_4 equivalent to match_inst03_matching_memory10_reg_last_4 has been removed
Register match_inst02_matching_memory10_reg_last_3 equivalent to match_inst03_matching_memory10_reg_last_3 has been removed
Register match_inst01_matching_memory10_reg_last_3 equivalent to match_inst03_matching_memory10_reg_last_3 has been removed
Register match_inst02_matching_memory10_reg_last_0 equivalent to match_inst03_matching_memory10_reg_last_0 has been removed
Register match_inst01_matching_memory10_reg_last_0 equivalent to match_inst03_matching_memory10_reg_last_0 has been removed
Register match_inst02_matching_memory10_reg_last_1 equivalent to match_inst03_matching_memory10_reg_last_1 has been removed
Register match_inst01_matching_memory10_reg_last_1 equivalent to match_inst03_matching_memory10_reg_last_1 has been removed
Register match_inst02_matching_memory10_reg_last_2 equivalent to match_inst03_matching_memory10_reg_last_2 has been removed
Register match_inst01_matching_memory10_reg_last_2 equivalent to match_inst03_matching_memory10_reg_last_2 has been removed
Found area constraint ratio of 100 (+ 5) on block toplevel, actual ratio is 145.
Optimizing block <toplevel> to meet ratio 100 (+ 5) of 19392 slices :
WARNING:Xst - Area constraint could not be met for block <toplevel>, final ratio is 142.
WARNING:Xst:382 - Register BU1253 is equivalent to BU1217
Register match_inst21_matching_memory15_invalid_reg equivalent to match_inst22_matching_memory15_invalid_reg has been removed
Register match_inst21_matching_memory14_invalid_reg equivalent to match_inst22_matching_memory14_invalid_reg has been removed
Register match_inst21_matching_memory13_invalid_reg equivalent to match_inst22_matching_memory13_invalid_reg has been removed
Register match_inst21_matching_memory12_invalid_reg equivalent to match_inst22_matching_memory12_invalid_reg has been removed
Register match_inst21_matching_memory11_invalid_reg equivalent to match_inst22_matching_memory11_invalid_reg has been removed
Register match_inst21_matching_memory10_invalid_reg equivalent to match_inst22_matching_memory10_invalid_reg has been removed
Register match_inst11_matching_memory15_invalid_reg equivalent to match_inst12_matching_memory15_invalid_reg has been removed
Register match_inst11_matching_memory14_invalid_reg equivalent to match_inst12_matching_memory14_invalid_reg has been removed
Register match_inst11_matching_memory13_invalid_reg equivalent to match_inst12_matching_memory13_invalid_reg has been removed
Register match_inst11_matching_memory12_invalid_reg equivalent to match_inst12_matching_memory12_invalid_reg has been removed
Register match_inst11_matching_memory11_invalid_reg equivalent to match_inst12_matching_memory11_invalid_reg has been removed
Register match_inst11_matching_memory10_invalid_reg equivalent to match_inst12_matching_memory10_invalid_reg has been removed
Register match_inst01_matching_memory15_invalid_reg equivalent to match_inst02_matching_memory15_invalid_reg has been removed
Register match_inst01_matching_memory14_invalid_reg equivalent to match_inst02_matching_memory14_invalid_reg has been removed
Register match_inst01_matching_memory13_invalid_reg equivalent to match_inst02_matching_memory13_invalid_reg has been removed
Register match_inst01_matching_memory12_invalid_reg equivalent to match_inst02_matching_memory12_invalid_reg has been removed
Register match_inst01_matching_memory11_invalid_reg equivalent to match_inst02_matching_memory11_invalid_reg has been removed
Register match_inst01_matching_memory10_invalid_reg equivalent to match_inst02_matching_memory10_invalid_reg has been removed
WARNING:Xst:382 - Register BU1253 is equivalent to BU1217
Register match_inst22_matching_memory15_invalid_reg equivalent to match_inst23_matching_memory15_invalid_reg has been removed
Register match_inst22_matching_memory14_invalid_reg equivalent to match_inst23_matching_memory14_invalid_reg has been removed
Register match_inst22_matching_memory13_invalid_reg equivalent to match_inst23_matching_memory13_invalid_reg has been removed
Register match_inst22_matching_memory12_invalid_reg equivalent to match_inst23_matching_memory12_invalid_reg has been removed
Register match_inst22_matching_memory11_invalid_reg equivalent to match_inst23_matching_memory11_invalid_reg has been removed
Register match_inst22_matching_memory10_invalid_reg equivalent to match_inst23_matching_memory10_invalid_reg has been removed
Register match_inst12_matching_memory15_invalid_reg equivalent to match_inst13_matching_memory15_invalid_reg has been removed
Register match_inst12_matching_memory14_invalid_reg equivalent to match_inst13_matching_memory14_invalid_reg has been removed
Register match_inst12_matching_memory13_invalid_reg equivalent to match_inst13_matching_memory13_invalid_reg has been removed
Register match_inst12_matching_memory12_invalid_reg equivalent to match_inst13_matching_memory12_invalid_reg has been removed
Register match_inst12_matching_memory11_invalid_reg equivalent to match_inst13_matching_memory11_invalid_reg has been removed
Register match_inst12_matching_memory10_invalid_reg equivalent to match_inst13_matching_memory10_invalid_reg has been removed
Register match_inst02_matching_memory15_invalid_reg equivalent to match_inst03_matching_memory15_invalid_reg has been removed
Register match_inst02_matching_memory14_invalid_reg equivalent to match_inst03_matching_memory14_invalid_reg has been removed
Register match_inst02_matching_memory13_invalid_reg equivalent to match_inst03_matching_memory13_invalid_reg has been removed
Register match_inst02_matching_memory12_invalid_reg equivalent to match_inst03_matching_memory12_invalid_reg has been removed
Register match_inst02_matching_memory11_invalid_reg equivalent to match_inst03_matching_memory11_invalid_reg has been removed
Register match_inst02_matching_memory10_invalid_reg equivalent to match_inst03_matching_memory10_invalid_reg has been removed
WARNING:Xst:382 - Register BU1253 is equivalent to BU1217
FlipFlop match_inst21_matching_memory11_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory11_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory11_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory11_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory11_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory11_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory11_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory11_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory11_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory11_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory11_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory11_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop unique_inst_zch_merger_i_rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop unique_inst_zch_merger_i_rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop unique_inst_zch_merger_i_rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop unique_inst_zch_merger_i_rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop unique_inst_zch_merger_i_rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop unique_inst_zch_merger_i_rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory13_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory13_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory13_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory15_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory14_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory15_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory14_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory15_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory14_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory10_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory12_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory10_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory10_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory12_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory12_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst23_matching_memory15_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory14_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory15_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory14_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory15_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory14_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory12_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory11_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory12_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory11_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory12_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory11_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory13_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst13_matching_memory13_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst03_matching_memory13_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory12_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory12_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory12_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory13_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory13_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory13_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory15_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory14_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory15_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory14_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory15_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory14_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory10_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory12_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory13_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory13_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory13_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory15_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory15_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory15_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory14_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory14_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory14_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory10_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory10_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory10_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory11_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory11_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory11_reg_a_1 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory10_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory10_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory12_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory12_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst23_matching_memory15_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory14_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory15_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory14_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory15_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory14_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory12_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory11_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory12_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory11_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory12_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory11_reg_b_2 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory13_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory13_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory15_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory14_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory15_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory14_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory15_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory14_reg_b_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory15_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory13_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory15_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory13_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory14_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory14_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory13_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory15_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory14_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory10_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory10_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory10_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory12_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory14_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory14_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory14_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory15_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory15_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory15_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory12_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory12_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory12_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory10_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory10_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory10_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory11_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory11_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory11_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory12_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory12_reg_a_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory13_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst13_matching_memory13_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst03_matching_memory13_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory12_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory12_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory12_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory13_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory13_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory13_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory15_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory14_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory15_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory14_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory15_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory14_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory10_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory12_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory10_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory10_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory12_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory12_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst23_matching_memory15_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory14_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory15_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory14_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory15_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory14_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory12_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory11_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory12_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory11_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory12_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory11_reg_b_3 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory13_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory13_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory15_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory14_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory15_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory14_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory15_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory14_reg_b_3 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory15_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory13_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory15_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory13_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory14_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory14_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory13_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory15_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory14_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory10_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory10_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory10_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory12_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst23_matching_memory14_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory14_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory14_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory15_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory15_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory15_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory13_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory13_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory13_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory13_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory13_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory15_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory15_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory12_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory12_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory12_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory15_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory15_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory15_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory14_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory14_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory14_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory14_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory14_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory10_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory10_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory10_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory10_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory10_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory10_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory10_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory10_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory10_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory11_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory11_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory11_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory11_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory11_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory11_reg_a_2 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory12_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory12_reg_a_2 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory13_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory13_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory15_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory14_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory15_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory14_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory15_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory14_reg_b_1 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory11_reg_b_1 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory13_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory13_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory13_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory12_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory12_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory12_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory15_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory13_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory15_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory13_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory14_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory14_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory13_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory15_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory14_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory10_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory10_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory10_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory13_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory13_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory13_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory15_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory14_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory15_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory14_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory15_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory14_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory10_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory12_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst01_matching_memory12_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory14_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory14_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory14_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory15_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory15_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory15_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst12_matching_memory13_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst02_matching_memory13_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst22_matching_memory13_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst12_matching_memory15_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory12_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory12_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory12_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst02_matching_memory15_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst22_matching_memory15_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst12_matching_memory14_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst02_matching_memory14_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst22_matching_memory14_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory10_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory10_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory10_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst12_matching_memory10_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst02_matching_memory10_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst22_matching_memory10_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory11_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory11_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory11_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst12_matching_memory11_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst02_matching_memory11_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst22_matching_memory11_reg_a_3 has been replicated 4 time(s)
FlipFlop match_inst21_matching_memory12_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory12_reg_a_3 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory10_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory10_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory12_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst11_matching_memory12_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory15_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory14_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory15_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory14_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory15_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory14_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory12_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory11_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory12_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst13_matching_memory11_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory12_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory11_reg_b_0 has been replicated 4 time(s)
FlipFlop match_inst22_matching_memory13_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory13_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory15_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory14_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory15_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory14_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory15_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory14_reg_b_0 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory13_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst13_matching_memory13_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst03_matching_memory13_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst12_matching_memory12_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst02_matching_memory12_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst22_matching_memory12_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory15_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory13_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory15_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory13_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory14_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory14_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory13_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory15_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory14_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory10_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst21_matching_memory10_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory10_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst01_matching_memory12_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst23_matching_memory14_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory14_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory14_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory15_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory15_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory15_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory13_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory12_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory12_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory12_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory15_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory14_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory10_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory10_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory10_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst23_matching_memory11_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst13_matching_memory11_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst03_matching_memory11_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst12_matching_memory11_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst02_matching_memory11_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst22_matching_memory11_reg_a_0 has been replicated 5 time(s)
FlipFlop match_inst21_matching_memory12_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst11_matching_memory12_reg_a_0 has been replicated 6 time(s)
FlipFlop match_inst13_matching_memory13_invalid_reg has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory11_invalid_reg has been replicated 3 time(s)
FlipFlop match_inst13_matching_memory11_invalid_reg has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory11_invalid_reg has been replicated 3 time(s)
FlipFlop match_inst23_matching_memory13_invalid_reg has been replicated 4 time(s)
FlipFlop match_inst03_matching_memory13_invalid_reg has been replicated 4 time(s)
FlipFlop match_inst23_matching_memory13_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst13_matching_memory13_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory13_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory12_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory12_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory12_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst21_matching_memory11_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst11_matching_memory11_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst01_matching_memory11_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst23_matching_memory15_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory14_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory15_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory14_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory15_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory14_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory11_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory11_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory11_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory13_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory13_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory13_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory15_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory14_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory15_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory14_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory15_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory14_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory10_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory12_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory10_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory10_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory12_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory12_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory15_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory14_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory15_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory14_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory15_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory14_reg_b_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory13_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory15_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory14_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory10_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory11_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory11_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory11_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory11_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory11_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst12_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst02_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst22_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory13_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory13_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory13_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst22_matching_memory12_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst12_matching_memory12_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst02_matching_memory12_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory11_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory11_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory11_reg_b_0 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory13_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst13_matching_memory13_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory13_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory12_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory12_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory12_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst21_matching_memory11_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst11_matching_memory11_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst01_matching_memory11_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst21_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst01_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst12_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst02_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst22_matching_memory13_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst12_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst02_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst22_matching_memory15_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst12_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst02_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst22_matching_memory14_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst12_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst02_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst22_matching_memory10_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst12_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst02_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst22_matching_memory11_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst21_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst11_matching_memory12_reg_a_4 has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory13_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst13_matching_memory13_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory13_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory12_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory12_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory12_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst21_matching_memory11_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst11_matching_memory11_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst01_matching_memory11_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst23_matching_memory13_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory13_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory13_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory12_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory12_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory12_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory13_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory13_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory13_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory15_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory14_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory15_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory14_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory15_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory14_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory10_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory12_reg_b_5 has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst01_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory11_invalid_reg has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory11_invalid_reg has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory11_invalid_reg has been replicated 1 time(s)
FlipFlop match_inst21_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst11_matching_memory12_reg_a_5 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory10_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst13_matching_memory10_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory10_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory10_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory10_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory10_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory11_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory11_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory13_reg_b_1 has been replicated 3 time(s)
FlipFlop match_inst23_matching_memory10_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst13_matching_memory10_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory10_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory11_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory10_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory10_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory10_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory11_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory11_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory13_reg_b_2 has been replicated 3 time(s)
FlipFlop match_inst23_matching_memory10_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst13_matching_memory10_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory10_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory11_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory10_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory10_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory10_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory11_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory11_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory13_reg_b_3 has been replicated 3 time(s)
FlipFlop match_inst23_matching_memory10_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst13_matching_memory10_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory10_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory11_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory10_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory10_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst02_matching_memory10_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst22_matching_memory11_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory11_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst12_matching_memory13_reg_b_0 has been replicated 3 time(s)
FlipFlop match_inst03_matching_memory12_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst13_matching_memory12_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst23_matching_memory12_invalid_reg has been replicated 2 time(s)
FlipFlop match_inst03_matching_memory10_invalid_reg has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory10_invalid_reg has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory10_invalid_reg has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory12_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory12_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory12_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory13_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory13_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory15_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory14_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory15_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory14_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory15_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory14_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst23_matching_memory10_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst13_matching_memory10_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst03_matching_memory10_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory10_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory10_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst02_matching_memory10_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst22_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory11_reg_b_4 has been replicated 1 time(s)
FlipFlop match_inst12_matching_memory13_reg_b_4 has been replicated 1 time(s)
FlipFlop z_channel_inst52_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst51_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst50_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst42_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst41_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst40_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst32_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst31_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst30_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst22_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst21_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst20_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst12_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst11_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst10_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst02_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst01_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst00_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst00_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst00_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst00_addr2_cnt_92 has been replicated 3 time(s)
FlipFlop z_channel_inst01_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst01_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst01_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst02_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst02_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst02_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst10_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst10_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst10_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst11_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst11_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst11_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst12_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst12_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst12_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst20_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst20_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst20_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst21_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst21_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst21_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst22_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst22_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst22_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst30_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst30_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst30_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst31_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst31_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst31_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst32_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst32_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst32_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst40_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst40_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst40_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst41_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst41_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst41_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst42_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst42_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst42_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst50_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst50_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst50_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst51_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst51_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst51_addr2_cnt_91 has been replicated 3 time(s)
FlipFlop z_channel_inst52_addr2_cnt_89 has been replicated 3 time(s)
FlipFlop z_channel_inst52_addr2_cnt_90 has been replicated 3 time(s)
FlipFlop z_channel_inst52_addr2_cnt_91 has been replicated 3 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                   35347  out of  19392   182% (*) 
 Number of Slice Flip Flops:          9663  out of  38784    24%  
 Number of 4 input LUTs:             41572  out of  38784   107% (*) 
 Number of bonded IOBs:                173  out of    692    25%  
 Number of BRAMs:                       12  out of    192     6%  
 Number of MULT18X18s:                  21  out of    192    10%  
 Number of GCLKs:                       13  out of     16    81%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 12139 |
clk0_in<5>                         | BUFGP                  | 103   |
clk1_in<5>                         | BUFGP                  | 103   |
input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE                   | 2     |
input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE                   | 2     |
clk0_in<4>                         | BUFGP                  | 103   |
clk1_in<4>                         | BUFGP                  | 103   |
input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE                   | 2     |
input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE                   | 2     |
clk0_in<3>                         | BUFGP                  | 103   |
clk1_in<3>                         | BUFGP                  | 103   |
input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE                   | 2     |
input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE                   | 2     |
clk0_in<2>                         | BUFGP                  | 103   |
clk1_in<2>                         | BUFGP                  | 103   |
input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE                   | 2     |
input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE                   | 2     |
clk0_in<1>                         | BUFGP                  | 103   |
clk1_in<1>                         | BUFGP                  | 103   |
input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE                   | 2     |
input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE                   | 2     |
clk0_in<0>                         | BUFGP                  | 103   |
clk1_in<0>                         | BUFGP                  | 103   |
input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/GND:G| NONE                   | 2     |
input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/GND:G| NONE                   | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 19.303ns (Maximum Frequency: 51.805MHz)
   Minimum input arrival time before clock: 12.891ns
   Maximum output required time after clock: 7.822ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
/home/cuveland/nfs/vhdl/gtu/syn_ise/_ngo -i -p xc2vp40-ff1152-5 toplevel.ngc
toplevel.ngd 

Reading NGO file "/home/cuveland/nfs/vhdl/gtu/syn_ise/toplevel.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa "cg_divide.edn" "_ngo/cg_divide.ngo"
INFO:NgdBuild - Release 6.2.01i - edif2ngd G.29
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "_ngo/cg_divide.ngo"...
Loading design module
"/home/cuveland/nfs/vhdl/gtu/syn_ise/_ngo/cg_divide.ngo"...
dividervht, Coregen 6.2i
Launcher: Executing edif2ngd -noa "cg_fifo_dc.edn" "_ngo/cg_fifo_dc.ngo"
INFO:NgdBuild - Release 6.2.01i - edif2ngd G.29
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "_ngo/cg_fifo_dc.ngo"...
Loading design module
"/home/cuveland/nfs/vhdl/gtu/syn_ise/_ngo/cg_fifo_dc.ngo"...
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU153' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU250' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU405' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU1460' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU1464' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/quot<17>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/quot<18>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/quot<19>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/quot<20>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<0>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<1>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<2>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<3>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<4>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<5>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<6>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<7>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<8>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<9>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<10>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<11>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<12>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<13>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<14>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<15>' has no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<29>' has
   no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings: 145

Total memory usage is 118552 kilobytes

Writing NGD file "toplevel.ngd" ...

Writing NGDBUILD log file "toplevel.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
/home/cuveland/nfs/vhdl/gtu/syn_ise/_ngo -uc toplevel.ucf -p xc2vp40-ff1152-5
toplevel.ngc toplevel.ngd 

Reading NGO file "/home/cuveland/nfs/vhdl/gtu/syn_ise/toplevel.ngc" ...
Reading component libraries for design expansion...
Launcher: "cg_divide.ngo" is up to date.
Loading design module
"/home/cuveland/nfs/vhdl/gtu/syn_ise/_ngo/cg_divide.ngo"...
dividervht, Coregen 6.2i
Launcher: "cg_fifo_dc.ngo" is up to date.
Loading design module
"/home/cuveland/nfs/vhdl/gtu/syn_ise/_ngo/cg_fifo_dc.ngo"...
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i
async_fifo_v5_1, Coregen 6.2i

Annotating constraints to design from file "toplevel.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU153' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU250' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU405' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU1460' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'reconst_inst_divide_wrapper_inst_divide_inst/BU1464' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst2_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst1_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU105' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'input_inst0_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/BU230' has
   unconnected output pin
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/quot<17>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/quot<18>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/quot<19>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/quot<20>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<0>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<1>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<2>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<3>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<4>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<5>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<6>' has no load
WARNING:NgdBuild:454 - logical net
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WARNING:NgdBuild:454 - logical net
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WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<9>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<10>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<11>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<12>' has no load
WARNING:NgdBuild:454 - logical net
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WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<14>' has no load
WARNING:NgdBuild:454 - logical net
   'reconst_inst_divide_wrapper_inst_divide_inst/remd<15>' has no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst5_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst4_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<25>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<26>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<30>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<27>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<31>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<28>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst0_fifo_dc_inst/dout<29>' has
   no load
WARNING:NgdBuild:454 - logical net
   'input_inst3_buffer_merger1_fifo_dc_wrapper_inst1_fifo_dc_inst/dout<24>' has
   no load
WARNING:NgdBuild:454 - logical net
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NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings: 145

Total memory usage is 120304 kilobytes

Writing NGD file "toplevel.ngd" ...

Writing NGDBUILD log file "toplevel.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2vp40ff1152-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Running unrelated packing...
ERROR:Pack:18 - The design is too large for the given device and package. 
   Please check the Design Summary section to see which resource requirement for
   your design exceeds the resources available in the device.
   

If the slice count exceeds device resources you might try to disable
   register ordering (-r).  Also if your design contains AREA_GROUPs, you may be
   able to improve density by adding COMPRESSION to your AREA_GROUPs if you
   haven't done so already.
   

NOTE: An NCD file will still be generated to allow you to examine the mapped
   design.  This file is intended for evaluation use only, and will not process
   successfully through PAR.
   

This mapped NCD file can be used to evaluate how the design's logic has been
   mapped into FPGA logic resources.  It can also be used to analyze
   preliminary, logic-level (pre-route) timing with one of the Xilinx static
   timing analysis tools (TRCE or Timing Analyzer).

Design Summary:
Number of errors:      1
Number of warnings: 12375
Logic Utilization:
  Number of Slice Flip Flops:       9,270 out of  38,784   23%
  Number of 4 input LUTs:          28,394 out of  38,784   73%
Logic Distribution:
  Number of occupied Slices:       26,969 out of  19,392  139% (OVERMAPPED)
  Number of Slices containing only related logic:  25,547 out of  26,969   94%
  Number of Slices containing unrelated logic:      1,422 out of  26,969    5%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:         53,731 out of  38,784  138% (OVERMAPPED)
  Number used as logic:            28,394
  Number used as a route-thru:        632
  Number used for Dual Port RAMs:  24,616
    (Two LUTs used per Dual Port RAM)
  Number used as Shift registers:      89

  Number of bonded IOBs:              186 out of     692   26%
    IOB Flip Flops:                   248
  Number of PPC405s:                   0 out of       2    0%
  Number of Block RAMs:                12 out of     192    6%
  Number of MULT18X18s:                21 out of     192   10%
  Number of GCLKs:                     13 out of      16   81%
  Number of GTs:                        0 out of      12    0%
  Number of GT10s:                      0 out of       0    0%

Total equivalent gate count for design:  4,334,631
Additional JTAG gate count for IOBs:  8,928
Peak Memory Usage:  488 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "toplevel_map.mrp" for details.
Problem encountered during the packing phase.
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module toplevel . . .
MAP command line:
map -intstyle ise -p xc2vp40-ff1152-5 -cm area -pr b -k 4 -c 100 -tx off -o toplevel_map.ncd toplevel.ngd toplevel.pcf
Mapping Module toplevel: failed


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Architecture default of Entity zch_merger is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <zch_merger> (Architecture <default>).
Entity <zch_merger> analyzed. Unit <zch_merger> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zch_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0004> created at line 103.
    Found 6-bit adder for signal <$n0012> created at line 103.
    Found 6-bit adder for signal <$n0013>.
    Found 4-bit adder for signal <$n0017> created at line 94.
    Found 6-bit adder for signal <$n0022> created at line 103.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0048> created at line 103.
    Found 3-bit adder for signal <$n0049> created at line 94.
    Found 3-bit comparator not equal for signal <$n0053> created at line 178.
    Found 3-bit comparator not equal for signal <$n0057> created at line 178.
    Found 3-bit comparator not equal for signal <$n0061> created at line 178.
    Found 4-bit adder for signal <$n0067>.
    Found 4-bit adder for signal <$n0072>.
    Found 4-bit subtractor for signal <$n0088> created at line 103.
    Found 4-bit subtractor for signal <$n0089> created at line 103.
    Found 4-bit subtractor for signal <$n0090> created at line 103.
    Found 4-bit comparator less for signal <$n0091> created at line 182.
    Found 4-bit comparator equal for signal <$n0092> created at line 182.
    Found 7-bit comparator less for signal <$n0093> created at line 182.
    Found 4-bit comparator less for signal <$n0094> created at line 182.
    Found 4-bit comparator equal for signal <$n0095> created at line 182.
    Found 7-bit comparator less for signal <$n0096> created at line 182.
    Found 4-bit comparator less for signal <$n0097> created at line 182.
    Found 4-bit comparator equal for signal <$n0098> created at line 182.
    Found 7-bit comparator less for signal <$n0099> created at line 182.
    Found 4x3-bit multiplier for signal <$n0103> created at line 103.
    Found 4x3-bit multiplier for signal <$n0104> created at line 103.
    Found 4x3-bit multiplier for signal <$n0105> created at line 103.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  13 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <zch_merger> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/xilinx6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zch_merger, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     544  out of  19392     2%  
 Number of Slice Flip Flops:            45  out of  38784     0%  
 Number of 4 input LUTs:               429  out of  38784     1%  
 Number of bonded IOBs:                219  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 201   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.108ns (Maximum Frequency: 66.190MHz)
   Minimum input arrival time before clock: 3.580ns
   Maximum output required time after clock: 19.579ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Entity <zch_merger> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <zch_merger> (Architecture <default>).
Entity <zch_merger> analyzed. Unit <zch_merger> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zch_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0004> created at line 103.
    Found 6-bit adder for signal <$n0012> created at line 103.
    Found 6-bit adder for signal <$n0013>.
    Found 4-bit adder for signal <$n0017> created at line 94.
    Found 6-bit adder for signal <$n0022> created at line 103.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0048> created at line 103.
    Found 3-bit adder for signal <$n0049> created at line 94.
    Found 3-bit comparator not equal for signal <$n0053> created at line 179.
    Found 3-bit comparator not equal for signal <$n0057> created at line 179.
    Found 3-bit comparator not equal for signal <$n0061> created at line 179.
    Found 4-bit adder for signal <$n0067>.
    Found 4-bit adder for signal <$n0072>.
    Found 4-bit subtractor for signal <$n0088> created at line 103.
    Found 4-bit subtractor for signal <$n0089> created at line 103.
    Found 4-bit subtractor for signal <$n0090> created at line 103.
    Found 4-bit comparator less for signal <$n0091> created at line 183.
    Found 4-bit comparator equal for signal <$n0092> created at line 183.
    Found 7-bit comparator less for signal <$n0093> created at line 183.
    Found 4-bit comparator less for signal <$n0094> created at line 183.
    Found 4-bit comparator equal for signal <$n0095> created at line 183.
    Found 7-bit comparator less for signal <$n0096> created at line 183.
    Found 4-bit comparator less for signal <$n0097> created at line 183.
    Found 4-bit comparator equal for signal <$n0098> created at line 183.
    Found 7-bit comparator less for signal <$n0099> created at line 183.
    Found 4x3-bit multiplier for signal <$n0103> created at line 103.
    Found 4x3-bit multiplier for signal <$n0104> created at line 103.
    Found 4x3-bit multiplier for signal <$n0105> created at line 103.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  13 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <zch_merger> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/xilinx6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zch_merger, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     538  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               417  out of  38784     1%  
 Number of bonded IOBs:                219  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 3.507ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Entity <zch_merger> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <zch_merger> (Architecture <default>).
Entity <zch_merger> analyzed. Unit <zch_merger> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zch_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 103 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0004> created at line 103.
    Found 6-bit adder for signal <$n0012> created at line 103.
    Found 6-bit adder for signal <$n0013>.
    Found 4-bit adder for signal <$n0017> created at line 94.
    Found 6-bit adder for signal <$n0022> created at line 103.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0048> created at line 103.
    Found 3-bit adder for signal <$n0049> created at line 94.
    Found 3-bit comparator not equal for signal <$n0053> created at line 185.
    Found 3-bit comparator not equal for signal <$n0057> created at line 185.
    Found 3-bit comparator not equal for signal <$n0061> created at line 185.
    Found 4-bit adder for signal <$n0067>.
    Found 4-bit adder for signal <$n0072>.
    Found 4-bit subtractor for signal <$n0088> created at line 103.
    Found 4-bit subtractor for signal <$n0089> created at line 103.
    Found 4-bit subtractor for signal <$n0090> created at line 103.
    Found 4-bit comparator less for signal <$n0091> created at line 189.
    Found 4-bit comparator equal for signal <$n0092> created at line 189.
    Found 7-bit comparator less for signal <$n0093> created at line 189.
    Found 4-bit comparator less for signal <$n0094> created at line 189.
    Found 4-bit comparator equal for signal <$n0095> created at line 189.
    Found 7-bit comparator less for signal <$n0096> created at line 189.
    Found 4-bit comparator less for signal <$n0097> created at line 189.
    Found 4-bit comparator equal for signal <$n0098> created at line 189.
    Found 7-bit comparator less for signal <$n0099> created at line 189.
    Found 4x3-bit multiplier for signal <$n0103> created at line 103.
    Found 4x3-bit multiplier for signal <$n0104> created at line 103.
    Found 4x3-bit multiplier for signal <$n0105> created at line 103.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  13 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <zch_merger> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/xilinx6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zch_merger, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     538  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               417  out of  38784     1%  
 Number of bonded IOBs:                219  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 3.507ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
ERROR:HDLParsers:800 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd Line 163. Type of next_rd_addr is incompatible with type of rd_addr_reg.
--> 


Total memory usage is 39492 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Entity <zch_merger> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <zch_merger> (Architecture <default>).
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd line 156: The following signals are missing in the process sensitivity list:
   rd_addr_reg.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd line 156: The following signals are missing in the process sensitivity list:
   rd_addr_reg.
WARNING:Xst:819 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd line 156: The following signals are missing in the process sensitivity list:
   rd_addr_reg.
Entity <zch_merger> analyzed. Unit <zch_merger> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zch_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0005> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0025> created at line 104.
    Found 6-bit adder for signal <$n0026>.
    Found 4-bit adder for signal <$n0051> created at line 104.
    Found 3-bit adder for signal <$n0052> created at line 95.
    Found 3-bit comparator not equal for signal <$n0056> created at line 192.
    Found 3-bit comparator not equal for signal <$n0060> created at line 192.
    Found 3-bit comparator not equal for signal <$n0064> created at line 192.
    Found 3-bit adder for signal <$n0072> created at line 161.
    Found 4-bit adder for signal <$n0075>.
    Found 3-bit adder for signal <$n0082> created at line 161.
    Found 4-bit adder for signal <$n0085>.
    Found 4-bit subtractor for signal <$n0101> created at line 104.
    Found 4-bit subtractor for signal <$n0102> created at line 104.
    Found 4-bit subtractor for signal <$n0103> created at line 104.
    Found 4-bit comparator less for signal <$n0104> created at line 196.
    Found 4-bit comparator equal for signal <$n0105> created at line 196.
    Found 7-bit comparator less for signal <$n0106> created at line 196.
    Found 4-bit comparator less for signal <$n0107> created at line 196.
    Found 4-bit comparator equal for signal <$n0108> created at line 196.
    Found 7-bit comparator less for signal <$n0109> created at line 196.
    Found 4-bit comparator less for signal <$n0110> created at line 196.
    Found 4-bit comparator equal for signal <$n0111> created at line 196.
    Found 7-bit comparator less for signal <$n0112> created at line 196.
    Found 4x3-bit multiplier for signal <$n0116> created at line 104.
    Found 4x3-bit multiplier for signal <$n0117> created at line 104.
    Found 4x3-bit multiplier for signal <$n0118> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <zch_merger> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/xilinx6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zch_merger, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     538  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               417  out of  38784     1%  
 Number of bonded IOBs:                219  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 3.507ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Entity <zch_merger> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <zch_merger> (Architecture <default>).
Entity <zch_merger> analyzed. Unit <zch_merger> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zch_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0005> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0025> created at line 104.
    Found 6-bit adder for signal <$n0026>.
    Found 4-bit adder for signal <$n0048> created at line 104.
    Found 3-bit adder for signal <$n0049> created at line 95.
    Found 3-bit comparator not equal for signal <$n0053> created at line 193.
    Found 3-bit comparator not equal for signal <$n0057> created at line 193.
    Found 3-bit comparator not equal for signal <$n0061> created at line 193.
    Found 3-bit adder for signal <$n0069> created at line 162.
    Found 4-bit adder for signal <$n0072>.
    Found 3-bit adder for signal <$n0079> created at line 162.
    Found 4-bit adder for signal <$n0082>.
    Found 4-bit subtractor for signal <$n0098> created at line 104.
    Found 4-bit subtractor for signal <$n0099> created at line 104.
    Found 4-bit subtractor for signal <$n0100> created at line 104.
    Found 4-bit comparator less for signal <$n0101> created at line 197.
    Found 4-bit comparator equal for signal <$n0102> created at line 197.
    Found 7-bit comparator less for signal <$n0103> created at line 197.
    Found 4-bit comparator less for signal <$n0104> created at line 197.
    Found 4-bit comparator equal for signal <$n0105> created at line 197.
    Found 7-bit comparator less for signal <$n0106> created at line 197.
    Found 4-bit comparator less for signal <$n0107> created at line 197.
    Found 4-bit comparator equal for signal <$n0108> created at line 197.
    Found 7-bit comparator less for signal <$n0109> created at line 197.
    Found 4x3-bit multiplier for signal <$n0113> created at line 104.
    Found 4x3-bit multiplier for signal <$n0114> created at line 104.
    Found 4x3-bit multiplier for signal <$n0115> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <zch_merger> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/xilinx6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zch_merger, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     533  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               408  out of  38784     1%  
 Number of bonded IOBs:                219  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 3.507ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_table.vhd in Library work.
Architecture default of Entity zch_table is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/sorter.vhd in Library work.
Architecture default of Entity sorter is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd in Library work.
Architecture default of Entity z_channel is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <z_channel> (Architecture <default>).
ERROR:Xst:834 - /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/z_channel.vhd line 28: Generic <plane> has not been given a value.
--> 


Total memory usage is 43784 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Architecture default of Entity zch_merger is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <zch_merger> (Architecture <default>).
Entity <zch_merger> analyzed. Unit <zch_merger> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zch_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0005> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0025> created at line 104.
    Found 6-bit adder for signal <$n0026>.
    Found 4-bit adder for signal <$n0048> created at line 104.
    Found 3-bit adder for signal <$n0049> created at line 95.
    Found 3-bit comparator not equal for signal <$n0053> created at line 193.
    Found 3-bit comparator not equal for signal <$n0057> created at line 193.
    Found 3-bit comparator not equal for signal <$n0061> created at line 193.
    Found 3-bit adder for signal <$n0069> created at line 162.
    Found 4-bit adder for signal <$n0072>.
    Found 3-bit adder for signal <$n0079> created at line 162.
    Found 4-bit adder for signal <$n0082>.
    Found 4-bit subtractor for signal <$n0098> created at line 104.
    Found 4-bit subtractor for signal <$n0099> created at line 104.
    Found 4-bit subtractor for signal <$n0100> created at line 104.
    Found 4-bit comparator less for signal <$n0101> created at line 197.
    Found 4-bit comparator equal for signal <$n0102> created at line 197.
    Found 7-bit comparator less for signal <$n0103> created at line 197.
    Found 4-bit comparator less for signal <$n0104> created at line 197.
    Found 4-bit comparator equal for signal <$n0105> created at line 197.
    Found 7-bit comparator less for signal <$n0106> created at line 197.
    Found 4-bit comparator less for signal <$n0107> created at line 197.
    Found 4-bit comparator equal for signal <$n0108> created at line 197.
    Found 7-bit comparator less for signal <$n0109> created at line 197.
    Found 4x3-bit multiplier for signal <$n0113> created at line 104.
    Found 4x3-bit multiplier for signal <$n0114> created at line 104.
    Found 4x3-bit multiplier for signal <$n0115> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <zch_merger> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zch_merger, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     533  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               408  out of  38784     1%  
 Number of bonded IOBs:                219  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 3.507ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/delme.vhd in Library work.
ERROR:HDLParsers:164 - /home/cuveland/nfs/vhdl/gtu/syn_ise/delme.vhd Line 20. parse error, unexpected TYPE
--> 


Total memory usage is 40256 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/delme.vhd in Library work.
ERROR:HDLParsers:837 - /home/cuveland/nfs/vhdl/gtu/syn_ise/delme.vhd Line 30. Index size for dimension 1 of rd_addr is not 5.
--> 


Total memory usage is 40256 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/delme.vhd in Library work.
Entity <delme> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <delme> (Architecture <Behavioral>).
Entity <delme> analyzed. Unit <delme> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <delme>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/delme.vhd.
    Found 16x16-bit dual-port block RAM for signal <RAM>.
    -----------------------------------------------------------------------
    | dual mode          | write-first                         |          |
    | aspect ratio       | 16-word x 16-bit                    |          |
    | clock              | connected to signal <clk>           | rise     |
    | dual clock         | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <wr_enable>     | high     |
    | address            | connected to signal <wr_addr>       |          |
    | dual address       | connected to signal <rd_addr>       |          |
    | data in            | connected to signal <wr_data>       |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <rd_data>       |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <delme> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Block RAMs                       : 1
 16x16-bit dual-port block RAM     : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <delme> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block delme, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of bonded IOBs:                 41  out of    692     5%  
 Number of BRAMs:                        1  out of    192     0%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: 1.821ns
   Maximum output required time after clock: 5.278ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd in Library work.
Entity <zch_merger> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <zch_merger> (Architecture <default>).
Entity <zch_merger> analyzed. Unit <zch_merger> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zch_merger>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/zch_merger.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0005> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0025> created at line 104.
    Found 6-bit adder for signal <$n0026>.
    Found 4-bit adder for signal <$n0048> created at line 104.
    Found 3-bit adder for signal <$n0049> created at line 95.
    Found 3-bit comparator not equal for signal <$n0053> created at line 194.
    Found 3-bit comparator not equal for signal <$n0057> created at line 194.
    Found 3-bit comparator not equal for signal <$n0061> created at line 194.
    Found 3-bit adder for signal <$n0069> created at line 163.
    Found 4-bit adder for signal <$n0072>.
    Found 3-bit adder for signal <$n0079> created at line 163.
    Found 4-bit adder for signal <$n0082>.
    Found 4-bit subtractor for signal <$n0098> created at line 104.
    Found 4-bit subtractor for signal <$n0099> created at line 104.
    Found 4-bit subtractor for signal <$n0100> created at line 104.
    Found 4-bit comparator less for signal <$n0101> created at line 198.
    Found 4-bit comparator equal for signal <$n0102> created at line 198.
    Found 7-bit comparator less for signal <$n0103> created at line 198.
    Found 4-bit comparator less for signal <$n0104> created at line 198.
    Found 4-bit comparator equal for signal <$n0105> created at line 198.
    Found 7-bit comparator less for signal <$n0106> created at line 198.
    Found 4-bit comparator less for signal <$n0107> created at line 198.
    Found 4-bit comparator equal for signal <$n0108> created at line 198.
    Found 7-bit comparator less for signal <$n0109> created at line 198.
    Found 4x3-bit multiplier for signal <$n0113> created at line 104.
    Found 4x3-bit multiplier for signal <$n0114> created at line 104.
    Found 4x3-bit multiplier for signal <$n0115> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <zch_merger> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <zch_merger> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zch_merger, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     530  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               404  out of  38784     1%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 2.788ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0005> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0025> created at line 104.
    Found 6-bit adder for signal <$n0026>.
    Found 4-bit adder for signal <$n0048> created at line 104.
    Found 3-bit adder for signal <$n0049> created at line 95.
    Found 3-bit comparator not equal for signal <$n0053> created at line 193.
    Found 3-bit comparator not equal for signal <$n0057> created at line 193.
    Found 3-bit comparator not equal for signal <$n0061> created at line 193.
    Found 3-bit adder for signal <$n0069> created at line 162.
    Found 4-bit adder for signal <$n0072>.
    Found 3-bit adder for signal <$n0079> created at line 162.
    Found 4-bit adder for signal <$n0082>.
    Found 4-bit subtractor for signal <$n0098> created at line 104.
    Found 4-bit subtractor for signal <$n0099> created at line 104.
    Found 4-bit subtractor for signal <$n0100> created at line 104.
    Found 4-bit comparator less for signal <$n0101> created at line 197.
    Found 4-bit comparator equal for signal <$n0102> created at line 197.
    Found 7-bit comparator less for signal <$n0103> created at line 197.
    Found 4-bit comparator less for signal <$n0104> created at line 197.
    Found 4-bit comparator equal for signal <$n0105> created at line 197.
    Found 7-bit comparator less for signal <$n0106> created at line 197.
    Found 4-bit comparator less for signal <$n0107> created at line 197.
    Found 4-bit comparator equal for signal <$n0108> created at line 197.
    Found 7-bit comparator less for signal <$n0109> created at line 197.
    Found 4x3-bit multiplier for signal <$n0113> created at line 104.
    Found 4x3-bit multiplier for signal <$n0114> created at line 104.
    Found 4x3-bit multiplier for signal <$n0115> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     533  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               408  out of  38784     1%  
 Number of bonded IOBs:                219  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 3.507ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0005> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0025> created at line 104.
    Found 6-bit adder for signal <$n0026>.
    Found 4-bit adder for signal <$n0048> created at line 104.
    Found 3-bit adder for signal <$n0049> created at line 95.
    Found 3-bit comparator not equal for signal <$n0053> created at line 172.
    Found 3-bit comparator not equal for signal <$n0057> created at line 172.
    Found 3-bit comparator not equal for signal <$n0061> created at line 172.
    Found 3-bit adder for signal <$n0069> created at line 156.
    Found 4-bit adder for signal <$n0072>.
    Found 3-bit adder for signal <$n0079> created at line 156.
    Found 4-bit adder for signal <$n0082>.
    Found 4-bit subtractor for signal <$n0098> created at line 104.
    Found 4-bit subtractor for signal <$n0099> created at line 104.
    Found 4-bit subtractor for signal <$n0100> created at line 104.
    Found 4-bit comparator less for signal <$n0101> created at line 176.
    Found 4-bit comparator equal for signal <$n0102> created at line 176.
    Found 7-bit comparator less for signal <$n0103> created at line 176.
    Found 4-bit comparator less for signal <$n0104> created at line 176.
    Found 4-bit comparator equal for signal <$n0105> created at line 176.
    Found 7-bit comparator less for signal <$n0106> created at line 176.
    Found 4-bit comparator less for signal <$n0107> created at line 176.
    Found 4-bit comparator equal for signal <$n0108> created at line 176.
    Found 7-bit comparator less for signal <$n0109> created at line 176.
    Found 4x3-bit multiplier for signal <$n0113> created at line 104.
    Found 4x3-bit multiplier for signal <$n0114> created at line 104.
    Found 4x3-bit multiplier for signal <$n0115> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     530  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               404  out of  38784     1%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 2.788ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0005> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0025> created at line 104.
    Found 6-bit adder for signal <$n0026>.
    Found 4-bit adder for signal <$n0048> created at line 104.
    Found 3-bit adder for signal <$n0049> created at line 95.
    Found 3-bit comparator not equal for signal <$n0053> created at line 172.
    Found 3-bit comparator not equal for signal <$n0057> created at line 172.
    Found 3-bit comparator not equal for signal <$n0061> created at line 172.
    Found 3-bit adder for signal <$n0069> created at line 156.
    Found 4-bit adder for signal <$n0072>.
    Found 3-bit adder for signal <$n0079> created at line 156.
    Found 4-bit adder for signal <$n0082>.
    Found 4-bit subtractor for signal <$n0098> created at line 104.
    Found 4-bit subtractor for signal <$n0099> created at line 104.
    Found 4-bit subtractor for signal <$n0100> created at line 104.
    Found 4-bit comparator less for signal <$n0101> created at line 176.
    Found 4-bit comparator equal for signal <$n0102> created at line 176.
    Found 7-bit comparator less for signal <$n0103> created at line 176.
    Found 4-bit comparator less for signal <$n0104> created at line 176.
    Found 4-bit comparator equal for signal <$n0105> created at line 176.
    Found 7-bit comparator less for signal <$n0106> created at line 176.
    Found 4-bit comparator less for signal <$n0107> created at line 176.
    Found 4-bit comparator equal for signal <$n0108> created at line 176.
    Found 7-bit comparator less for signal <$n0109> created at line 176.
    Found 4x3-bit multiplier for signal <$n0113> created at line 104.
    Found 4x3-bit multiplier for signal <$n0114> created at line 104.
    Found 4x3-bit multiplier for signal <$n0115> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     530  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               404  out of  38784     1%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 2.788ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Architecture default of Entity downgrade is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0005> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0025> created at line 104.
    Found 6-bit adder for signal <$n0026>.
    Found 4-bit adder for signal <$n0048> created at line 104.
    Found 3-bit adder for signal <$n0049> created at line 95.
    Found 3-bit comparator not equal for signal <$n0053> created at line 172.
    Found 3-bit comparator not equal for signal <$n0057> created at line 172.
    Found 3-bit comparator not equal for signal <$n0061> created at line 172.
    Found 3-bit adder for signal <$n0069> created at line 156.
    Found 4-bit adder for signal <$n0072>.
    Found 3-bit adder for signal <$n0079> created at line 156.
    Found 4-bit adder for signal <$n0082>.
    Found 4-bit subtractor for signal <$n0098> created at line 104.
    Found 4-bit subtractor for signal <$n0099> created at line 104.
    Found 4-bit subtractor for signal <$n0100> created at line 104.
    Found 4-bit comparator less for signal <$n0101> created at line 176.
    Found 4-bit comparator equal for signal <$n0102> created at line 176.
    Found 7-bit comparator less for signal <$n0103> created at line 176.
    Found 4-bit comparator less for signal <$n0104> created at line 176.
    Found 4-bit comparator equal for signal <$n0105> created at line 176.
    Found 7-bit comparator less for signal <$n0106> created at line 176.
    Found 4-bit comparator less for signal <$n0107> created at line 176.
    Found 4-bit comparator equal for signal <$n0108> created at line 176.
    Found 7-bit comparator less for signal <$n0109> created at line 176.
    Found 4x3-bit multiplier for signal <$n0113> created at line 104.
    Found 4x3-bit multiplier for signal <$n0114> created at line 104.
    Found 4x3-bit multiplier for signal <$n0115> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     530  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               404  out of  38784     1%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 2.788ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 104 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0008> created at line 104.
    Found 6-bit adder for signal <$n0014> created at line 104.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 95.
    Found 6-bit adder for signal <$n0022> created at line 104.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0045> created at line 104.
    Found 3-bit adder for signal <$n0046> created at line 95.
    Found 3-bit comparator not equal for signal <$n0050> created at line 182.
    Found 3-bit comparator not equal for signal <$n0054> created at line 182.
    Found 3-bit comparator not equal for signal <$n0058> created at line 182.
    Found 3-bit adder for signal <$n0066> created at line 167.
    Found 4-bit adder for signal <$n0069>.
    Found 3-bit adder for signal <$n0076> created at line 167.
    Found 4-bit adder for signal <$n0079>.
    Found 4-bit subtractor for signal <$n0095> created at line 104.
    Found 4-bit subtractor for signal <$n0096> created at line 104.
    Found 4-bit subtractor for signal <$n0097> created at line 104.
    Found 4-bit comparator less for signal <$n0098> created at line 186.
    Found 4-bit comparator equal for signal <$n0099> created at line 186.
    Found 7-bit comparator less for signal <$n0100> created at line 186.
    Found 4-bit comparator less for signal <$n0101> created at line 186.
    Found 4-bit comparator equal for signal <$n0102> created at line 186.
    Found 7-bit comparator less for signal <$n0103> created at line 186.
    Found 4-bit comparator less for signal <$n0104> created at line 186.
    Found 4-bit comparator equal for signal <$n0105> created at line 186.
    Found 7-bit comparator less for signal <$n0106> created at line 186.
    Found 4x3-bit multiplier for signal <$n0110> created at line 104.
    Found 4x3-bit multiplier for signal <$n0111> created at line 104.
    Found 4x3-bit multiplier for signal <$n0112> created at line 104.
    Found 3-bit up counter for signal <rd_addr_reg>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     528  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               404  out of  38784     1%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 2.788ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 150. Undefined symbol 'valid_in_0'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 150. valid_in_0: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 155. Undefined symbol 'mem_0'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 155. mem_0: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 161. Undefined symbol 'mem_out_0'.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 161. Undefined symbol 'mem_0'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 161. mem_0: Undefined symbol (last report in this block)
--> 


Total memory usage is 40768 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 155. Undefined symbol 'mem_0'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 155. mem_0: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 161. Undefined symbol 'mem_out_0'.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 161. Undefined symbol 'mem_0'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 161. mem_0: Undefined symbol (last report in this block)
--> 


Total memory usage is 40768 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
WARNING:Xst:1780 - Signal <wr_addr_reg<0>> is never used or assigned.
WARNING:Xst:653 - Signal <rd_addr_reg<0>> is used but never assigned. Tied to value 000.
WARNING:Xst:646 - Signal <wr_addr_last_0> is assigned but never used.
WARNING:Xst:653 - Signal <wr_addr_last<0>> is used but never assigned. Tied to value 000.
WARNING:Xst:653 - Signal <next_rd_addr_0> is used but never assigned. Tied to value 000.
WARNING:Xst:646 - Signal <next_rd_addr<0>> is assigned but never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port block RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | dual mode          | write-first                         |          |
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | dual clock         | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg_0> |          |
    | dual address       | connected to signal <next_rd_addr_0> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0008> created at line 109.
    Found 6-bit adder for signal <$n0014> created at line 109.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 100.
    Found 6-bit adder for signal <$n0022> created at line 109.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0044> created at line 109.
    Found 3-bit adder for signal <$n0045> created at line 100.
    Found 3-bit comparator not equal for signal <$n0049> created at line 187.
    Found 3-bit comparator not equal for signal <$n0053> created at line 187.
    Found 3-bit adder for signal <$n0065> created at line 172.
    Found 4-bit adder for signal <$n0068>.
    Found 4-bit adder for signal <$n0073>.
    Found 4-bit subtractor for signal <$n0089> created at line 109.
    Found 4-bit subtractor for signal <$n0090> created at line 109.
    Found 4-bit subtractor for signal <$n0091> created at line 109.
    Found 4-bit comparator less for signal <$n0092> created at line 191.
    Found 4-bit comparator equal for signal <$n0093> created at line 191.
    Found 7-bit comparator less for signal <$n0094> created at line 191.
    Found 4-bit comparator less for signal <$n0095> created at line 191.
    Found 4-bit comparator equal for signal <$n0096> created at line 191.
    Found 7-bit comparator less for signal <$n0097> created at line 191.
    Found 4-bit comparator less for signal <$n0098> created at line 191.
    Found 4-bit comparator equal for signal <$n0099> created at line 191.
    Found 7-bit comparator less for signal <$n0100> created at line 191.
    Found 4x3-bit multiplier for signal <$n0104> created at line 109.
    Found 4x3-bit multiplier for signal <$n0105> created at line 109.
    Found 4x3-bit multiplier for signal <$n0106> created at line 109.
    Found 3-bit up counter for signal <rd_addr_reg<2:1>>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 6-bit register for signal <wr_addr_last<2:1>>.
    Found 3-bit up counter for signal <wr_addr_reg<2:1>>.
    Found 3-bit up counter for signal <wr_addr_reg_0>.
    Summary:
	inferred   3 RAM(s).
	inferred   5 Counter(s).
	inferred   9 D-type flip-flop(s).
	inferred  14 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  11 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Block RAMs                       : 1
 8x52-bit dual-port block RAM      : 1
# LUT RAMs                         : 2
 8x52-bit dual-port distributed RAM: 2
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 10
 6-bit adder                       : 2
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 3
 5-bit adder                       : 1
# Counters                         : 5
 3-bit up counter                  : 5
# Registers                        : 5
 1-bit register                    : 3
 3-bit register                    : 2
# Comparators                      : 5
 7-bit comparator less             : 1
 4-bit comparator equal            : 1
 4-bit comparator less             : 1
 3-bit comparator not equal        : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 1.
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     378  out of  19392     1%  
 Number of Slice Flip Flops:            30  out of  38784     0%  
 Number of 4 input LUTs:               314  out of  38784     0%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of BRAMs:                        2  out of    192     1%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 136   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.333ns (Maximum Frequency: 75.002MHz)
   Minimum input arrival time before clock: 2.768ns
   Maximum output required time after clock: 18.643ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
WARNING:Xst:1780 - Signal <wr_addr_reg_0> is never used or assigned.
WARNING:Xst:653 - Signal <rd_addr_reg<0>> is used but never assigned. Tied to value 000.
WARNING:Xst:1780 - Signal <wr_addr_last_0> is never used or assigned.
WARNING:Xst:653 - Signal <next_rd_addr_0> is used but never assigned. Tied to value 000.
WARNING:Xst:646 - Signal <next_rd_addr<0>> is assigned but never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port block RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | dual mode          | write-first                         |          |
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | dual clock         | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <next_rd_addr_0> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0008> created at line 109.
    Found 6-bit adder for signal <$n0014> created at line 109.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 100.
    Found 6-bit adder for signal <$n0022> created at line 109.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0044> created at line 109.
    Found 3-bit adder for signal <$n0045> created at line 100.
    Found 3-bit comparator not equal for signal <$n0049> created at line 187.
    Found 3-bit comparator not equal for signal <$n0053> created at line 187.
    Found 3-bit adder for signal <$n0065> created at line 172.
    Found 4-bit adder for signal <$n0068>.
    Found 4-bit adder for signal <$n0073>.
    Found 4-bit subtractor for signal <$n0089> created at line 109.
    Found 4-bit subtractor for signal <$n0090> created at line 109.
    Found 4-bit subtractor for signal <$n0091> created at line 109.
    Found 4-bit comparator less for signal <$n0092> created at line 191.
    Found 4-bit comparator equal for signal <$n0093> created at line 191.
    Found 7-bit comparator less for signal <$n0094> created at line 191.
    Found 4-bit comparator less for signal <$n0095> created at line 191.
    Found 4-bit comparator equal for signal <$n0096> created at line 191.
    Found 7-bit comparator less for signal <$n0097> created at line 191.
    Found 4-bit comparator less for signal <$n0098> created at line 191.
    Found 4-bit comparator equal for signal <$n0099> created at line 191.
    Found 7-bit comparator less for signal <$n0100> created at line 191.
    Found 4x3-bit multiplier for signal <$n0104> created at line 109.
    Found 4x3-bit multiplier for signal <$n0105> created at line 109.
    Found 4x3-bit multiplier for signal <$n0106> created at line 109.
    Found 3-bit up counter for signal <rd_addr_reg<2:1>>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   5 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  14 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  11 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Block RAMs                       : 1
 8x52-bit dual-port block RAM      : 1
# LUT RAMs                         : 2
 8x52-bit dual-port distributed RAM: 2
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 5
 3-bit up counter                  : 5
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 11
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 1.
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     397  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               350  out of  38784     0%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of BRAMs:                        2  out of    192     1%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 145   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.322ns (Maximum Frequency: 65.266MHz)
   Minimum input arrival time before clock: 2.788ns
   Maximum output required time after clock: 19.487ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
WARNING:Xst:1780 - Signal <wr_addr_reg_0> is never used or assigned.
WARNING:Xst:653 - Signal <rd_addr_reg<0>> is used but never assigned. Tied to value 000.
WARNING:Xst:1780 - Signal <wr_addr_last_0> is never used or assigned.
WARNING:Xst:1780 - Signal <next_rd_addr_0> is never used or assigned.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg<2>> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg<1>> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port block RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | dual mode          | write-first                         |          |
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | dual clock         | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <next_rd_addr<0>> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 109 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0008> created at line 109.
    Found 6-bit adder for signal <$n0014> created at line 109.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 100.
    Found 6-bit adder for signal <$n0022> created at line 109.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0044> created at line 109.
    Found 3-bit adder for signal <$n0045> created at line 100.
    Found 3-bit comparator not equal for signal <$n0049> created at line 187.
    Found 3-bit comparator not equal for signal <$n0053> created at line 187.
    Found 3-bit adder for signal <$n0065> created at line 172.
    Found 3-bit adder for signal <$n0070> created at line 172.
    Found 4-bit adder for signal <$n0073>.
    Found 3-bit adder for signal <$n0080> created at line 172.
    Found 4-bit adder for signal <$n0083>.
    Found 4-bit subtractor for signal <$n0099> created at line 109.
    Found 4-bit subtractor for signal <$n0100> created at line 109.
    Found 4-bit subtractor for signal <$n0101> created at line 109.
    Found 4-bit comparator less for signal <$n0102> created at line 191.
    Found 4-bit comparator equal for signal <$n0103> created at line 191.
    Found 7-bit comparator less for signal <$n0104> created at line 191.
    Found 4-bit comparator less for signal <$n0105> created at line 191.
    Found 4-bit comparator equal for signal <$n0106> created at line 191.
    Found 7-bit comparator less for signal <$n0107> created at line 191.
    Found 4-bit comparator less for signal <$n0108> created at line 191.
    Found 4-bit comparator equal for signal <$n0109> created at line 191.
    Found 7-bit comparator less for signal <$n0110> created at line 191.
    Found 4x3-bit multiplier for signal <$n0114> created at line 109.
    Found 4x3-bit multiplier for signal <$n0115> created at line 109.
    Found 4x3-bit multiplier for signal <$n0116> created at line 109.
    Found 3-bit up counter for signal <rd_addr_reg<2:1>>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   5 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  16 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  11 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Block RAMs                       : 1
 8x52-bit dual-port block RAM      : 1
# LUT RAMs                         : 2
 8x52-bit dual-port distributed RAM: 2
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 14
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 2
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 5
 3-bit up counter                  : 5
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 11
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 1.
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     400  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               356  out of  38784     0%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of BRAMs:                        2  out of    192     1%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 145   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.361ns (Maximum Frequency: 65.100MHz)
   Minimum input arrival time before clock: 5.588ns
   Maximum output required time after clock: 19.526ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 119. Undefined symbol 'rd_addr_reg_1'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 119. rd_addr_reg_1: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 120. Undefined symbol 'rd_addr_reg_2'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 120. rd_addr_reg_2: Undefined symbol (last report in this block)
--> 


Total memory usage is 40760 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 123. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 123. rd_addr_reg: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 149. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 149. rd_addr_reg: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 170. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 170. rd_addr_reg: Undefined symbol (last report in this block)
--> 


Total memory usage is 40756 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 123. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 123. rd_addr_reg: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 129. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 129. rd_addr_reg: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 135. Undefined symbol 'ch'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 135. ch: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 176. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 176. rd_addr_reg: Undefined symbol (last report in this block)
--> 


Total memory usage is 40764 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 123. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 123. rd_addr_reg: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 135. Undefined symbol 'ch'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 135. ch: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 176. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 176. rd_addr_reg: Undefined symbol (last report in this block)
--> 


Total memory usage is 40764 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 135. Undefined symbol 'ch'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 135. ch: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 176. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 176. rd_addr_reg: Undefined symbol (last report in this block)
--> 


Total memory usage is 40764 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
ERROR:HDLParsers:3312 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 192. Undefined symbol 'rd_addr_reg'.
ERROR:HDLParsers:1209 - /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd Line 192. rd_addr_reg: Undefined symbol (last report in this block)
--> 


Total memory usage is 40768 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg_2> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg_1> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg_0> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 108 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 108 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 108 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0008> created at line 108.
    Found 6-bit adder for signal <$n0014> created at line 108.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 99.
    Found 6-bit adder for signal <$n0022> created at line 108.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0045> created at line 108.
    Found 3-bit adder for signal <$n0046> created at line 99.
    Found 3-bit comparator not equal for signal <$n0049> created at line 162.
    Found 3-bit comparator not equal for signal <$n0050> created at line 165.
    Found 3-bit comparator not equal for signal <$n0051> created at line 168.
    Found 3-bit adder for signal <$n0066> created at line 145.
    Found 3-bit adder for signal <$n0071> created at line 156.
    Found 4-bit adder for signal <$n0074>.
    Found 4-bit adder for signal <$n0079>.
    Found 4-bit subtractor for signal <$n0095> created at line 108.
    Found 4-bit subtractor for signal <$n0096> created at line 108.
    Found 4-bit subtractor for signal <$n0097> created at line 108.
    Found 4-bit comparator less for signal <$n0098> created at line 202.
    Found 4-bit comparator equal for signal <$n0099> created at line 202.
    Found 7-bit comparator less for signal <$n0100> created at line 202.
    Found 4-bit comparator less for signal <$n0101> created at line 202.
    Found 4-bit comparator equal for signal <$n0102> created at line 202.
    Found 7-bit comparator less for signal <$n0103> created at line 202.
    Found 4-bit comparator less for signal <$n0104> created at line 202.
    Found 4-bit comparator equal for signal <$n0105> created at line 202.
    Found 7-bit comparator less for signal <$n0106> created at line 202.
    Found 4x3-bit multiplier for signal <$n0110> created at line 108.
    Found 4x3-bit multiplier for signal <$n0111> created at line 108.
    Found 4x3-bit multiplier for signal <$n0112> created at line 108.
    Found 3-bit up counter for signal <rd_addr_reg_0>.
    Found 3-bit up counter for signal <rd_addr_reg_1>.
    Found 3-bit up counter for signal <rd_addr_reg_2>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     528  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               404  out of  38784     1%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 2.788ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/gtu_types.vhd in Library work.
Architecture gtu_types of Entity gtu_types is up to date.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/../src/track_types.vhd in Library work.
Compiling vhdl file /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd in Library work.
Entity <downgrade> (Architecture <default>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <downgrade> (Architecture <default>).
Entity <downgrade> analyzed. Unit <downgrade> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <downgrade>.
    Related source file is /home/cuveland/nfs/vhdl/gtu/syn_ise/downgrade.vhd.
WARNING:Xst:647 - Input <rst_n> is never used.
    Found 8x52-bit dual-port distributed RAM for signal <mem<2>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<2>>   | high     |
    | address            | connected to signal <wr_addr_reg<2>> |          |
    | dual address       | connected to signal <rd_addr_reg_2> |          |
    | data in            | connected to signal <track_in<2>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<2>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<1>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<1>>   | high     |
    | address            | connected to signal <wr_addr_reg<1>> |          |
    | dual address       | connected to signal <rd_addr_reg_1> |          |
    | data in            | connected to signal <track_in<1>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<1>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8x52-bit dual-port distributed RAM for signal <mem<0>>.
    -----------------------------------------------------------------------
    | aspect ratio       | 8-word x 52-bit                     |          |
    | clock              | connected to signal <clk>           | rise     |
    | write enable       | connected to signal <valid_in<0>>   | high     |
    | address            | connected to signal <wr_addr_reg<0>> |          |
    | dual address       | connected to signal <rd_addr_reg_0> |          |
    | data in            | connected to signal <track_in<0>>   |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <mem_out<0>>    |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 108 is partially used. Only the 5 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 108 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
WARNING:Xst:643 - The result of a 4x3-bit multiplication found at line 108 is partially used. Only the 6 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
    Found 5-bit adder for signal <$n0008> created at line 108.
    Found 6-bit adder for signal <$n0014> created at line 108.
    Found 6-bit adder for signal <$n0015>.
    Found 4-bit adder for signal <$n0019> created at line 99.
    Found 6-bit adder for signal <$n0022> created at line 108.
    Found 6-bit adder for signal <$n0023>.
    Found 4-bit adder for signal <$n0045> created at line 108.
    Found 3-bit adder for signal <$n0046> created at line 99.
    Found 3-bit comparator not equal for signal <$n0049> created at line 162.
    Found 3-bit comparator not equal for signal <$n0050> created at line 165.
    Found 3-bit comparator not equal for signal <$n0051> created at line 168.
    Found 3-bit adder for signal <$n0066> created at line 145.
    Found 3-bit adder for signal <$n0071> created at line 156.
    Found 4-bit adder for signal <$n0074>.
    Found 4-bit adder for signal <$n0079>.
    Found 4-bit subtractor for signal <$n0095> created at line 108.
    Found 4-bit subtractor for signal <$n0096> created at line 108.
    Found 4-bit subtractor for signal <$n0097> created at line 108.
    Found 4-bit comparator less for signal <$n0098> created at line 202.
    Found 4-bit comparator equal for signal <$n0099> created at line 202.
    Found 7-bit comparator less for signal <$n0100> created at line 202.
    Found 4-bit comparator less for signal <$n0101> created at line 202.
    Found 4-bit comparator equal for signal <$n0102> created at line 202.
    Found 7-bit comparator less for signal <$n0103> created at line 202.
    Found 4-bit comparator less for signal <$n0104> created at line 202.
    Found 4-bit comparator equal for signal <$n0105> created at line 202.
    Found 7-bit comparator less for signal <$n0106> created at line 202.
    Found 4x3-bit multiplier for signal <$n0110> created at line 108.
    Found 4x3-bit multiplier for signal <$n0111> created at line 108.
    Found 4x3-bit multiplier for signal <$n0112> created at line 108.
    Found 3-bit up counter for signal <rd_addr_reg_0>.
    Found 3-bit up counter for signal <rd_addr_reg_1>.
    Found 3-bit up counter for signal <rd_addr_reg_2>.
    Found 3-bit register for signal <ready_in_reg>.
    Found 9-bit register for signal <wr_addr_last>.
    Found 3-bit up counter for signal <wr_addr_reg>.
    Summary:
	inferred   3 RAM(s).
	inferred   6 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred  15 Adder/Subtracter(s).
	inferred   3 Multiplier(s).
	inferred  12 Comparator(s).
Unit <downgrade> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 3
 8x52-bit dual-port distributed RAM: 3
# Multipliers                      : 3
 4x3-bit multiplier                : 3
# Adders/Subtractors               : 13
 6-bit adder                       : 4
 4-bit subtractor                  : 3
 3-bit adder                       : 1
 4-bit adder                       : 4
 5-bit adder                       : 1
# Counters                         : 6
 3-bit up counter                  : 6
# Registers                        : 6
 1-bit register                    : 3
 3-bit register                    : 3
# Comparators                      : 12
 7-bit comparator less             : 3
 4-bit comparator equal            : 3
 4-bit comparator less             : 3
 3-bit comparator not equal        : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <downgrade> ...
Loading device for application Xst from file '2vp40.nph' in environment /cad/products/xilinx/6.2i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block downgrade, actual ratio is 2.
FlipFlop rd_addr_reg_0_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_0_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_1_2 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_0 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_1 has been replicated 1 time(s)
FlipFlop rd_addr_reg_2_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp40ff1152-5 

 Number of Slices:                     528  out of  19392     2%  
 Number of Slice Flip Flops:            39  out of  38784     0%  
 Number of 4 input LUTs:               404  out of  38784     1%  
 Number of bonded IOBs:                218  out of    692    31%  
 Number of MULT18X18s:                   3  out of    192     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 195   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 15.199ns (Maximum Frequency: 65.794MHz)
   Minimum input arrival time before clock: 2.788ns
   Maximum output required time after clock: 19.442ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".