Design Analyzer (TM) Behavioral Compiler (TM) DC Professional (TM) DC Expert (TM) DC Ultra (TM) FPGA Compiler (TM) VHDL Compiler (TM) HDL Compiler (TM) Library Compiler (TM) Power Compiler (TM) DFT Compiler (TM) Test Compiler (TM) BSD Compiler DesignWare Developer (TM) DesignPower (TM) Version 2000.11 for hpux10 -- Nov 09, 2000 Copyright (c) 1988-2000 by Synopsys, Inc. ALL RIGHTS RESERVED design_analyzer> read -format vhdl {"/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd"} Loading db file '/cad/products/synopsys/2000.11/libraries/syn/standard.sldb' Loading db file '/cad/products/synopsys/1999.10/libraries/syn/dw01.sldb' Loading db file '/cad/products/synopsys/1999.10/libraries/syn/dw03.sldb' Loading db file '/cad/products/synopsys/1999.10/libraries/syn/dw04.sldb' Loading db file '/cad/products/synopsys/1999.10/libraries/syn/dw05.sldb' Loading db file '/cad/products/synopsys/1999.10/libraries/syn/dw06.sldb' Loading db file '/cad/products/synopsys/1999.10/libraries/syn/dw07.sldb' Loading db file '/cad/products/synopsys/1999.10/libraries/syn/class.db' Loading db file '/cad/products/synopsys/2000.11/libraries/syn/gtech.db' Loading db file '/cad/libs/ams3.20/synopsys/csx_3.3V/csx_IOLIB_3M.db' Loading db file '/cad/libs/ams3.20/synopsys/csx_3.3V/csx_HRDLIB.db' Loading vhdl file '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd' Reading in the Synopsys vhdl primitives. /cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd: Warning: The VHDL design 'sortc' contains generics but was treated as a "design." To save as a "template", which can be instantiated with different parameters, use the "analyze" command. This is recommended since this does not require changing HDL code or setting any variables. Alternately reread file(s) with 'hdlin_auto_save_templates = "TRUE"', or insert the synthetic comment "template" in the HDL source. (HDL-209) Inferred memory devices in process 'reg' in routine sortc line 60 in file '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd'. =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | REG_Q_reg | Flip-flop | 8 | Y | N | N | Y | N | N | N | =============================================================================== Current design is now '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.db:sortc' {"sortc"} design_analyzer> create_schematic -size infinite -gen_database Loading db file '/cad/products/synopsys/1999.10/libraries/syn/generic.sdb' Loading db file '/cad/libs/ams3.20/synopsys/csx_3.3V/csxs.sdb' Loading db file '/cad/products/synopsys/1999.10/libraries/syn/1_25.font' 1 design_analyzer> create_schematic -size infinite -symbol_view Warning: Design 'sortc' isn't mapped. (UIS-3) 1 design_analyzer> create_schematic -size infinite -hier_view Warning: Design 'sortc' isn't mapped. (UIS-3) 1 design_analyzer> create_schematic -size infinite -schematic_view Warning: Design 'sortc' isn't mapped. (UIS-3) Generating schematic for design: sortc Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_0' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_0' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_1' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_1' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'sub_52/minus/minus' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'sub_52/minus/minus' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'sub_52/minus/minus' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) The schematic for design 'sortc' has 1 page(s). 1 design_analyzer> compile -map_effort medium Information: Checking out the license 'DesignWare-Foundation'. (SEC-104) Information: Evaluating DesignWare library utilization. (UISN-27) ============================================================================ | DesignWare Library | Available | ============================================================================ | DesignWare-Basic | * | | DesignWare-Foundation | * | | class | | ============================================================================ Loading target library 'csx_IOLIB_3M' Loading target library 'csx_HRDLIB' Loading design 'sortc' Warning: In design 'sortc', there are 8 ports not connected to any nets. (LINT-30) Information: Use the 'check_design' command for more information about warnings. (LINT-99) Information: Design 'sortc' has no optimization constraints set. (OPT-108) Beginning Resource Allocation (area only) ----------------------------- Allocating blocks in 'sortc' Allocating blocks in 'sortc' Allocating blocks in 'DW01_MUX' Building model 'DW01_MUX' Information: Changed wire load model for 'DW01_MUX' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_mmux_2' Building model 'DW01_mmux_2' Information: Changed wire load model for 'DW01_mmux_2' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_mmux_3' Building model 'DW01_mmux_3' Information: Changed wire load model for 'DW01_mmux_3' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_mmux_4' Building model 'DW01_mmux_4' Information: Changed wire load model for 'DW01_mmux_4' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_mmux_5' Building model 'DW01_mmux_5' Information: Changed wire load model for 'DW01_mmux_5' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_SUB_ABC' Building model 'DW01_SUB_ABC' Information: Changed wire load model for 'DW01_SUB_ABC' from '(none)' to '10k'. (OPT-170) Setting local link library '{dw01.sldb}' on design 'DW01_sub_8' Setting local link library '{dw01.sldb}' on design 'DW01_sub_8' Loading db file '/cad/products/synopsys/2000.11/libraries/syn/dw01.sldb' Allocating blocks in 'DW01_sub_8' Allocating blocks in 'DW01_sub_8' Allocating blocks in 'DW01_add_8' Allocating blocks in 'DW01_NAND2' Building model 'DW01_NAND2' Information: Changed wire load model for 'DW01_NAND2' from '(none)' to '10k'. (OPT-170) Building model 'DW01_add_8' (csm) Information: Changed wire load model for 'DW01_add_8' from '(none)' to '10k'. (OPT-170) Warning: Design 'DW01_sub_8' inherited license information from design 'DW01_add_8'. (DDB-74) Building model 'DW01_sub_8' (csm) Information: Changed wire load model for 'DW01_sub_8' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_OR2' Building model 'DW01_OR2' Information: Changed wire load model for 'DW01_OR2' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_NOT' Building model 'DW01_NOT' Information: Changed wire load model for 'DW01_NOT' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_GP_SUM' Building model 'DW01_GP_SUM' Information: Changed wire load model for 'DW01_GP_SUM' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_AND2' Building model 'DW01_AND2' Information: Changed wire load model for 'DW01_AND2' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_AO21' Building model 'DW01_AO21' Information: Changed wire load model for 'DW01_AO21' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_sub_8' Building model 'DW01_sub_8' (bk) Information: Changed wire load model for 'DW01_sub_8' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_sub_8' Building model 'DW01_sub_8' (rpcs) Information: Changed wire load model for 'DW01_sub_8' from '(none)' to '10k'. (OPT-170) Beginning Mapping Optimizations (Medium effort) ------------------------------- Structuring 'sortc_DW01_sub_8_0' Mapping 'sortc_DW01_sub_8_0' Information: Changed wire load model for 'sortc_DW01_sub_8_0' from '(none)' to '10k'. (OPT-170) Selecting implementations in 'sortc' Structuring 'sortc_DW01_sub_8_0' Mapping 'sortc_DW01_sub_8_0' Structuring 'sortc' Mapping 'sortc' Information: Changed wire load model for 'sortc' from '(none)' to '10k'. (OPT-170) Selecting implementations in 'sortc' Beginning Delay Optimization Phase ---------------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- Beginning Area-Recovery Phase (cleanup) ----------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:41 15311.4 0.00 0.0 0.0 0:00:41 15275.0 0.00 0.0 0.0 0:00:41 15238.6 0.00 0.0 0.0 0:00:41 15202.2 0.00 0.0 0.0 0:00:41 15165.8 0.00 0.0 0.0 0:00:41 15129.4 0.00 0.0 0.0 0:00:41 15093.0 0.00 0.0 0.0 0:00:41 15056.6 0.00 0.0 0.0 0:00:41 14820.0 0.00 0.0 0.0 0:00:41 14820.0 0.00 0.0 0.0 0:00:41 14710.8 0.00 0.0 0.0 0:00:41 14638.0 0.00 0.0 0.0 0:00:41 14638.0 0.00 0.0 0.0 0:00:41 14565.2 0.00 0.0 0.0 0:00:41 14565.2 0.00 0.0 0.0 0:00:41 14528.8 0.00 0.0 0.0 Optimization Complete --------------------- Transferring design 'sortc' to database 'sortc.db' Current design is 'sortc'. 1 design_analyzer> current_design = "/cad21/caduser/cuveland/vhdl/gtu/src/sortc.db:sortc" Current design is 'sortc'. "/cad21/caduser/cuveland/vhdl/gtu/src/sortc.db:sortc" design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> create_schematic -size infinite -schematic_view -symbol_view -hier_view Generating schematic for design: sortc The schematic for design 'sortc' has 1 page(s). 1 design_analyzer> check_design Warning: In design 'sortc', port 'Q[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc', port 'Q[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc', port 'Q[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc', port 'Q[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc', port 'Q[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc', port 'Q[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc', port 'Q[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc', port 'Q[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_DW01_sub_8_0', port 'CO' is not connected to any nets. (LINT-28) 1 design_analyzer> remove_design -designs Removing file 'sortc.db' design 'sortc' design 'sortc_DW01_sub_8_0' 1 design_analyzer> read -format vhdl {"/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd"} Loading vhdl file '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd' /cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd: Warning: The VHDL design 'sortc' contains generics but was treated as a "design." To save as a "template", which can be instantiated with different parameters, use the "analyze" command. This is recommended since this does not require changing HDL code or setting any variables. Alternately reread file(s) with 'hdlin_auto_save_templates = "TRUE"', or insert the synthetic comment "template" in the HDL source. (HDL-209) Inferred memory devices in process 'reg' in routine sortc line 61 in file '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd'. =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | REG_Q_reg | Flip-flop | 8 | Y | N | N | Y | N | N | N | =============================================================================== Current design is now '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.db:sortc' {"sortc"} design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> create_schematic -size infinite -symbol_view Warning: Design 'sortc' isn't mapped. (UIS-3) 1 design_analyzer> create_schematic -size infinite -hier_view Warning: Design 'sortc' isn't mapped. (UIS-3) 1 design_analyzer> create_schematic -size infinite -schematic_view Warning: Design 'sortc' isn't mapped. (UIS-3) Generating schematic for design: sortc Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_5' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_0' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_0' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_1' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_1' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'sub_52/minus/minus' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'sub_52/minus/minus' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'sub_52/minus/minus' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) Warning: The symbol for cell 'S_8' has a pin off the route grid. You may be mixing symbol libraries with different route grids. (GEN-19) The schematic for design 'sortc' has 1 page(s). 1 design_analyzer> compile -map_effort medium Loading design 'sortc' Information: Design 'sortc' has no optimization constraints set. (OPT-108) Beginning Resource Allocation (area only) ----------------------------- Allocating blocks in 'sortc' Allocating blocks in 'sortc' Beginning Mapping Optimizations (Medium effort) ------------------------------- Structuring 'sortc_DW01_sub_8_0' Mapping 'sortc_DW01_sub_8_0' Information: Changed wire load model for 'sortc_DW01_sub_8_0' from '(none)' to '10k'. (OPT-170) Selecting implementations in 'sortc' Structuring 'sortc_DW01_sub_8_0' Mapping 'sortc_DW01_sub_8_0' Structuring 'sortc' Mapping 'sortc' Information: Changed wire load model for 'sortc' from '(none)' to '10k'. (OPT-170) Selecting implementations in 'sortc' Beginning Delay Optimization Phase ---------------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- Beginning Area-Recovery Phase (cleanup) ----------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:03 15685.8 0.00 0.0 0.0 0:00:03 15649.4 0.00 0.0 0.0 0:00:03 15613.0 0.00 0.0 0.0 0:00:03 15576.6 0.00 0.0 0.0 0:00:03 15540.2 0.00 0.0 0.0 0:00:03 15503.8 0.00 0.0 0.0 0:00:03 15467.4 0.00 0.0 0.0 0:00:03 15431.0 0.00 0.0 0.0 0:00:03 15194.4 0.00 0.0 0.0 0:00:03 15194.4 0.00 0.0 0.0 0:00:03 15085.2 0.00 0.0 0.0 0:00:03 15012.4 0.00 0.0 0.0 0:00:03 15012.4 0.00 0.0 0.0 0:00:03 14939.6 0.00 0.0 0.0 0:00:03 14939.6 0.00 0.0 0.0 0:00:03 14903.2 0.00 0.0 0.0 Optimization Complete --------------------- Transferring design 'sortc' to database 'sortc.db' Current design is 'sortc'. 1 design_analyzer> current_design = "/cad21/caduser/cuveland/vhdl/gtu/src/sortc.db:sortc" Current design is 'sortc'. "/cad21/caduser/cuveland/vhdl/gtu/src/sortc.db:sortc" design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> create_schematic -size infinite -schematic_view -symbol_view -hier_view Generating schematic for design: sortc The schematic for design 'sortc' has 1 page(s). 1 design_analyzer> read -format vhdl {"/cad21/caduser/cuveland/vhdl/gtu/src/sort.vhd"} Loading vhdl file '/cad21/caduser/cuveland/vhdl/gtu/src/sort.vhd' /cad21/caduser/cuveland/vhdl/gtu/src/sort.vhd: Warning: The VHDL design 'sort' contains generics but was treated as a "design." To save as a "template", which can be instantiated with different parameters, use the "analyze" command. This is recommended since this does not require changing HDL code or setting any variables. Alternately reread file(s) with 'hdlin_auto_save_templates = "TRUE"', or insert the synthetic comment "template" in the HDL source. (HDL-209) Current design is now '/cad21/caduser/cuveland/vhdl/gtu/src/sort.db:sort' {"sort"} design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> current_design "/cad21/caduser/cuveland/vhdl/gtu/src/sortc.db:sortc" Current design is 'sortc'. {"sortc"} design_analyzer> Information: Building the design 'sortc' instantiated from design 'sort' with the parameters "WIDTH => 13". (HDL-193) Warning: The entity 'sortc' is out of date with respect to its source file '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd'. (LBR-3) Warning: The architecture 'sortc(default)' is out of date with respect to its source file '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd'. (LBR-3) Inferred memory devices in process 'reg' in routine sortc_WIDTH13 line 60 in file '/cad21/caduser/cuveland/vhdl/gtu/src/sortc.vhd'. =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | REG_Q_reg | Flip-flop | 13 | Y | N | N | Y | N | N | N | =============================================================================== current_design "/cad21/caduser/cuveland/vhdl/gtu/src/sort.db:sort" Current design is 'sort'. {"sort"} design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> create_schematic -size infinite -symbol_view 1 design_analyzer> create_schematic -size infinite -hier_view 1 design_analyzer> create_schematic -size infinite -schematic_view Generating schematic for design: sort The schematic for design 'sort' has 1 page(s). 1 design_analyzer> compile -map_effort medium Loading design 'sort' Warning: Design 'sortc_WIDTH13' is instantiated 10 times. (LINT-45) Error: Use the 'uniquify' command to fix multiply instantiated designs. (OPT-124) Error: Compile terminated abnormally. (OPT-100) Current design is 'sort'. 0 design_analyzer> current_design = "/cad21/caduser/cuveland/vhdl/gtu/src/sort.db:sort" Current design is 'sort'. "/cad21/caduser/cuveland/vhdl/gtu/src/sort.db:sort" design_analyzer> create_schematic -size infinite -schematic_view -symbol_view -hier_view Generating schematic for design: sort The schematic for design 'sort' has 1 page(s). 1 design_analyzer> uniquify Uniquifying cell 'cell_6' in design 'sort'. New design is 'sortc_WIDTH13_0'. Uniquifying cell 'cell_9' in design 'sort'. New design is 'sortc_WIDTH13_1'. Uniquifying cell 'cell_8' in design 'sort'. New design is 'sortc_WIDTH13_2'. Uniquifying cell 'cell_7' in design 'sort'. New design is 'sortc_WIDTH13_3'. Uniquifying cell 'cell_5' in design 'sort'. New design is 'sortc_WIDTH13_4'. Uniquifying cell 'cell_3' in design 'sort'. New design is 'sortc_WIDTH13_5'. Uniquifying cell 'cell_2' in design 'sort'. New design is 'sortc_WIDTH13_6'. Uniquifying cell 'cell_1' in design 'sort'. New design is 'sortc_WIDTH13_7'. Uniquifying cell 'cell' in design 'sort'. New design is 'sortc_WIDTH13_8'. Uniquifying cell 'cell_4' in design 'sort'. New design is 'sortc_WIDTH13_9'. 1 design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> compile -map_effort medium Loading design 'sort' Warning: In design 'sort', there is 1 submodule connected to power or ground. (LINT-30) Warning: In design 'sort', there is 1 submodule with pins connected to the same net. (LINT-30) Warning: In design 'sortc_WIDTH13_9', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_8', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_7', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_6', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_5', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_4', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_3', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_2', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_1', there are 13 ports not connected to any nets. (LINT-30) Warning: In design 'sortc_WIDTH13_0', there are 13 ports not connected to any nets. (LINT-30) Information: Use the 'check_design' command for more information about warnings. (LINT-99) Information: Design 'sort' has no optimization constraints set. (OPT-108) Beginning Resource Allocation (area only) ----------------------------- Allocating blocks in 'sort' Allocating blocks in 'cell_4' Allocating blocks in 'cell_4' Setting local link library '{dw01.sldb}' on design 'DW01_sub_13' Setting local link library '{dw01.sldb}' on design 'DW01_sub_13' Allocating blocks in 'DW01_sub_13' Allocating blocks in 'DW01_sub_13' Allocating blocks in 'DW01_add_13' Building model 'DW01_add_13' (csm) Information: Changed wire load model for 'DW01_add_13' from '(none)' to '10k'. (OPT-170) Warning: Design 'DW01_sub_13' inherited license information from design 'DW01_add_13'. (DDB-74) Building model 'DW01_sub_13' (csm) Information: Changed wire load model for 'DW01_sub_13' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_sub_13' Building model 'DW01_sub_13' (bk) Information: Changed wire load model for 'DW01_sub_13' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'DW01_sub_13' Building model 'DW01_sub_13' (rpcs) Information: Changed wire load model for 'DW01_sub_13' from '(none)' to '10k'. (OPT-170) Allocating blocks in 'cell' Allocating blocks in 'cell' Allocating blocks in 'cell_1' Allocating blocks in 'cell_1' Allocating blocks in 'cell_2' Allocating blocks in 'cell_2' Allocating blocks in 'cell_3' Allocating blocks in 'cell_3' Allocating blocks in 'cell_5' Allocating blocks in 'cell_5' Allocating blocks in 'cell_7' Allocating blocks in 'cell_7' Allocating blocks in 'cell_8' Allocating blocks in 'cell_8' Allocating blocks in 'cell_9' Allocating blocks in 'cell_9' Allocating blocks in 'cell_6' Allocating blocks in 'cell_6' Beginning Mapping Optimizations (Medium effort) ------------------------------- Structuring 'sortc_WIDTH13_0_DW01_sub_13_0' Mapping 'sortc_WIDTH13_0_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_0_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_1_DW01_sub_13_0' Mapping 'sortc_WIDTH13_1_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_1_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_2_DW01_sub_13_0' Mapping 'sortc_WIDTH13_2_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_2_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_3_DW01_sub_13_0' Mapping 'sortc_WIDTH13_3_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_3_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_4_DW01_sub_13_0' Mapping 'sortc_WIDTH13_4_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_4_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_5_DW01_sub_13_0' Mapping 'sortc_WIDTH13_5_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_5_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_6_DW01_sub_13_0' Mapping 'sortc_WIDTH13_6_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_6_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_7_DW01_sub_13_0' Mapping 'sortc_WIDTH13_7_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_7_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_8_DW01_sub_13_0' Mapping 'sortc_WIDTH13_8_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_8_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_9_DW01_sub_13_0' Mapping 'sortc_WIDTH13_9_DW01_sub_13_0' Information: Changed wire load model for 'sortc_WIDTH13_9_DW01_sub_13_0' from '(none)' to '10k'. (OPT-170) Selecting implementations in 'cell_4' Selecting implementations in 'cell' Selecting implementations in 'cell_1' Selecting implementations in 'cell_2' Selecting implementations in 'cell_3' Selecting implementations in 'cell_5' Selecting implementations in 'cell_7' Selecting implementations in 'cell_8' Selecting implementations in 'cell_9' Selecting implementations in 'cell_6' Structuring 'sortc_WIDTH13_9_DW01_sub_13_0' Mapping 'sortc_WIDTH13_9_DW01_sub_13_0' Structuring 'sortc_WIDTH13_8_DW01_sub_13_0' Mapping 'sortc_WIDTH13_8_DW01_sub_13_0' Structuring 'sortc_WIDTH13_7_DW01_sub_13_0' Mapping 'sortc_WIDTH13_7_DW01_sub_13_0' Structuring 'sortc_WIDTH13_6_DW01_sub_13_0' Mapping 'sortc_WIDTH13_6_DW01_sub_13_0' Structuring 'sortc_WIDTH13_5_DW01_sub_13_0' Mapping 'sortc_WIDTH13_5_DW01_sub_13_0' Structuring 'sortc_WIDTH13_4_DW01_sub_13_0' Mapping 'sortc_WIDTH13_4_DW01_sub_13_0' Structuring 'sortc_WIDTH13_3_DW01_sub_13_0' Mapping 'sortc_WIDTH13_3_DW01_sub_13_0' Structuring 'sortc_WIDTH13_2_DW01_sub_13_0' Mapping 'sortc_WIDTH13_2_DW01_sub_13_0' Structuring 'sortc_WIDTH13_1_DW01_sub_13_0' Mapping 'sortc_WIDTH13_1_DW01_sub_13_0' Structuring 'sortc_WIDTH13_0_DW01_sub_13_0' Mapping 'sortc_WIDTH13_0_DW01_sub_13_0' Structuring 'sortc_WIDTH13_0' Mapping 'sortc_WIDTH13_0' Information: Changed wire load model for 'sortc_WIDTH13_0' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_1' Mapping 'sortc_WIDTH13_1' Information: Changed wire load model for 'sortc_WIDTH13_1' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_2' Mapping 'sortc_WIDTH13_2' Information: Changed wire load model for 'sortc_WIDTH13_2' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_3' Mapping 'sortc_WIDTH13_3' Information: Changed wire load model for 'sortc_WIDTH13_3' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_4' Mapping 'sortc_WIDTH13_4' Information: Changed wire load model for 'sortc_WIDTH13_4' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_5' Mapping 'sortc_WIDTH13_5' Information: Changed wire load model for 'sortc_WIDTH13_5' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_6' Mapping 'sortc_WIDTH13_6' Information: Changed wire load model for 'sortc_WIDTH13_6' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_7' Mapping 'sortc_WIDTH13_7' Information: Changed wire load model for 'sortc_WIDTH13_7' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_8' Mapping 'sortc_WIDTH13_8' Information: Changed wire load model for 'sortc_WIDTH13_8' from '(none)' to '10k'. (OPT-170) Structuring 'sortc_WIDTH13_9' Mapping 'sortc_WIDTH13_9' Information: Changed wire load model for 'sortc_WIDTH13_9' from '(none)' to '10k'. (OPT-170) Information: Changed wire load model for 'sort' from '(none)' to '10k'. (OPT-170) Selecting implementations in 'cell_4' Selecting implementations in 'cell' Selecting implementations in 'cell_1' Selecting implementations in 'cell_2' Selecting implementations in 'cell_3' Selecting implementations in 'cell_5' Selecting implementations in 'cell_7' Selecting implementations in 'cell_8' Selecting implementations in 'cell_9' Selecting implementations in 'cell_6' Beginning Delay Optimization Phase ---------------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- Beginning Phase 1 Design Rule Fixing (max_transition) ------------------------------------ ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:45 264134.0 0.00 0.0 0.2 cell_6/ACCEPT_OUT 0:00:45 264134.0 0.00 0.0 0.2 cell_6/ACCEPT_OUT 0:00:45 264134.0 0.00 0.0 0.2 0:00:45 264217.2 0.00 0.0 0.1 cell_4/ACCEPT_OUT 0:00:45 264217.2 0.00 0.0 0.1 cell_4/ACCEPT_OUT 0:00:45 264217.2 0.00 0.0 0.1 0:00:45 264300.4 0.00 0.0 0.0 cell_2/ACCEPT_OUT 0:00:45 264300.4 0.00 0.0 0.0 cell_2/ACCEPT_OUT 0:00:45 264300.4 0.00 0.0 0.0 0:00:45 264300.4 0.00 0.0 0.0 cell_1/ACCEPT_OUT 0:00:45 264300.4 0.00 0.0 0.0 cell_8/ACCEPT_OUT 0:00:45 264300.4 0.00 0.0 0.0 cell/ACCEPT_OUT Beginning Area-Recovery Phase (cleanup) ----------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:45 264217.2 0.00 0.0 0.0 0:00:45 264134.0 0.00 0.0 0.0 0:00:45 264050.8 0.00 0.0 0.0 0:00:46 264014.4 0.00 0.0 0.0 0:00:46 263978.0 0.00 0.0 0.0 0:00:46 263941.6 0.00 0.0 0.0 0:00:46 263905.2 0.00 0.0 0.0 0:00:46 263868.8 0.00 0.0 0.0 0:00:46 263832.4 0.00 0.0 0.0 0:00:46 263796.0 0.00 0.0 0.0 0:00:46 263759.6 0.00 0.0 0.0 0:00:46 263723.2 0.00 0.0 0.0 0:00:46 263686.8 0.00 0.0 0.0 0:00:46 263650.4 0.00 0.0 0.0 0:00:46 263614.0 0.00 0.0 0.0 0:00:47 263577.6 0.00 0.0 0.0 0:00:47 263541.2 0.00 0.0 0.0 0:00:47 263504.8 0.00 0.0 0.0 0:00:47 263468.4 0.00 0.0 0.0 0:00:47 263432.0 0.00 0.0 0.0 0:00:47 263395.6 0.00 0.0 0.0 0:00:47 263359.2 0.00 0.0 0.0 0:00:47 263322.8 0.00 0.0 0.0 0:00:47 263286.4 0.00 0.0 0.0 0:00:47 263250.0 0.00 0.0 0.0 0:00:47 263213.6 0.00 0.0 0.0 0:00:47 263177.2 0.00 0.0 0.0 0:00:47 263140.8 0.00 0.0 0.0 0:00:47 263104.4 0.00 0.0 0.0 0:00:48 263068.0 0.00 0.0 0.0 0:00:48 263031.6 0.00 0.0 0.0 0:00:48 262995.2 0.00 0.0 0.0 0:00:48 262958.8 0.00 0.0 0.0 0:00:48 262922.4 0.00 0.0 0.0 0:00:48 262886.0 0.00 0.0 0.0 0:00:48 262849.6 0.00 0.0 0.0 0:00:48 262813.2 0.00 0.0 0.0 0:00:48 262776.8 0.00 0.0 0.0 0:00:48 262740.4 0.00 0.0 0.0 0:00:48 262704.0 0.00 0.0 0.0 0:00:48 262667.6 0.00 0.0 0.0 0:00:48 262631.2 0.00 0.0 0.0 0:00:48 262594.8 0.00 0.0 0.0 0:00:48 262558.4 0.00 0.0 0.0 0:00:48 262522.0 0.00 0.0 0.0 0:00:48 262485.6 0.00 0.0 0.0 0:00:48 262449.2 0.00 0.0 0.0 0:00:48 262412.8 0.00 0.0 0.0 0:00:48 262376.4 0.00 0.0 0.0 0:00:49 262340.0 0.00 0.0 0.0 0:00:49 262303.6 0.00 0.0 0.0 0:00:49 262267.2 0.00 0.0 0.0 0:00:49 262230.8 0.00 0.0 0.0 0:00:49 262194.4 0.00 0.0 0.0 0:00:49 262158.0 0.00 0.0 0.0 0:00:49 262121.6 0.00 0.0 0.0 0:00:49 262085.2 0.00 0.0 0.0 0:00:49 262048.8 0.00 0.0 0.0 0:00:49 262012.4 0.00 0.0 0.0 0:00:49 261976.0 0.00 0.0 0.0 0:00:49 261939.6 0.00 0.0 0.0 0:00:49 261903.2 0.00 0.0 0.0 0:00:49 261866.8 0.00 0.0 0.0 0:00:49 261830.4 0.00 0.0 0.0 0:00:49 261794.0 0.00 0.0 0.0 0:00:49 261757.6 0.00 0.0 0.0 0:00:49 261721.2 0.00 0.0 0.0 0:00:49 261684.8 0.00 0.0 0.0 0:00:50 261648.4 0.00 0.0 0.0 0:00:50 261612.0 0.00 0.0 0.0 0:00:50 261575.6 0.00 0.0 0.0 0:00:50 261539.2 0.00 0.0 0.0 0:00:50 261502.8 0.00 0.0 0.0 0:00:50 261466.4 0.00 0.0 0.0 0:00:50 261430.0 0.00 0.0 0.0 0:00:50 261393.6 0.00 0.0 0.0 0:00:50 261357.2 0.00 0.0 0.0 0:00:50 261320.8 0.00 0.0 0.0 0:00:50 261284.4 0.00 0.0 0.0 0:00:50 261248.0 0.00 0.0 0.0 0:00:50 261211.6 0.00 0.0 0.0 0:00:50 261175.2 0.00 0.0 0.0 0:00:50 261138.8 0.00 0.0 0.0 0:00:50 261102.4 0.00 0.0 0.0 0:00:50 261066.0 0.00 0.0 0.0 0:00:50 261029.6 0.00 0.0 0.0 0:00:50 260993.2 0.00 0.0 0.0 0:00:51 260956.8 0.00 0.0 0.0 0:00:51 260920.4 0.00 0.0 0.0 0:00:51 260884.0 0.00 0.0 0.0 0:00:51 260847.6 0.00 0.0 0.0 0:00:51 260811.2 0.00 0.0 0.0 0:00:51 260774.8 0.00 0.0 0.0 0:00:51 260738.4 0.00 0.0 0.0 0:00:51 260702.0 0.00 0.0 0.0 0:00:51 260665.6 0.00 0.0 0.0 0:00:51 260629.2 0.00 0.0 0.0 0:00:51 260592.8 0.00 0.0 0.0 0:00:51 260556.4 0.00 0.0 0.0 0:00:51 260520.0 0.00 0.0 0.0 0:00:51 260483.6 0.00 0.0 0.0 0:00:51 260447.2 0.00 0.0 0.0 0:00:51 260410.8 0.00 0.0 0.0 0:00:51 260374.4 0.00 0.0 0.0 0:00:51 260338.0 0.00 0.0 0.0 0:00:52 260301.6 0.00 0.0 0.0 0:00:52 260265.2 0.00 0.0 0.0 0:00:52 260228.8 0.00 0.0 0.0 0:00:52 260192.4 0.00 0.0 0.0 0:00:52 260156.0 0.00 0.0 0.0 0:00:52 260119.6 0.00 0.0 0.0 0:00:52 260083.2 0.00 0.0 0.0 0:00:52 260046.8 0.00 0.0 0.0 0:00:52 260010.4 0.00 0.0 0.0 0:00:52 259974.0 0.00 0.0 0.0 0:00:52 259937.6 0.00 0.0 0.0 0:00:52 259901.2 0.00 0.0 0.0 0:00:52 259864.8 0.00 0.0 0.0 0:00:52 259828.4 0.00 0.0 0.0 0:00:52 259792.0 0.00 0.0 0.0 0:00:52 259755.6 0.00 0.0 0.0 0:00:52 259719.2 0.00 0.0 0.0 0:00:52 259682.8 0.00 0.0 0.0 0:00:52 259646.4 0.00 0.0 0.0 0:00:53 259610.0 0.00 0.0 0.0 0:00:53 259573.6 0.00 0.0 0.0 0:00:53 259537.2 0.00 0.0 0.0 0:00:53 259500.8 0.00 0.0 0.0 0:00:53 259464.4 0.00 0.0 0.0 0:00:53 259428.0 0.00 0.0 0.0 0:00:53 259391.6 0.00 0.0 0.0 0:00:53 259355.2 0.00 0.0 0.0 0:00:53 259318.8 0.00 0.0 0.0 0:00:54 259064.0 0.00 0.0 0.0 0:00:54 259064.0 0.00 0.0 0.0 0:00:54 259064.0 0.00 0.0 0.0 0:00:54 258809.2 0.00 0.0 0.0 0:00:54 258809.2 0.00 0.0 0.0 0:00:54 258809.2 0.00 0.0 0.0 0:00:54 258554.4 0.00 0.0 0.0 0:00:54 258554.4 0.00 0.0 0.0 0:00:54 258554.4 0.00 0.0 0.0 0:00:54 258299.6 0.00 0.0 0.0 0:00:54 258299.6 0.00 0.0 0.0 0:00:54 258299.6 0.00 0.0 0.0 0:00:54 258044.8 0.00 0.0 0.0 0:00:54 258044.8 0.00 0.0 0.0 0:00:54 258044.8 0.00 0.0 0.0 0:00:54 257790.0 0.00 0.0 0.0 0:00:54 257790.0 0.00 0.0 0.0 0:00:54 257790.0 0.00 0.0 0.0 0:00:54 257535.2 0.00 0.0 0.0 0:00:54 257535.2 0.00 0.0 0.0 0:00:54 257535.2 0.00 0.0 0.0 0:00:54 257280.4 0.00 0.0 0.0 0:00:54 257280.4 0.00 0.0 0.0 0:00:54 257280.4 0.00 0.0 0.0 0:00:54 257025.6 0.00 0.0 0.0 0:00:54 257025.6 0.00 0.0 0.0 0:00:54 257025.6 0.00 0.0 0.0 0:00:54 256770.8 0.00 0.0 0.0 0:00:54 256770.8 0.00 0.0 0.0 0:00:54 256770.8 0.00 0.0 0.0 0:00:54 256698.0 0.00 0.0 0.0 0:00:54 256698.0 0.00 0.0 0.0 0:00:54 256625.2 0.00 0.0 0.0 0:00:54 256625.2 0.00 0.0 0.0 0:00:54 256552.4 0.00 0.0 0.0 0:00:54 256552.4 0.00 0.0 0.0 0:00:54 256479.6 0.00 0.0 0.0 0:00:54 256479.6 0.00 0.0 0.0 0:00:54 256406.8 0.00 0.0 0.0 0:00:54 256406.8 0.00 0.0 0.0 0:00:54 256334.0 0.00 0.0 0.0 0:00:54 256334.0 0.00 0.0 0.0 0:00:54 256261.2 0.00 0.0 0.0 0:00:54 256261.2 0.00 0.0 0.0 0:00:54 256188.4 0.00 0.0 0.0 0:00:54 256188.4 0.00 0.0 0.0 0:00:54 256115.6 0.00 0.0 0.0 0:00:54 256115.6 0.00 0.0 0.0 0:00:54 256042.8 0.00 0.0 0.0 0:00:54 256042.8 0.00 0.0 0.0 0:00:54 255970.0 0.00 0.0 0.0 0:00:54 255970.0 0.00 0.0 0.0 0:00:54 255897.2 0.00 0.0 0.0 0:00:54 255897.2 0.00 0.0 0.0 0:00:54 255824.4 0.00 0.0 0.0 0:00:54 255824.4 0.00 0.0 0.0 0:00:54 255751.6 0.00 0.0 0.0 0:00:54 255751.6 0.00 0.0 0.0 0:00:54 255678.8 0.00 0.0 0.0 0:00:54 255678.8 0.00 0.0 0.0 0:00:54 255606.0 0.00 0.0 0.0 0:00:54 255606.0 0.00 0.0 0.0 0:00:54 255533.2 0.00 0.0 0.0 0:00:54 255533.2 0.00 0.0 0.0 0:00:54 255460.4 0.00 0.0 0.0 0:00:54 255460.4 0.00 0.0 0.0 0:00:54 255387.6 0.00 0.0 0.0 0:00:54 255387.6 0.00 0.0 0.0 0:00:55 255314.8 0.00 0.0 0.0 0:00:55 255314.8 0.00 0.0 0.0 0:00:55 255242.0 0.00 0.0 0.0 0:00:55 255242.0 0.00 0.0 0.0 0:00:55 255169.2 0.00 0.0 0.0 0:00:55 255169.2 0.00 0.0 0.0 0:00:55 255096.4 0.00 0.0 0.0 0:00:55 255096.4 0.00 0.0 0.0 0:00:55 255023.6 0.00 0.0 0.0 0:00:55 255023.6 0.00 0.0 0.0 0:00:55 254950.8 0.00 0.0 0.0 0:00:55 254950.8 0.00 0.0 0.0 0:00:55 254878.0 0.00 0.0 0.0 0:00:55 254878.0 0.00 0.0 0.0 0:00:55 254805.2 0.00 0.0 0.0 0:00:55 254805.2 0.00 0.0 0.0 0:00:55 254732.4 0.00 0.0 0.0 0:00:55 254732.4 0.00 0.0 0.0 0:00:55 254659.6 0.00 0.0 0.0 0:00:55 254659.6 0.00 0.0 0.0 0:00:55 254586.8 0.00 0.0 0.0 0:00:55 254586.8 0.00 0.0 0.0 0:00:55 254459.4 0.00 0.0 0.0 0:00:55 254386.6 0.00 0.0 0.0 0:00:55 254386.6 0.00 0.0 0.0 0:00:55 254259.2 0.00 0.0 0.0 0:00:55 254186.4 0.00 0.0 0.0 0:00:55 254186.4 0.00 0.0 0.0 0:00:55 254059.0 0.00 0.0 0.0 0:00:55 253986.2 0.00 0.0 0.0 0:00:55 253986.2 0.00 0.0 0.0 0:00:55 253858.8 0.00 0.0 0.0 0:00:55 253786.0 0.00 0.0 0.0 0:00:55 253786.0 0.00 0.0 0.0 0:00:55 253658.6 0.00 0.0 0.0 0:00:55 253585.8 0.00 0.0 0.0 0:00:55 253585.8 0.00 0.0 0.0 0:00:55 253458.4 0.00 0.0 0.0 0:00:55 253385.6 0.00 0.0 0.0 0:00:55 253385.6 0.00 0.0 0.0 0:00:55 253258.2 0.00 0.0 0.0 0:00:55 253185.4 0.00 0.0 0.0 0:00:55 253185.4 0.00 0.0 0.0 0:00:55 253058.0 0.00 0.0 0.0 0:00:55 252985.2 0.00 0.0 0.0 0:00:55 252985.2 0.00 0.0 0.0 0:00:55 252857.8 0.00 0.0 0.0 0:00:55 252785.0 0.00 0.0 0.0 0:00:55 252785.0 0.00 0.0 0.0 0:00:55 252657.6 0.00 0.0 0.0 0:00:55 252584.8 0.00 0.0 0.0 0:00:55 252584.8 0.00 0.0 0.0 0:00:55 252512.0 0.00 0.0 0.0 0:00:55 252512.0 0.00 0.0 0.0 0:00:55 252439.2 0.00 0.0 0.0 0:00:55 252439.2 0.00 0.0 0.0 0:00:55 252366.4 0.00 0.0 0.0 0:00:55 252366.4 0.00 0.0 0.0 0:00:55 252293.6 0.00 0.0 0.0 0:00:55 252293.6 0.00 0.0 0.0 0:00:55 252220.8 0.00 0.0 0.0 0:00:55 252220.8 0.00 0.0 0.0 0:00:55 252148.0 0.00 0.0 0.0 0:00:55 252148.0 0.00 0.0 0.0 0:00:55 252075.2 0.00 0.0 0.0 0:00:55 252075.2 0.00 0.0 0.0 0:00:55 252002.4 0.00 0.0 0.0 0:00:55 252002.4 0.00 0.0 0.0 0:00:55 251929.6 0.00 0.0 0.0 0:00:55 251929.6 0.00 0.0 0.0 0:00:55 251856.8 0.00 0.0 0.0 0:00:55 251856.8 0.00 0.0 0.0 0:00:56 251820.4 0.00 0.0 0.0 0:00:56 251784.0 0.00 0.0 0.0 0:00:56 251747.6 0.00 0.0 0.0 0:00:56 251711.2 0.00 0.0 0.0 0:00:56 251674.8 0.00 0.0 0.0 0:00:56 251638.4 0.00 0.0 0.0 0:00:56 251602.0 0.00 0.0 0.0 0:00:56 251565.6 0.00 0.0 0.0 0:00:56 251529.2 0.00 0.0 0.0 0:00:56 251492.8 0.00 0.0 0.0 Optimization Complete --------------------- Transferring design 'sort' to database 'sort.db' Current design is 'sort'. 1 design_analyzer> current_design = "/cad21/caduser/cuveland/vhdl/gtu/src/sort.db:sort" Current design is 'sort'. "/cad21/caduser/cuveland/vhdl/gtu/src/sort.db:sort" design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> create_schematic -size infinite -schematic_view -symbol_view -hier_view Generating schematic for design: sort The schematic for design 'sort' has 1 page(s). 1 design_analyzer> current_instance "cell_4" Current instance is '/sort/cell_4'. "/sort/cell_4" design_analyzer> create_schematic -size infinite -symbol_view -reference 1 design_analyzer> create_schematic -size infinite -hier_view -reference 1 design_analyzer> create_schematic -size infinite -schematic_view -reference Generating schematic for design: sortc_WIDTH13_9 The schematic for design 'sortc_WIDTH13_9' has 1 page(s). 1 design_analyzer> current_instance ".." Current instance is the top-level of design 'sort'. "" design_analyzer> check_design Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[2]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[6]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[4]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[11]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[8]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[3]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[7]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[5]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[1]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[10]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[9]'. (LINT-31) Warning: In design 'sort', output port 'TEST_OUT[12]' is connected directly to output port 'TEST_OUT[0]'. (LINT-31) Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_4'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'ACCEPT_IN', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_1'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_2'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_3'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_5'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_7'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_8'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', cell 'cell_9' does not drive any nets. (LINT-1) Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_9'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sort', the same net is connected to more than one pin on submodule 'cell_6'. (LINT-33) Net 'D[8][11]' is connected to pins 'D[12]', 'D[9]', 'D[4]', 'D[0]', 'D[6]', 'D[2]', 'D[11]', 'D[10]', 'D[8]', 'D[7]', 'D[3]', 'D[1]', 'D[5]'. Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_9_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_8_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_7_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_6_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_5_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_4_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_3_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_2_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_1_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[1]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[3]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[5]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[7]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[9]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[11]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[10]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[8]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[6]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[4]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[2]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0', output port 'Q[12]' is connected directly to output port 'Q[0]'. (LINT-31) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'CI' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[11]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[10]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[9]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[8]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[7]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[6]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[5]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[4]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[3]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[2]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[1]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'DIFF[0]' is not connected to any nets. (LINT-28) Warning: In design 'sortc_WIDTH13_0_DW01_sub_13_0', port 'CO' is not connected to any nets. (LINT-28) 1 design_analyzer> uniquify 1 design_analyzer> flatten Error: Undefined operator on or near line 46 at or near 'flatten'. (EQN-2) design_analyzer> uniquify -flatten Error: Unexpected argument '-flatten'. (EQN-18) Usage: uniquify -force (force the uniquify_naming_style on all designs) -base_name (use this as the base name for new design names instead of original design name) -cell (force generation of new designs for these cells) -reference (force generation of new designs for all cells referencing this design) -new_name (use this name for the new design of the given cell) 0 design_analyzer> highlight_path -critical_path Timing design: 'sort' Information: Updating design information... (UID-85) 1 design_analyzer> Thank you...