FILES
{
	VHDL_FILE = ..\src\gtu_types.vhd;
	VHDL_FILE = ..\src\buffer_merger.vhd;
	VHDL_FILE = ..\src\z_channel.vhd;
	VHDL_FILE = ..\src\toplevel.vhd;
	VHDL_FILE = ..\src\sorter.vhd;
	VHDL_FILE = ..\src\proj_y.vhd;
	VHDL_FILE = ..\src\proj_d.vhd;
	VHDL_FILE = ..\src\matching_memory.vhd;
	VHDL_FILE = ..\src\matching_logic.vhd;
	VHDL_FILE = ..\src\match.vhd;
	VHDL_FILE = ..\src\inputcontrol.vhd;
	VHDL_FILE = ..\src\input.vhd;
	VHDL_FILE = ..\src\zch_table.vhd;
	TEXT_FORMAT_REPORT_FILE = "toplevel Compilation Report.rpt";
}
COMPILER_SETTINGS_LIST
{
	COMPILER_SETTINGS = toplevel;
}
SIMULATOR_SETTINGS_LIST
{
	SIMULATOR_SETTINGS = toplevel;
}
SOFTWARE_SETTINGS_LIST
{
	SOFTWARE_SETTINGS = Debug;
	SOFTWARE_SETTINGS = Release;
}