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library ieee;
use ieee.std_logic_1164.all;

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entity sort_tb is

end sort_tb;

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architecture default of sort_tb is

  component sort
    generic (
      WIDTH : integer;
      DEPTH : integer);
    port (
      CLK : in std_logic;
      RST : in std_logic;
      EN  : in std_logic;
      A   : in std_logic_vector);
  end component;

  constant WIDTH : integer := 8;
  constant DEPTH : integer := 8;

  signal CLK_i : std_logic;
  signal RST_i : std_logic;
  signal EN_i  : std_logic;
  signal A_i   : std_logic_vector;

begin  -- default

  DUT: sort
    generic map (
        WIDTH => WIDTH,
        DEPTH => DEPTH)
    port map (
        CLK => CLK_i,
        RST => RST_i,
        EN  => EN_i,
        A   => A_i);

  

end default;

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