library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity test is
  port (
    vec  : in  std_logic_vector(7 downto 0);
    bool : out boolean);
end;

architecture default of test is

  function test_func (
    signal   vec  : std_logic_vector(7 downto 0))
    return boolean is
    variable temp : real := 1.0;
  begin
--    if vec(0) = '1' then
--      temp               := 1.0;
      temp               := -1.0;
--    end if;
    return true;
  end;

begin
  bool <= test_func(vec);
end;