-------------------------------------------------------------------------------
-- Title      : Z-Channel Sorter Unit
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : z_channel.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    :
-- Last update: 2003/05/26
-- Platform   :
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/03/10  1.0      cuveland        Created
-- 2006/06/22  1.1      angelov         Memory instantiated
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.gtu_types.all;

-------------------------------------------------------------------------------

entity z_channel is

  generic (
    plane         : integer := 1;            -- 0..5
    channel_index : integer := 1);           -- 0..2

  port (
    chamber : in unsigned(2 downto 0);

    clk   : in std_logic;
    rst_n : in std_logic;

    valid_in : in std_logic;

    y_in    : in signed(PROJ_YPOS_WIDTH-1 downto 0);
    a_in    : in signed(DEFLANG_WIDTH-1 downto 0);
    z_in    : in unsigned(ZPOS_WIDTH-1 downto 0);
    addr_in : in unsigned(ADDR_WIDTH-1 downto 0);

    valid_out : out std_logic;

    y_out    : out signed(PROJ_YPOS_WIDTH-1 downto 0);
    a_out    : out signed(DEFLANG_WIDTH-1 downto 0);
    idx_out  : out unsigned(IDX_WIDTH-1 downto 0);
    addr_out : out unsigned(ADDR_WIDTH-1 downto 0);

    addr2_out : out unsigned(ADDR_WIDTH-1 downto 0));

end z_channel;

-------------------------------------------------------------------------------

architecture default of z_channel is

component dpram64xN is
generic (Nd : Integer := 21);
port(
         clk  : in  std_logic;
         we   : in  std_logic;
         wa   : in  unsigned(   5 downto 0);
         din  : in  std_logic_vector(Nd-1 downto 0);
         ra   : in  unsigned(   5 downto 0);
         dout : out std_logic_vector(Nd-1 downto 0)
         );
end component;

  -- internal signals
  signal idx       : unsigned(IDX_WIDTH-1 downto 0);
  signal addr2_cnt : unsigned(ADDR_WIDTH-1 downto 0);

--type mem is array (0 to 63) of std_logic_vector(DEFLANG_WIDTH-1 downto 0);
--signal ram_block        : mem;

  -- output signals
  signal valid_out_i : std_logic;
  signal idx_out_i   : unsigned(IDX_WIDTH-1 downto 0);
  signal addr_out_i  : unsigned(ADDR_WIDTH-1 downto 0);
  signal a_out_s     : std_logic_vector(DEFLANG_WIDTH-1 downto 0);

begin  -- default

  zch_table1 : entity work.zch_table
    generic map (
      plane   => plane,
      zunit   => channel_index)
    port map (
      chamber => chamber,
      z       => z_in,
      index   => idx);

  sorter1 : entity work.sorter
    generic map (
      depth     => 8)
    port map (
      clk       => clk,
      rst_n     => rst_n,
      valid_in  => valid_in,
      y_in      => y_in,
      idx_in    => idx,
      addr_in   => addr_in,
      valid_out => valid_out_i,
      y_out     => y_out,
      idx_out   => idx_out_i,
      addr_out  => addr_out_i);

---- ram block
--process (clk)
--begin
--  if clk'event and clk = '1' then
--    if valid_in = '1' then
--      ram_block(conv_integer(addr_in)) <= std_logic_vector(a_in);
--    end if;
--  end if;
--end process;
--a_out     <= signed(ram_block(conv_integer(addr_out_i)));

ramb: dpram64xN
    generic map (Nd => a_in'length)
    port map(
         clk  => clk,
         we   => valid_in,
         wa   => addr_in,
         din  => std_logic_vector(a_in),
         ra   => addr_out_i,
         dout => a_out_s
         );
  a_out     <= signed(a_out_s);

  -- address_2 counter
  process (clk, rst_n)
  begin
    if rst_n = '0' then
      addr2_cnt <= "000000";
    elsif clk'event and clk = '1' then
      if valid_out_i = '1' then
        if idx_out_i = unsigned(conv_signed(-1, IDX_WIDTH)) then
          addr2_cnt <= (addr2_cnt'range => '0');
        else
          addr2_cnt <= addr2_cnt + 1;
        end if;
      end if;
    end if;
  end process;

  -- output signals
  valid_out <= valid_out_i;
  idx_out   <= idx_out_i;
  addr_out  <= addr_out_i;
  addr2_out <= addr2_cnt;

end default;