------------------------------------------------------------------------------- -- Title : Uniquifier for track candidates -- Project : Prototype implementation of the GTU of the Alice TRD Experiment ------------------------------------------------------------------------------- -- File : unique.vhd -- Author : Jan de Cuveland -- Company : -- Last update: 2004/04/29 -- Platform : ------------------------------------------------------------------------------- -- This is a prototype implementation of the Global Tracking Unit (GTU) -- of the Alice TRD detector. ------------------------------------------------------------------------------- -- Description: Uniquifies track candidates from different seedlines/z-channels ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/06/04 1.0 cuveland Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.gtu_types.all; use work.track_types.all; ------------------------------------------------------------------------------- entity unique is port ( clk : in std_logic; rst_n : in std_logic; pretrigger : in std_logic; valid_in : in std_logic_vector(8 downto 0); ready_in : in std_logic_vector(8 downto 0); track8_in : in std_logic_vector(track_with_idx_width-1 downto 0); track7_in : in std_logic_vector(track_with_idx_width-1 downto 0); track6_in : in std_logic_vector(track_with_idx_width-1 downto 0); track5_in : in std_logic_vector(track_with_idx_width-1 downto 0); track4_in : in std_logic_vector(track_with_idx_width-1 downto 0); track3_in : in std_logic_vector(track_with_idx_width-1 downto 0); track2_in : in std_logic_vector(track_with_idx_width-1 downto 0); track1_in : in std_logic_vector(track_with_idx_width-1 downto 0); track0_in : in std_logic_vector(track_with_idx_width-1 downto 0); valid_out : out std_logic; ready_out : out std_logic; track_out : out std_logic_vector(track_width-1 downto 0)); end; ------------------------------------------------------------------------------- architecture default of unique is type slv3_t3 is array (2 downto 0) of std_logic_vector(2 downto 0); type track_with_idx_t3 is array (2 downto 0) of track_with_idx_t; type track_with_idx_t33 is array (2 downto 0) of track_with_idx_t3; -- input signals signal valid_in_i : slv3_t3; signal ready_in_i : slv3_t3; signal track_in : track_with_idx_t33; -- internal signals signal valid_post_seed_merger : std_logic_vector(2 downto 0); signal ready_post_seed_merger : std_logic_vector(2 downto 0); signal track_post_seed_merger : track_with_idx_t3; signal valid_post_seed_uniq : std_logic_vector(2 downto 0); signal ready_post_seed_uniq : std_logic_vector(2 downto 0); signal track_post_seed_uniq : track_with_idx_t3; signal valid_post_zch_merger : std_logic; signal ready_post_zch_merger : std_logic; signal track_post_zch_merger : track_with_zpos_t; signal valid_post_zch_uniq : std_logic; signal ready_post_zch_uniq : std_logic; signal track_post_zch_uniq : track_with_zpos_t; signal valid_post_zch_resorter : std_logic; signal ready_post_zch_resorter : std_logic; signal track_post_zch_resorter : track_t; begin gen_ch : for ch in 2 downto 0 generate seed_merger_i : entity work.seed_merger port map ( clk => clk, rst_n => rst_n, pretrigger => pretrigger, valid_in => valid_in_i(ch), ready_in => ready_in_I(ch), track2_in => track_in(ch)(2), track1_in => track_in(ch)(1), track0_in => track_in(ch)(0), valid_out => valid_post_seed_merger(ch), ready_out => ready_post_seed_merger(ch), track_out => track_post_seed_merger(ch)); seed_uniq_i : entity work.uniquifier generic map ( width => track_with_idx_width) port map ( clk => clk, rst_n => rst_n, track_in => track_post_seed_merger(ch), valid_in => valid_post_seed_merger(ch), ready_in => ready_post_seed_merger(ch), track_out => track_post_seed_uniq(ch), valid_out => valid_post_seed_uniq(ch), ready_out => ready_post_seed_uniq(ch)); end generate; zch_merger_i : entity work.zch_merger port map ( clk => clk, rst_n => rst_n, pretrigger => pretrigger, valid_in => valid_post_seed_uniq, ready_in => ready_post_seed_uniq, track2_in => track_post_seed_uniq(2), track1_in => track_post_seed_uniq(1), track0_in => track_post_seed_uniq(0), valid_out => valid_post_zch_merger, ready_out => ready_post_zch_merger, track_out => track_post_zch_merger); zch_uniq_i : entity work.uniquifier generic map ( width => track_with_zpos_width) port map ( clk => clk, rst_n => rst_n, track_in => track_post_zch_merger, valid_in => valid_post_zch_merger, ready_in => ready_post_zch_merger, track_out => track_post_zch_uniq, valid_out => valid_post_zch_uniq, ready_out => ready_post_zch_uniq); zch_resorter_i : entity work.zch_resorter port map ( clk => clk, rst_n => rst_n, pretrigger => pretrigger, valid_in => valid_post_zch_uniq, ready_in => ready_post_zch_uniq, track_in => track_post_zch_uniq, valid_out => valid_post_zch_resorter, ready_out => ready_post_zch_resorter, track_out => track_post_zch_resorter); final_uniq_i : entity work.uniquifier generic map ( width => track_width) port map ( clk => clk, rst_n => rst_n, track_in => track_post_zch_resorter, valid_in => valid_post_zch_resorter, ready_in => ready_post_zch_resorter, track_out => track_out, valid_out => valid_out, ready_out => ready_out); -- connect input signals valid_in_i(2)(2) <= valid_in(8); valid_in_i(2)(1) <= valid_in(7); valid_in_i(2)(0) <= valid_in(6); valid_in_i(1)(2) <= valid_in(5); valid_in_i(1)(1) <= valid_in(4); valid_in_i(1)(0) <= valid_in(3); valid_in_i(0)(2) <= valid_in(2); valid_in_i(0)(1) <= valid_in(1); valid_in_i(0)(0) <= valid_in(0); ready_in_i(2)(2) <= ready_in(8); ready_in_i(2)(1) <= ready_in(7); ready_in_i(2)(0) <= ready_in(6); ready_in_i(1)(2) <= ready_in(5); ready_in_i(1)(1) <= ready_in(4); ready_in_i(1)(0) <= ready_in(3); ready_in_i(0)(2) <= ready_in(2); ready_in_i(0)(1) <= ready_in(1); ready_in_i(0)(0) <= ready_in(0); track_in(2)(2) <= track8_in; track_in(2)(1) <= track7_in; track_in(2)(0) <= track6_in; track_in(1)(2) <= track5_in; track_in(1)(1) <= track4_in; track_in(1)(0) <= track3_in; track_in(0)(2) <= track2_in; track_in(0)(1) <= track1_in; track_in(0)(0) <= track0_in; end;