------------------------------------------------------------------------------- -- Title : Top Level -- Project : Prototype implementation of the GTU of the Alice TRD Experiment ------------------------------------------------------------------------------- -- File : toplevel.vhd -- Author : Jan de Cuveland -- Company : -- Last update: 2003/07/02 -- Platform : ------------------------------------------------------------------------------- -- This is a prototype implementation of the Global Tracking Unit (GTU) -- of the Alice TRD detector. ------------------------------------------------------------------------------- -- Description: Top Level ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/02/04 1.0 cuveland Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.gtu_types.all; use work.track_types.all; ------------------------------------------------------------------------------- entity toplevel is port ( chamber : in unsigned(2 downto 0); -- 0..4 clk : in std_logic; -- external clock rst_n : in std_logic; -- asynchronous reset (active low) pretrigger : in std_logic; clk1_in : in std_logic_vector(5 downto 0); clk0_in : in std_logic_vector(5 downto 0); valid1_in : in std_logic_vector(5 downto 0); valid0_in : in std_logic_vector(5 downto 0); d1_in5 : in std_logic_vector(7 downto 0); -- data1 in [5] d0_in5 : in std_logic_vector(7 downto 0); -- data0 in [5] d1_in4 : in std_logic_vector(7 downto 0); -- data1 in [4] d0_in4 : in std_logic_vector(7 downto 0); -- data0 in [4] d1_in3 : in std_logic_vector(7 downto 0); -- data1 in [3] d0_in3 : in std_logic_vector(7 downto 0); -- data0 in [3] d1_in2 : in std_logic_vector(7 downto 0); -- data1 in [2] d0_in2 : in std_logic_vector(7 downto 0); -- data0 in [2] d1_in1 : in std_logic_vector(7 downto 0); -- data1 in [1] d0_in1 : in std_logic_vector(7 downto 0); -- data0 in [1] d1_in0 : in std_logic_vector(7 downto 0); -- data1 in [0] d0_in0 : in std_logic_vector(7 downto 0); -- data0 in [0] valid_out : out std_logic; ready_out : out std_logic; track_out : out std_logic_vector(track_width-1 downto 0); pt_out : out signed(pt_width-1 downto 0)); end toplevel; ------------------------------------------------------------------------------- architecture default of toplevel is type d_in_tn is array (5 downto 0) of std_logic_vector(7 downto 0); signal d0_in, d1_in : d_in_tn; type y_tn is array (5 downto 0) of signed(proj_ypos_width-1 downto 0); type raw_y_tn is array (5 downto 0) of signed(ypos_width-1 downto 0); type a_tn is array (5 downto 0) of signed(deflang_width-1 downto 0); type z_tn is array (5 downto 0) of unsigned(zpos_width-1 downto 0); type addr_tn is array (5 downto 0) of unsigned(addr_width-1 downto 0); type pid_tn is array (5 downto 0) of std_logic_vector(pid_width-1 downto 0); type idx_tn is array (5 downto 0) of unsigned(idx_width-1 downto 0); signal mem_addr : addr_tn; signal mem_ys : raw_y_tn; signal mem_pid : pid_tn; signal y_post_input : y_tn; signal a_post_input : a_tn; signal z_post_input : z_tn; signal addr_post_input : addr_tn; signal valid_post_input : std_logic_vector(5 downto 0); type valid_t3n is array(2 downto 0) of std_logic_vector(5 downto 0); type y_t3n is array(2 downto 0) of y_tn; type a_t3n is array(2 downto 0) of a_tn; type idx_t3n is array(2 downto 0) of idx_tn; type addr_t3n is array(2 downto 0) of addr_tn; signal valid_post_zch : valid_t3n; signal y_post_zch : y_t3n; signal a_post_zch : a_t3n; signal idx_post_zch : idx_t3n; signal addr_post_zch : addr_t3n; signal addr2_post_zch : addr_t3n; type track_with_idx_t9 is array (8 downto 0) of track_with_idx_t; signal valid_post_match : std_logic_vector(8 downto 0); signal ready_post_match : std_logic_vector(8 downto 0); signal track_post_match : track_with_idx_t9; signal valid_post_unique : std_logic; signal ready_post_unique : std_logic; signal track_post_unique : std_logic_vector(track_width-1 downto 0); function get_mask ( constant seedline : integer) return integer is begin case seedline is when 3 => return 0; -- mask "000000" when 2 => return 8; -- mask "001000" when 1 => return 12; -- mask "001100" when others => return 0; end case; end get_mask; begin d1_in(5) <= d1_in5; d0_in(5) <= d0_in5; d1_in(4) <= d1_in4; d0_in(4) <= d0_in4; d1_in(3) <= d1_in3; d0_in(3) <= d0_in3; d1_in(2) <= d1_in2; d0_in(2) <= d0_in2; d1_in(1) <= d1_in1; d0_in(1) <= d0_in1; d1_in(0) <= d1_in0; d0_in(0) <= d0_in0; -- generate input units input_gen : for plane in 5 downto 0 generate input_inst : entity work.input generic map ( plane => plane) port map ( chamber => chamber, clk => clk, rst_n => rst_n, pretrigger => pretrigger, clk1_in => clk1_in(plane), valid1_in => valid1_in(plane), d1_in => d1_in(plane), clk0_in => clk0_in(plane), valid0_in => valid0_in(plane), d0_in => d0_in(plane), y_out => y_post_input(plane), a_out => a_post_input(plane), z_out => z_post_input(plane), addr_out => addr_post_input(plane), valid_out => valid_post_input(plane), mem_addr => mem_addr(plane), mem_ys => mem_ys(plane), mem_pid => mem_pid(plane)); end generate input_gen; -- generate z_channel units z_channel_gen1 : for plane in 5 downto 0 generate z_channel_gen2 : for channel_index in 2 downto 0 generate z_channel_inst : entity work.z_channel generic map ( plane => plane, channel_index => channel_index) port map ( chamber => chamber, clk => clk, rst_n => rst_n, valid_in => valid_post_input(plane), y_in => y_post_input(plane), a_in => a_post_input(plane), z_in => z_post_input(plane), addr_in => addr_post_input(plane), valid_out => valid_post_zch(channel_index)(plane), y_out => y_post_zch(channel_index)(plane), a_out => a_post_zch(channel_index)(plane), idx_out => idx_post_zch(channel_index)(plane), addr_out => addr_post_zch(channel_index)(plane), addr2_out => addr2_post_zch(channel_index)(plane)); end generate z_channel_gen2; end generate z_channel_gen1; -- generate matching units match_gen1 : for channel_index in 2 downto 0 generate match_gen2 : for seedline in 3 downto 1 generate match_inst : entity work.match generic map ( seedline => seedline, line_mask => get_mask(seedline)) port map ( clk => clk, rst_n => rst_n, pretrigger => pretrigger, valid_in5 => valid_post_zch(channel_index)(5), y_in5 => y_post_zch(channel_index)(5), a_in5 => a_post_zch(channel_index)(5), idx_in5 => idx_post_zch(channel_index)(5), addr_in5 => addr_post_zch(channel_index)(5), addr2_in5 => addr2_post_zch(channel_index)(5), valid_in4 => valid_post_zch(channel_index)(4), y_in4 => y_post_zch(channel_index)(4), a_in4 => a_post_zch(channel_index)(4), idx_in4 => idx_post_zch(channel_index)(4), addr_in4 => addr_post_zch(channel_index)(4), addr2_in4 => addr2_post_zch(channel_index)(4), valid_in3 => valid_post_zch(channel_index)(3), y_in3 => y_post_zch(channel_index)(3), a_in3 => a_post_zch(channel_index)(3), idx_in3 => idx_post_zch(channel_index)(3), addr_in3 => addr_post_zch(channel_index)(3), addr2_in3 => addr2_post_zch(channel_index)(3), valid_in2 => valid_post_zch(channel_index)(2), y_in2 => y_post_zch(channel_index)(2), a_in2 => a_post_zch(channel_index)(2), idx_in2 => idx_post_zch(channel_index)(2), addr_in2 => addr_post_zch(channel_index)(2), addr2_in2 => addr2_post_zch(channel_index)(2), valid_in1 => valid_post_zch(channel_index)(1), y_in1 => y_post_zch(channel_index)(1), a_in1 => a_post_zch(channel_index)(1), idx_in1 => idx_post_zch(channel_index)(1), addr_in1 => addr_post_zch(channel_index)(1), addr2_in1 => addr2_post_zch(channel_index)(1), valid_in0 => valid_post_zch(channel_index)(0), y_in0 => y_post_zch(channel_index)(0), a_in0 => a_post_zch(channel_index)(0), idx_in0 => idx_post_zch(channel_index)(0), addr_in0 => addr_post_zch(channel_index)(0), addr2_in0 => addr2_post_zch(channel_index)(0), valid_out => valid_post_match(3 * channel_index + seedline - 1), ready_out => ready_post_match(3 * channel_index + seedline - 1), track_out => track_post_match(3 * channel_index + seedline - 1)); end generate match_gen2; end generate match_gen1; -- uniquifying unit unique_inst : entity work.unique port map ( clk => clk, rst_n => rst_n, pretrigger => pretrigger, valid_in => valid_post_match, ready_in => ready_post_match, track8_in => track_post_match(8), track7_in => track_post_match(7), track6_in => track_post_match(6), track5_in => track_post_match(5), track4_in => track_post_match(4), track3_in => track_post_match(3), track2_in => track_post_match(2), track1_in => track_post_match(1), track0_in => track_post_match(0), valid_out => valid_post_unique, ready_out => ready_post_unique, track_out => track_post_unique); -- pt reconstruction unit reconst_inst : entity work.reconst port map ( clk => clk, rst_n => rst_n, valid_in => valid_post_unique, ready_in => ready_post_unique, track_in => track_post_unique, valid_out => valid_out, ready_out => ready_out, track_out => track_out, pt_out => pt_out, mem5_addr => mem_addr(5), mem4_addr => mem_addr(4), mem3_addr => mem_addr(3), mem2_addr => mem_addr(2), mem1_addr => mem_addr(1), mem0_addr => mem_addr(0), mem5_ys => mem_ys(5), mem4_ys => mem_ys(4), mem3_ys => mem_ys(3), mem2_ys => mem_ys(2), mem1_ys => mem_ys(1), mem0_ys => mem_ys(0), mem5_pid => mem_pid(5), mem4_pid => mem_pid(4), mem3_pid => mem_pid(3), mem2_pid => mem_pid(2), mem1_pid => mem_pid(1), mem0_pid => mem_pid(0)); end default;