-------------------------------------------------------------------------------
-- Title      : Wrapper for vendor-specific multiplier
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : mult_wrapper_xilinx.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2004/04/28
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2004/04/27  1.0      cuveland        Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-------------------------------------------------------------------------------

entity mult_wrapper is

  port (
    a      : in  signed(12 downto 0);
    b      : in  signed(12 downto 0);
    aclr   : in  std_logic;
    clk    : in  std_logic;
    result : out signed(17 downto 0));

end mult_wrapper;

-------------------------------------------------------------------------------

architecture default of mult_wrapper is

  signal a_ext       : std_logic_vector(17 downto 0);
  signal b_ext       : std_logic_vector(17 downto 0);
  signal product     : std_logic_vector(35 downto 0);
  signal product_reg : signed(18 downto 0);
  signal result_ext  : signed(18 downto 0);

  component mult18x18
    port (
      a : in  std_logic_vector(17 downto 0);
      b : in  std_logic_vector(17 downto 0);
      p : out std_logic_vector(35 downto 0));
  end component;

begin

  a_ext <= a(12) & a(12) & a(12) & a(12) & a(12) & std_logic_vector(a);
  b_ext <= b(12) & b(12) & b(12) & b(12) & b(12) & std_logic_vector(b);

  mult_inst : mult18x18
    port map (
      a => a_ext,
      b => b_ext,
      p => product);

  process (clk, aclr)
  begin
    if aclr = '1' then
      product_reg <= (product_reg'range => '0');
    elsif clk'event and clk = '1' then
      product_reg <= signed(product(25 downto 7));
    end if;
  end process;

  result_ext <= product_reg + conv_signed(1, product_reg'length);
  result     <= result_ext(18 downto 1);

end default;