-------------------------------------------------------------------------------
-- Title      : Wrapper for vendor-specific multiplier
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : mult_wrapper_lpm.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2004/04/28
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2004/04/27  1.0      cuveland        Created
-------------------------------------------------------------------------------

library ieee, lpm;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use lpm.lpm_components.all;

-------------------------------------------------------------------------------

entity mult_wrapper is

  port (
    a      : in  signed(12 downto 0);
    b      : in  signed(12 downto 0);
    aclr   : in  std_logic;
    clk    : in  std_logic;
    result : out signed(17 downto 0));

end mult_wrapper;

-------------------------------------------------------------------------------

architecture default of mult_wrapper is

  component lpm_mult

    generic (lpm_widtha         : positive;
             lpm_widthb         : positive;
             lpm_widths         : natural := 0;
             lpm_widthp         : positive;
             lpm_representation : string  := "UNSIGNED";
             lpm_pipeline       : integer := 0;
             lpm_type           : string  := "LPM_MULT";
             lpm_hint           : string  := "UNUSED");

    port (dataa       : in  std_logic_vector(lpm_widtha-1 downto 0);
          datab       : in  std_logic_vector(lpm_widthb-1 downto 0);
          aclr, clock : in  std_logic := '0';
          clken       : in  std_logic := '1';
          sum         : in  std_logic_vector(lpm_widths-1 downto 0)
                                      := (others => '0');
          result      : out std_logic_vector(lpm_widthp-1 downto 0));

  end component;

  signal result_slv : std_logic_vector(17 downto 0);
  signal sum : std_logic_vector(8 downto 0);

begin

  sum <= "010000000";
  
  mult_inst : lpm_mult
    generic map (
      lpm_widtha         => 13,
      lpm_widthb         => 13,
      lpm_widths         => 9,
      lpm_widthp         => 18,
      lpm_representation => "SIGNED",
      lpm_pipeline       => 1)
    port map (
      dataa              => std_logic_vector(a),
      datab              => std_logic_vector(b),
      aclr               => aclr,
      clock              => clk,
      sum                => sum,
      result             => result_slv);

  result <= signed(result_slv);

end default;