------------------------------------------------------------------------------- -- Title : Matching Unit -- Project : Prototype implementation of the GTU of the Alice TRD Experiment ------------------------------------------------------------------------------- -- File : match.vhd -- Author : Jan de Cuveland -- Company : -- Last update: 2003/06/16 -- Platform : ------------------------------------------------------------------------------- -- This is a prototype implementation of the Global Tracking Unit (GTU) -- of the Alice TRD detector. ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/03/25 1.0 cuveland Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.gtu_types.all; use work.track_types.all; ------------------------------------------------------------------------------- entity match is generic ( seedline : integer; line_mask : integer); port ( clk : in std_logic; rst_n : in std_logic; pretrigger : in std_logic; valid_in5 : in std_logic; y_in5 : in signed(proj_ypos_width-1 downto 0); a_in5 : in signed(deflang_width-1 downto 0); idx_in5 : in unsigned(idx_width-1 downto 0); addr_in5 : in unsigned(addr_width-1 downto 0); addr2_in5 : in unsigned(addr_width-1 downto 0); valid_in4 : in std_logic; y_in4 : in signed(proj_ypos_width-1 downto 0); a_in4 : in signed(deflang_width-1 downto 0); idx_in4 : in unsigned(idx_width-1 downto 0); addr_in4 : in unsigned(addr_width-1 downto 0); addr2_in4 : in unsigned(addr_width-1 downto 0); valid_in3 : in std_logic; y_in3 : in signed(proj_ypos_width-1 downto 0); a_in3 : in signed(deflang_width-1 downto 0); idx_in3 : in unsigned(idx_width-1 downto 0); addr_in3 : in unsigned(addr_width-1 downto 0); addr2_in3 : in unsigned(addr_width-1 downto 0); valid_in2 : in std_logic; y_in2 : in signed(proj_ypos_width-1 downto 0); a_in2 : in signed(deflang_width-1 downto 0); idx_in2 : in unsigned(idx_width-1 downto 0); addr_in2 : in unsigned(addr_width-1 downto 0); addr2_in2 : in unsigned(addr_width-1 downto 0); valid_in1 : in std_logic; y_in1 : in signed(proj_ypos_width-1 downto 0); a_in1 : in signed(deflang_width-1 downto 0); idx_in1 : in unsigned(idx_width-1 downto 0); addr_in1 : in unsigned(addr_width-1 downto 0); addr2_in1 : in unsigned(addr_width-1 downto 0); valid_in0 : in std_logic; y_in0 : in signed(proj_ypos_width-1 downto 0); a_in0 : in signed(deflang_width-1 downto 0); idx_in0 : in unsigned(idx_width-1 downto 0); addr_in0 : in unsigned(addr_width-1 downto 0); addr2_in0 : in unsigned(addr_width-1 downto 0); valid_out : out std_logic; ready_out : out std_logic; track_out : out std_logic_vector(track_with_idx_width-1 downto 0)); end match; ------------------------------------------------------------------------------- architecture default of match is -- Type Definitions type addr_tn is array (5 downto 0) of unsigned(5 downto 0); type y_tn is array (5 downto 0) of signed(proj_ypos_width-1 downto 0); type a_tn is array (5 downto 0) of signed(deflang_width-1 downto 0); type idx_tn is array (5 downto 0) of unsigned(2 downto 0); type inc_tn is array (5 downto 0) of unsigned(1 downto 0); -- Input Signals signal valid_in : std_logic_vector(5 downto 0); signal y_in : y_tn; signal a_in : a_tn; signal idx_in : idx_tn; signal addr_in : addr_tn; signal addr2_in : addr_tn; -- Output Signals signal addr_out : addr_tn; signal matchvec : std_logic_vector(5 downto 0); signal idx_out : std_logic_vector(idx_width-1 downto 0); signal y_out : std_logic_vector(approx_ypos_width-1 downto 0); signal ab_select : std_logic_vector(5 downto 0); signal idx_a : idx_tn; signal idx_b : idx_tn; signal y_a : y_tn; signal y_b : y_tn; signal a_a : a_tn; signal a_b : a_tn; -- internal signals signal inc : inc_tn; signal invalid, ready : std_logic_vector(5 downto 0); signal all_ready : std_logic; signal match_i : std_logic; begin gen : for i in 5 downto 0 generate -- instances of memory unit matching_memory1 : entity work.matching_memory port map ( clk => clk, rst_n => rst_n, pretrigger => pretrigger, valid_in => valid_in(i), y_in => y_in(i), a_in => a_in(i), idx_in => idx_in(i), addr_in => addr_in(i), addr2_in => addr2_in(i), ab_select => ab_select(i), inc => inc(i), idx_a => idx_a(i), idx_b => idx_b(i), y_a => y_a(i), y_b => y_b(i), a_a => a_a(i), a_b => a_b(i), addr_out => addr_out(i), invalid => invalid(i), ready => ready(i)); end generate; -- instance of matching logic matching_logic1 : entity work.matching_logic generic map ( seedline => seedline, line_mask => line_mask) port map ( i5a => idx_a(5), i5b => idx_b(5), i4a => idx_a(4), i4b => idx_b(4), i3a => idx_a(3), i3b => idx_b(3), i2a => idx_a(2), i2b => idx_b(2), i1a => idx_a(1), i1b => idx_b(1), i0a => idx_a(0), i0b => idx_b(0), y5a => y_a(5), y5b => y_b(5), y4a => y_a(4), y4b => y_b(4), y3a => y_a(3), y3b => y_b(3), y2a => y_a(2), y2b => y_b(2), y1a => y_a(1), y1b => y_b(1), y0a => y_a(0), y0b => y_b(0), a5a => a_a(5), a5b => a_b(5), a4a => a_a(4), a4b => a_b(4), a3a => a_a(3), a3b => a_b(3), a2a => a_a(2), a2b => a_b(2), a1a => a_a(1), a1b => a_b(1), a0a => a_a(0), a0b => a_b(0), inc5 => inc(5), inc4 => inc(4), inc3 => inc(3), inc2 => inc(2), inc1 => inc(1), inc0 => inc(0), match => match_i, matchvec => matchvec, ab_select => ab_select); -- Connect Input Signals valid_in(5) <= valid_in5; valid_in(4) <= valid_in4; valid_in(3) <= valid_in3; valid_in(2) <= valid_in2; valid_in(1) <= valid_in1; valid_in(0) <= valid_in0; y_in(5) <= y_in5; y_in(4) <= y_in4; y_in(3) <= y_in3; y_in(2) <= y_in2; y_in(1) <= y_in1; y_in(0) <= y_in0; a_in(5) <= a_in5; a_in(4) <= a_in4; a_in(3) <= a_in3; a_in(2) <= a_in2; a_in(1) <= a_in1; a_in(0) <= a_in0; idx_in(5) <= idx_in5; idx_in(4) <= idx_in4; idx_in(3) <= idx_in3; idx_in(2) <= idx_in2; idx_in(1) <= idx_in1; idx_in(0) <= idx_in0; addr_in(5) <= addr_in5; addr_in(4) <= addr_in4; addr_in(3) <= addr_in3; addr_in(2) <= addr_in2; addr_in(1) <= addr_in1; addr_in(0) <= addr_in0; addr2_in(5) <= addr2_in5; addr2_in(4) <= addr2_in4; addr2_in(3) <= addr2_in3; addr2_in(2) <= addr2_in2; addr2_in(1) <= addr2_in1; addr2_in(0) <= addr2_in0; -- Connect Output Signals track_out(matchvec_high downto matchvec_low) <= matchvec; track_out(y_high downto y_low) <= y_out; track_out(idx_high downto idx_low) <= idx_out; gen2 : for i in 5 downto 0 generate track_out(addr0_high + i * 6 downto addr0_low + i * 6) <= std_logic_vector(addr_out(i)); end generate; process (clk) begin if clk'event and clk = '1' then if ready = "111111" then all_ready <= '1'; else all_ready <= '0'; end if; end if; end process; ready_out <= all_ready; valid_out <= '1' when match_i = '1' and invalid = "000000" and all_ready = '0' else '0'; idx_out <= std_logic_vector(idx_a(seedline)) when ab_select(seedline) = '0' else std_logic_vector(idx_b(seedline)); y_out <= std_logic_vector(y_a(seedline)(proj_ypos_width-1 downto approx_ypos_bit_decrease)) when ab_select(seedline) = '0' else std_logic_vector(y_b(seedline)(proj_ypos_width-1 downto approx_ypos_bit_decrease)); end;