-------------------------------------------------------------------------------
-- Title      : Input Control Logic
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : inputcontrol.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2003/05/16
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: Input Control Logic
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/02/03  1.0      cuveland        Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.gtu_types.all;

-------------------------------------------------------------------------------

entity inputcontrol is

  port (
    rst_n      : in std_logic;
    pretrigger : in std_logic;

    clk_in   : in std_logic;                     -- External Clock (120 MHz)
    valid_in : in std_logic;                     -- Data valid (DDR)
    d_in     : in std_logic_vector(7 downto 0);  -- Data from de-serializer
                                                 -- (DDR)

    valid_out : out std_logic;                       -- High if data is valid
    d_out     : out std_logic_vector(31 downto 0));  -- Data to process

end inputcontrol;

-------------------------------------------------------------------------------

architecture default of inputcontrol is

  signal i          : std_logic_vector(15 downto 0);
  signal i_lo, i_hi : std_logic_vector(7 downto 0);
  signal i_valid    : std_logic;
  signal enable     : std_logic;

  signal stage_a, stage_b : std_logic_vector(15 downto 0);
  signal stage_b2         : std_logic_vector(15 downto 0);

  type state_t is (idle, low_word, high_word);
  signal state, next_state : state_t;

  signal d_out_reg     : std_logic_vector(31 downto 0);
  signal valid_out_reg : std_logic;

  signal stage_a_end, next_stage_a_end : std_logic;

begin

  i <= i_hi & i_lo;
  
  -- input register for falling edge
  process (clk_in, rst_n)
  begin
    if rst_n = '0' then
      i_lo <= (i_lo'range => '0');
    elsif falling_edge(clk_in) then
      i_lo <= d_in;
    end if;
  end process;

  -- input register for rising edge
  process (clk_in, rst_n)
  begin
    if rst_n = '0' then
      i_hi    <= (i_hi'range => '0');
      i_valid <= '0';
    elsif rising_edge(clk_in) then
      i_hi    <= d_in;
      i_valid <= valid_in;
    end if;
  end process;

  -- data buffers
  process (clk_in, rst_n)
  begin
    if rst_n = '0' then
      stage_a       <= (stage_a'range => '0');
      stage_a_end   <= '0';
      stage_b       <= (stage_b'range => '0');
    elsif falling_edge(clk_in) then
      if i_valid = '1' then
        stage_a     <= i;
        stage_a_end <= next_stage_a_end;
        stage_b     <= stage_a;
      end if;
    end if;
  end process;

  next_stage_a_end <= '1' when is_end_word(i) else '0';

  -- FSM register
  process (clk_in, rst_n)
  begin
    if rst_n = '0' then
      state <= idle;
    elsif rising_edge(clk_in) then
      state <= next_state;
    end if;
  end process;

  process (state, pretrigger, i_valid, stage_a_end, stage_b)
  begin
    next_state <= idle;
    enable     <= '0';
    stage_b2   <= stage_b;

    if pretrigger = '1' then
      next_state <= low_word;

    elsif state = low_word then
      if i_valid = '1' then
        if stage_a_end = '1' then
          enable     <= '1';
          stage_b2   <= link_end_word;
          next_state <= idle;
        else
          next_state <= high_word;
        end if;
      else
        next_state   <= low_word;
      end if;

    elsif state = high_word then
      if i_valid = '1' then
        enable     <= '1';
        next_state <= low_word;
      else
        next_state <= high_word;
      end if;
    end if;

  end process;

  -- output registers
  process (clk_in, rst_n)
  begin
    if rst_n = '0' then
      d_out_reg     <= (d_out_reg'range => '0');
      valid_out_reg <= '0';
    elsif rising_edge(clk_in) then
      if enable = '1' then
        d_out_reg   <= stage_a & stage_b2;
      else
        d_out_reg   <= (d_out_reg'range => '0');
      end if;
      valid_out_reg <= enable;
    end if;
  end process;

  d_out     <= d_out_reg;
  valid_out <= valid_out_reg;

end default;