------------------------------------------------------------------------------- -- Title : Input Unit -- Project : Prototype implementation of the GTU of the Alice TRD Experiment ------------------------------------------------------------------------------- -- File : input.vhd -- Author : Jan de Cuveland -- Company : -- Last update: 2003/07/07 -- Platform : ------------------------------------------------------------------------------- -- This is a prototype implementation of the Global Tracking Unit (GTU) -- of the Alice TRD detector. ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/03/11 1.0 cuveland Created -- 2006/06/22 1.1 angelov Memory instantiated ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.gtu_types.all; ------------------------------------------------------------------------------- entity input is generic ( plane : integer := 1); -- 1 in order to compile independently port ( chamber : in unsigned(2 downto 0); -- 0..4 clk : in std_logic; rst_n : in std_logic; pretrigger : in std_logic; -- link 1 clk1_in : in std_logic; valid1_in : in std_logic; d1_in : in std_logic_vector(7 downto 0); -- link 0 clk0_in : in std_logic; valid0_in : in std_logic; d0_in : in std_logic_vector(7 downto 0); -- outputs y_out : out signed(proj_ypos_width-1 downto 0); a_out : out signed(deflang_width-1 downto 0); z_out : out unsigned(zpos_width-1 downto 0); addr_out : out unsigned(addr_width-1 downto 0); valid_out : out std_logic; -- memory read interface mem_addr : in unsigned(addr_width-1 downto 0); mem_ys : out signed(ypos_width-1 downto 0); mem_pid : out std_logic_vector(pid_width-1 downto 0) ); end input; ------------------------------------------------------------------------------- architecture default of input is component dpram64xN is generic (Nd : Integer := 21); port( clk : in std_logic; we : in std_logic; wa : in unsigned( 5 downto 0); din : in std_logic_vector(Nd-1 downto 0); ra : in unsigned( 5 downto 0); dout : out std_logic_vector(Nd-1 downto 0) ); end component; signal valid1 : std_logic; signal valid0 : std_logic; signal data1 : std_logic_vector(31 downto 0); signal data0 : std_logic_vector(31 downto 0); signal y : signed(ypos_width-1 downto 0); signal d : signed(deflen_width-1 downto 0); signal pid : std_logic_vector(pid_width-1 downto 0); signal end_sig : std_logic; signal addr_cnt : unsigned(addr_width-1 downto 0); -- memory --type mem is array (0 to 63) of -- std_logic_vector(pid_width+ypos_width-1 downto 0); --signal ram_block : mem; signal mem_out : std_logic_vector(pid_width+ypos_width-1 downto 0); signal din_ram : std_logic_vector(pid_width+ypos_width-1 downto 0); -- internal signals signal yt : signed(10 downto 0); signal ys : signed(ypos_width-1 downto 0); signal y_out_int : signed(proj_ypos_width-1 downto 0); signal a_out_int : signed(deflang_width-1 downto 0); signal z_out_int : unsigned(zpos_width-1 downto 0); signal valid_out_int : std_logic; -- output registers signal y_out_reg : signed(proj_ypos_width-1 downto 0); signal a_out_reg : signed(deflang_width-1 downto 0); signal z_out_reg : unsigned(zpos_width-1 downto 0); signal addr_out_reg : unsigned(addr_width-1 downto 0); signal valid_out_reg : std_logic; begin -- link 1 inputcontrol1 : entity work.inputcontrol port map ( rst_n => rst_n, pretrigger => pretrigger, clk_in => clk1_in, valid_in => valid1_in, d_in => d1_in, valid_out => valid1, d_out => data1); -- link 0 inputcontrol0 : entity work.inputcontrol port map ( rst_n => rst_n, pretrigger => pretrigger, clk_in => clk0_in, valid_in => valid0_in, d_in => d0_in, valid_out => valid0, d_out => data0); buffer_merger1 : entity work.buffer_merger port map ( clk => clk, rst_n => rst_n, pretrigger => pretrigger, clk1_in => clk1_in, valid1_in => valid1, data1_in => data1, clk0_in => clk0_in, valid0_in => valid0, data0_in => data0, y_out => y, d_out => d, z_out => z_out_int, pid_out => pid, end_out => end_sig, valid_out => valid_out_int); -- ram block --process (clk) --begin -- if clk'event and clk = '1' then -- if valid_out_int = '1' then -- ram_block(conv_integer(addr_cnt)) <= pid & std_logic_vector(ys); -- end if; -- end if; --end process; --mem_out <= ram_block(conv_integer(unsigned(mem_addr))); din_ram <= pid & std_logic_vector(ys); ramb: dpram64xN generic map(Nd => mem_out'length) port map( clk => clk, we => valid_out_int, wa => addr_cnt, din => din_ram, ra => mem_addr, dout => mem_out ); -- address counter process (clk, rst_n) begin if rst_n = '0' then addr_cnt <= (addr_cnt'range => '0'); elsif clk'event and clk = '1' then if pretrigger = '1' then addr_cnt <= (addr_cnt'range => '0'); elsif valid_out_int = '1' then addr_cnt <= addr_cnt + 1; end if; end if; end process; proj_d1 : entity work.proj_d generic map ( plane => plane) port map ( d => d, y => y, d_out => a_out_int); proj_y1 : entity work.proj_y generic map ( plane => plane) port map ( d => d, y => y, end_sig => end_sig, y_out => y_out_int); yt_lut1 : entity work.yt_lut generic map ( plane => plane) port map ( chamber => chamber, zpos => z_out_int, yt => yt); ys <= y + yt; -- memory interface mem_pid <= mem_out(pid_width+ypos_width-1 downto ypos_width); mem_ys <= signed(mem_out(ypos_width-1 downto 0)); -- output register with asynchronous reset process (clk, rst_n) begin if rst_n = '0' then valid_out_reg <= '0'; elsif clk'event and clk = '1' then valid_out_reg <= valid_out_int; end if; end process; -- output registers without reset process (clk) begin if clk'event and clk = '1' then y_out_reg <= y_out_int; a_out_reg <= a_out_int; z_out_reg <= z_out_int; addr_out_reg <= addr_cnt; end if; end process; -- connect output signals y_out <= y_out_reg; a_out <= a_out_reg; z_out <= z_out_reg; addr_out <= addr_out_reg; valid_out <= valid_out_reg; end default;