-------------------------------------------------------------------------------
-- Title      : Wrapper for vendor-specific dual-clock FIFO
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : fifo_dc_wrapper_xilinx.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2004/04/28
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2004/04/27  1.0      cuveland        Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-------------------------------------------------------------------------------

entity fifo_dc_wrapper is

  port (
    data    : in  std_logic_vector(31 downto 0);
    wrclk   : in  std_logic;
    rdclk   : in  std_logic;
    wrreq   : in  std_logic;
    rdreq   : in  std_logic;
    aclr    : in  std_logic;
    rdempty : out std_logic;
    q       : out std_logic_vector(31 downto 0));

end fifo_dc_wrapper;

-------------------------------------------------------------------------------

architecture default of fifo_dc_wrapper is

  component cg_fifo_dc
    port (
      din    : in  std_logic_vector(31 downto 0);
      wr_en  : in  std_logic;
      wr_clk : in  std_logic;
      rd_en  : in  std_logic;
      rd_clk : in  std_logic;
      ainit  : in  std_logic;
      dout   : out std_logic_vector(31 downto 0);
      full   : out std_logic;
      empty  : out std_logic);
  end component;

begin

  fifo_dc_inst : cg_fifo_dc
    port map (
      din    => data,
      wr_en  => wrreq,
      wr_clk => wrclk,
      rd_en  => rdreq,
      rd_clk => rdclk,
      ainit  => aclr,
      dout   => q,
      full   => open,
      empty  => rdempty);

end default;