-------------------------------------------------------------------------------
-- Title      : Wrapper for vendor-specific dual-clock FIFO
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : fifo_dc_wrapper_lpm.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2004/04/28
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2004/04/27  1.0      cuveland        Created
-------------------------------------------------------------------------------

library ieee, lpm;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use lpm.lpm_components.all;

-------------------------------------------------------------------------------

entity fifo_dc_wrapper is

  port (
    data    : in  std_logic_vector(31 downto 0);
    wrclk   : in  std_logic;
    rdclk   : in  std_logic;
    wrreq   : in  std_logic;
    rdreq   : in  std_logic;
    aclr    : in  std_logic;
    rdempty : out std_logic;
    q       : out std_logic_vector(31 downto 0));

end fifo_dc_wrapper;

-------------------------------------------------------------------------------

architecture default of fifo_dc_wrapper is

  component lpm_fifo_dc

    generic (lpm_width     : positive;
             lpm_widthu    : positive := 1;
             lpm_numwords  : positive;
             lpm_showahead : string   := "OFF";
             lpm_type      : string   := "LPM_FIFO_DC";
             lpm_hint      : string   := "UNUSED");

    port (data             : in  std_logic_vector(lpm_width-1 downto 0);
          wrclock, rdclock,
          wrreq, rdreq     : in  std_logic;
          aclr             : in  std_logic := '0';
          wrfull, rdfull,
          wrempty, rdempty : out std_logic;
          wrusedw, rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
          q                : out std_logic_vector(lpm_width-1 downto 0) );

  end component;

begin

  fifo_dc_inst : lpm_fifo_dc
    generic map (
      lpm_width    => 32,
      lpm_widthu   => 5,
      lpm_numwords => 32)
    port map (
      data         => data,
      wrclock      => wrclk,
      rdclock      => rdclk,
      wrreq        => wrreq,
      rdreq        => rdreq,
      aclr         => aclr,
      wrfull       => open,
      rdfull       => open,
      wrempty      => open,
      rdempty      => rdempty,
      wrusedw      => open,
      rdusedw      => open,
      q            => q);

end default;