library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

-- created 22-Jun-2006 / V.Angelov
-- May be later replace with memory generated by the core-gen

entity dpram64xN is
generic (Nd : Integer := 21);
port(
         clk  : in  std_logic;
         we   : in  std_logic;
         wa   : in  unsigned(   5 downto 0);
         din  : in  std_logic_vector(Nd-1 downto 0);
         ra   : in  unsigned(   5 downto 0);
         dout : out std_logic_vector(Nd-1 downto 0)
         );
end dpram64xN;


architecture behave of dpram64xN is

  -- memory
  type mem is array (0 to 63) of
    std_logic_vector(Nd-1 downto 0);
  signal ram_block : mem;

begin

    -- memory write
    process(clk)
    begin
        if clk'event and clk='1' then
            if we = '1' then
                ram_block(conv_integer(wa)) <= din;
            end if;
        end if;
    end process;


    -- memory read interface
    dout <= ram_block(conv_integer(unsigned(ra)));

end;