-------------------------------------------------------------------------------
-- Title      : Wrapper for vendor-specific divider
-- Project    : Prototype implementation of the GTU of the Alice TRD Experiment
-------------------------------------------------------------------------------
-- File       : divide_wrapper_lpm.vhd
-- Author     : Jan de Cuveland  <cuveland@kip.uni-heidelberg.de>
-- Company    : 
-- Last update: 2004/04/27
-- Platform   : 
-------------------------------------------------------------------------------
-- This is a prototype implementation of the Global Tracking Unit (GTU)
-- of the Alice TRD detector.
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2004/04/27  1.0      cuveland        Created
-------------------------------------------------------------------------------

library ieee, lpm;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use lpm.lpm_components.all;

-------------------------------------------------------------------------------

entity divide_wrapper is

  generic (
    div_stages : integer);

  port (
    numer    : in  signed(20 downto 0);
    denom    : in  signed(15 downto 0);
    aclr     : in  std_logic;
    clk      : in  std_logic;
    quotient : out signed(20 downto 0));

end divide_wrapper;

-------------------------------------------------------------------------------

architecture default of divide_wrapper is

  component lpm_divide

    generic (lpm_widthn            : positive;
             lpm_widthd            : positive;
             lpm_nrepresentation   : string  := "UNSIGNED";
             lpm_drepresentation   : string  := "UNSIGNED";
             lpm_remainderpositive : string  := "TRUE";
             lpm_pipeline          : integer := 0;
             lpm_type              : string  := "LPM_DIVIDE";
             lpm_hint              : string  := "UNUSED");

    port (numer       : in  std_logic_vector(lpm_widthn-1 downto 0);
          denom       : in  std_logic_vector(lpm_widthd-1 downto 0);
          clock, aclr : in  std_logic := '0';
          clken       : in  std_logic := '1';
          quotient    : out std_logic_vector(lpm_widthn-1 downto 0);
          remain      : out std_logic_vector(lpm_widthd-1 downto 0));

  end component;

  signal quotient_slv : std_logic_vector(20 downto 0);

begin

  div_inst : lpm_divide
    generic map (
      lpm_widthn          => 21,
      lpm_widthd          => 16,
      lpm_nrepresentation => "SIGNED",
      lpm_drepresentation => "SIGNED",
      lpm_pipeline        => div_stages)
    port map (
      numer               => std_logic_vector(numer),
      denom               => std_logic_vector(denom),
      clock               => clk,
      aclr                => aclr,
      quotient            => quotient_slv,
      remain              => open);

  quotient <= signed(quotient_slv);

end default;