------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.gtu_types.all; ------------------------------------------------------------------------------- entity unique_tb is end unique_tb; ------------------------------------------------------------------------------- architecture default of unique_tb is component unique port ( clk : in std_logic; rst_n : in std_logic; pretrigger : in std_logic; valid_in : in std_logic_vector(8 downto 0); ready_in : in std_logic_vector(8 downto 0); matchvec_in8 : in std_logic_vector(5 downto 0); addr5_in8 : in unsigned(addr_width-1 downto 0); addr4_in8 : in unsigned(addr_width-1 downto 0); addr3_in8 : in unsigned(addr_width-1 downto 0); addr2_in8 : in unsigned(addr_width-1 downto 0); addr1_in8 : in unsigned(addr_width-1 downto 0); addr0_in8 : in unsigned(addr_width-1 downto 0); idx_in8 : in unsigned(idx_width-1 downto 0); y_in8 : in signed(approx_ypos_width-1 downto 0); matchvec_in7 : in std_logic_vector(5 downto 0); addr5_in7 : in unsigned(addr_width-1 downto 0); addr4_in7 : in unsigned(addr_width-1 downto 0); addr3_in7 : in unsigned(addr_width-1 downto 0); addr2_in7 : in unsigned(addr_width-1 downto 0); addr1_in7 : in unsigned(addr_width-1 downto 0); addr0_in7 : in unsigned(addr_width-1 downto 0); idx_in7 : in unsigned(idx_width-1 downto 0); y_in7 : in signed(approx_ypos_width-1 downto 0); matchvec_in6 : in std_logic_vector(5 downto 0); addr5_in6 : in unsigned(addr_width-1 downto 0); addr4_in6 : in unsigned(addr_width-1 downto 0); addr3_in6 : in unsigned(addr_width-1 downto 0); addr2_in6 : in unsigned(addr_width-1 downto 0); addr1_in6 : in unsigned(addr_width-1 downto 0); addr0_in6 : in unsigned(addr_width-1 downto 0); idx_in6 : in unsigned(idx_width-1 downto 0); y_in6 : in signed(approx_ypos_width-1 downto 0); matchvec_in5 : in std_logic_vector(5 downto 0); addr5_in5 : in unsigned(addr_width-1 downto 0); addr4_in5 : in unsigned(addr_width-1 downto 0); addr3_in5 : in unsigned(addr_width-1 downto 0); addr2_in5 : in unsigned(addr_width-1 downto 0); addr1_in5 : in unsigned(addr_width-1 downto 0); addr0_in5 : in unsigned(addr_width-1 downto 0); idx_in5 : in unsigned(idx_width-1 downto 0); y_in5 : in signed(approx_ypos_width-1 downto 0); matchvec_in4 : in std_logic_vector(5 downto 0); addr5_in4 : in unsigned(addr_width-1 downto 0); addr4_in4 : in unsigned(addr_width-1 downto 0); addr3_in4 : in unsigned(addr_width-1 downto 0); addr2_in4 : in unsigned(addr_width-1 downto 0); addr1_in4 : in unsigned(addr_width-1 downto 0); addr0_in4 : in unsigned(addr_width-1 downto 0); idx_in4 : in unsigned(idx_width-1 downto 0); y_in4 : in signed(approx_ypos_width-1 downto 0); matchvec_in3 : in std_logic_vector(5 downto 0); addr5_in3 : in unsigned(addr_width-1 downto 0); addr4_in3 : in unsigned(addr_width-1 downto 0); addr3_in3 : in unsigned(addr_width-1 downto 0); addr2_in3 : in unsigned(addr_width-1 downto 0); addr1_in3 : in unsigned(addr_width-1 downto 0); addr0_in3 : in unsigned(addr_width-1 downto 0); idx_in3 : in unsigned(idx_width-1 downto 0); y_in3 : in signed(approx_ypos_width-1 downto 0); matchvec_in2 : in std_logic_vector(5 downto 0); addr5_in2 : in unsigned(addr_width-1 downto 0); addr4_in2 : in unsigned(addr_width-1 downto 0); addr3_in2 : in unsigned(addr_width-1 downto 0); addr2_in2 : in unsigned(addr_width-1 downto 0); addr1_in2 : in unsigned(addr_width-1 downto 0); addr0_in2 : in unsigned(addr_width-1 downto 0); idx_in2 : in unsigned(idx_width-1 downto 0); y_in2 : in signed(approx_ypos_width-1 downto 0); matchvec_in1 : in std_logic_vector(5 downto 0); addr5_in1 : in unsigned(addr_width-1 downto 0); addr4_in1 : in unsigned(addr_width-1 downto 0); addr3_in1 : in unsigned(addr_width-1 downto 0); addr2_in1 : in unsigned(addr_width-1 downto 0); addr1_in1 : in unsigned(addr_width-1 downto 0); addr0_in1 : in unsigned(addr_width-1 downto 0); idx_in1 : in unsigned(idx_width-1 downto 0); y_in1 : in signed(approx_ypos_width-1 downto 0); matchvec_in0 : in std_logic_vector(5 downto 0); addr5_in0 : in unsigned(addr_width-1 downto 0); addr4_in0 : in unsigned(addr_width-1 downto 0); addr3_in0 : in unsigned(addr_width-1 downto 0); addr2_in0 : in unsigned(addr_width-1 downto 0); addr1_in0 : in unsigned(addr_width-1 downto 0); addr0_in0 : in unsigned(addr_width-1 downto 0); idx_in0 : in unsigned(idx_width-1 downto 0); y_in0 : in signed(approx_ypos_width-1 downto 0); valid_out : out std_logic; ready_out : out std_logic; matchvec_out : out std_logic_vector(5 downto 0); addr5_out : out unsigned(addr_width-1 downto 0); addr4_out : out unsigned(addr_width-1 downto 0); addr3_out : out unsigned(addr_width-1 downto 0); addr2_out : out unsigned(addr_width-1 downto 0); addr1_out : out unsigned(addr_width-1 downto 0); addr0_out : out unsigned(addr_width-1 downto 0)); end component; signal clk_i : std_logic; signal rst_n_i : std_logic; signal pretrigger_i : std_logic; signal valid_in_i : std_logic_vector(8 downto 0); signal ready_in_i : std_logic_vector(8 downto 0); signal matchvec_in8_i : std_logic_vector(5 downto 0); signal addr5_in8_i : unsigned(addr_width-1 downto 0); signal addr4_in8_i : unsigned(addr_width-1 downto 0); signal addr3_in8_i : unsigned(addr_width-1 downto 0); signal addr2_in8_i : unsigned(addr_width-1 downto 0); signal addr1_in8_i : unsigned(addr_width-1 downto 0); signal addr0_in8_i : unsigned(addr_width-1 downto 0); signal idx_in8_i : unsigned(idx_width-1 downto 0); signal y_in8_i : signed(approx_ypos_width-1 downto 0); signal matchvec_in7_i : std_logic_vector(5 downto 0); signal addr5_in7_i : unsigned(addr_width-1 downto 0); signal addr4_in7_i : unsigned(addr_width-1 downto 0); signal addr3_in7_i : unsigned(addr_width-1 downto 0); signal addr2_in7_i : unsigned(addr_width-1 downto 0); signal addr1_in7_i : unsigned(addr_width-1 downto 0); signal addr0_in7_i : unsigned(addr_width-1 downto 0); signal idx_in7_i : unsigned(idx_width-1 downto 0); signal y_in7_i : signed(approx_ypos_width-1 downto 0); signal matchvec_in6_i : std_logic_vector(5 downto 0); signal addr5_in6_i : unsigned(addr_width-1 downto 0); signal addr4_in6_i : unsigned(addr_width-1 downto 0); signal addr3_in6_i : unsigned(addr_width-1 downto 0); signal addr2_in6_i : unsigned(addr_width-1 downto 0); signal addr1_in6_i : unsigned(addr_width-1 downto 0); signal addr0_in6_i : unsigned(addr_width-1 downto 0); signal idx_in6_i : unsigned(idx_width-1 downto 0); signal y_in6_i : signed(approx_ypos_width-1 downto 0); signal matchvec_in5_i : std_logic_vector(5 downto 0); signal addr5_in5_i : unsigned(addr_width-1 downto 0); signal addr4_in5_i : unsigned(addr_width-1 downto 0); signal addr3_in5_i : unsigned(addr_width-1 downto 0); signal addr2_in5_i : unsigned(addr_width-1 downto 0); signal addr1_in5_i : unsigned(addr_width-1 downto 0); signal addr0_in5_i : unsigned(addr_width-1 downto 0); signal idx_in5_i : unsigned(idx_width-1 downto 0); signal y_in5_i : signed(approx_ypos_width-1 downto 0); signal matchvec_in4_i : std_logic_vector(5 downto 0); signal addr5_in4_i : unsigned(addr_width-1 downto 0); signal addr4_in4_i : unsigned(addr_width-1 downto 0); signal addr3_in4_i : unsigned(addr_width-1 downto 0); signal addr2_in4_i : unsigned(addr_width-1 downto 0); signal addr1_in4_i : unsigned(addr_width-1 downto 0); signal addr0_in4_i : unsigned(addr_width-1 downto 0); signal idx_in4_i : unsigned(idx_width-1 downto 0); signal y_in4_i : signed(approx_ypos_width-1 downto 0); signal matchvec_in3_i : std_logic_vector(5 downto 0); signal addr5_in3_i : unsigned(addr_width-1 downto 0); signal addr4_in3_i : unsigned(addr_width-1 downto 0); signal addr3_in3_i : unsigned(addr_width-1 downto 0); signal addr2_in3_i : unsigned(addr_width-1 downto 0); signal addr1_in3_i : unsigned(addr_width-1 downto 0); signal addr0_in3_i : unsigned(addr_width-1 downto 0); signal idx_in3_i : unsigned(idx_width-1 downto 0); signal y_in3_i : signed(approx_ypos_width-1 downto 0); signal matchvec_in2_i : std_logic_vector(5 downto 0); signal addr5_in2_i : unsigned(addr_width-1 downto 0); signal addr4_in2_i : unsigned(addr_width-1 downto 0); signal addr3_in2_i : unsigned(addr_width-1 downto 0); signal addr2_in2_i : unsigned(addr_width-1 downto 0); signal addr1_in2_i : unsigned(addr_width-1 downto 0); signal addr0_in2_i : unsigned(addr_width-1 downto 0); signal idx_in2_i : unsigned(idx_width-1 downto 0); signal y_in2_i : signed(approx_ypos_width-1 downto 0); signal matchvec_in1_i : std_logic_vector(5 downto 0); signal addr5_in1_i : unsigned(addr_width-1 downto 0); signal addr4_in1_i : unsigned(addr_width-1 downto 0); signal addr3_in1_i : unsigned(addr_width-1 downto 0); signal addr2_in1_i : unsigned(addr_width-1 downto 0); signal addr1_in1_i : unsigned(addr_width-1 downto 0); signal addr0_in1_i : unsigned(addr_width-1 downto 0); signal idx_in1_i : unsigned(idx_width-1 downto 0); signal y_in1_i : signed(approx_ypos_width-1 downto 0); signal matchvec_in0_i : std_logic_vector(5 downto 0); signal addr5_in0_i : unsigned(addr_width-1 downto 0); signal addr4_in0_i : unsigned(addr_width-1 downto 0); signal addr3_in0_i : unsigned(addr_width-1 downto 0); signal addr2_in0_i : unsigned(addr_width-1 downto 0); signal addr1_in0_i : unsigned(addr_width-1 downto 0); signal addr0_in0_i : unsigned(addr_width-1 downto 0); signal idx_in0_i : unsigned(idx_width-1 downto 0); signal y_in0_i : signed(approx_ypos_width-1 downto 0); signal valid_out_i : std_logic; signal ready_out_i : std_logic; signal matchvec_out_i : std_logic_vector(5 downto 0); signal addr5_out_i : unsigned(addr_width-1 downto 0); signal addr4_out_i : unsigned(addr_width-1 downto 0); signal addr3_out_i : unsigned(addr_width-1 downto 0); signal addr2_out_i : unsigned(addr_width-1 downto 0); signal addr1_out_i : unsigned(addr_width-1 downto 0); signal addr0_out_i : unsigned(addr_width-1 downto 0); begin -- default DUT : unique port map ( clk => clk_i, rst_n => rst_n_i, pretrigger => pretrigger_i, valid_in => valid_in_i, ready_in => ready_in_i, matchvec_in8 => matchvec_in8_i, addr5_in8 => addr5_in8_i, addr4_in8 => addr4_in8_i, addr3_in8 => addr3_in8_i, addr2_in8 => addr2_in8_i, addr1_in8 => addr1_in8_i, addr0_in8 => addr0_in8_i, idx_in8 => idx_in8_i, y_in8 => y_in8_i, matchvec_in7 => matchvec_in7_i, addr5_in7 => addr5_in7_i, addr4_in7 => addr4_in7_i, addr3_in7 => addr3_in7_i, addr2_in7 => addr2_in7_i, addr1_in7 => addr1_in7_i, addr0_in7 => addr0_in7_i, idx_in7 => idx_in7_i, y_in7 => y_in7_i, matchvec_in6 => matchvec_in6_i, addr5_in6 => addr5_in6_i, addr4_in6 => addr4_in6_i, addr3_in6 => addr3_in6_i, addr2_in6 => addr2_in6_i, addr1_in6 => addr1_in6_i, addr0_in6 => addr0_in6_i, idx_in6 => idx_in6_i, y_in6 => y_in6_i, matchvec_in5 => matchvec_in5_i, addr5_in5 => addr5_in5_i, addr4_in5 => addr4_in5_i, addr3_in5 => addr3_in5_i, addr2_in5 => addr2_in5_i, addr1_in5 => addr1_in5_i, addr0_in5 => addr0_in5_i, idx_in5 => idx_in5_i, y_in5 => y_in5_i, matchvec_in4 => matchvec_in4_i, addr5_in4 => addr5_in4_i, addr4_in4 => addr4_in4_i, addr3_in4 => addr3_in4_i, addr2_in4 => addr2_in4_i, addr1_in4 => addr1_in4_i, addr0_in4 => addr0_in4_i, idx_in4 => idx_in4_i, y_in4 => y_in4_i, matchvec_in3 => matchvec_in3_i, addr5_in3 => addr5_in3_i, addr4_in3 => addr4_in3_i, addr3_in3 => addr3_in3_i, addr2_in3 => addr2_in3_i, addr1_in3 => addr1_in3_i, addr0_in3 => addr0_in3_i, idx_in3 => idx_in3_i, y_in3 => y_in3_i, matchvec_in2 => matchvec_in2_i, addr5_in2 => addr5_in2_i, addr4_in2 => addr4_in2_i, addr3_in2 => addr3_in2_i, addr2_in2 => addr2_in2_i, addr1_in2 => addr1_in2_i, addr0_in2 => addr0_in2_i, idx_in2 => idx_in2_i, y_in2 => y_in2_i, matchvec_in1 => matchvec_in1_i, addr5_in1 => addr5_in1_i, addr4_in1 => addr4_in1_i, addr3_in1 => addr3_in1_i, addr2_in1 => addr2_in1_i, addr1_in1 => addr1_in1_i, addr0_in1 => addr0_in1_i, idx_in1 => idx_in1_i, y_in1 => y_in1_i, matchvec_in0 => matchvec_in0_i, addr5_in0 => addr5_in0_i, addr4_in0 => addr4_in0_i, addr3_in0 => addr3_in0_i, addr2_in0 => addr2_in0_i, addr1_in0 => addr1_in0_i, addr0_in0 => addr0_in0_i, idx_in0 => idx_in0_i, y_in0 => y_in0_i, valid_out => valid_out_i, ready_out => ready_out_i, matchvec_out => matchvec_out_i, addr5_out => addr5_out_i, addr4_out => addr4_out_i, addr3_out => addr3_out_i, addr2_out => addr2_out_i, addr1_out => addr1_out_i, addr0_out => addr0_out_i); pretrigger_i <= '0'; process begin clk_i <= '1'; wait for 5 ns; clk_i <= '0'; wait for 5 ns; end process; -- channel 0, reset process begin y_in2_i <= (y_in2_i'range => '0'); y_in1_i <= (y_in1_i'range => '0'); y_in0_i <= (y_in0_i'range => '0'); idx_in2_i <= (idx_in2_i'range => '0'); idx_in1_i <= (idx_in1_i'range => '0'); idx_in0_i <= (idx_in0_i'range => '0'); valid_in_i(2 downto 0) <= "000"; ready_in_i(2 downto 0) <= "000"; rst_n_i <= '0'; wait for 28 ns; rst_n_i <= '1'; idx_in2_i <= conv_unsigned(0, idx_in2_i'length); idx_in1_i <= conv_unsigned(1, idx_in2_i'length); valid_in_i(2 downto 0) <= "110"; wait for 10 ns; ready_in_i(0) <= '1'; idx_in2_i <= conv_unsigned(2, idx_in2_i'length); valid_in_i(2 downto 0) <= "100"; wait for 10 ns; ready_in_i(1) <= '1'; idx_in2_i <= conv_unsigned(3, idx_in2_i'length); valid_in_i(2 downto 0) <= "100"; wait for 10 ns; ready_in_i(2) <= '1'; idx_in2_i <= conv_unsigned(3, idx_in2_i'length); valid_in_i(2 downto 0) <= "000"; wait; end process; -- channel 1 (uniquifier test) process begin y_in5_i <= (y_in2_i'range => '0'); y_in4_i <= (y_in1_i'range => '0'); y_in3_i <= (y_in0_i'range => '0'); idx_in5_i <= (idx_in2_i'range => '0'); idx_in4_i <= (idx_in1_i'range => '0'); idx_in3_i <= (idx_in0_i'range => '0'); ready_in_i(5 downto 3) <= "110"; valid_in_i(5 downto 3) <= "000"; wait for 28 ns; y_in3_i <= conv_signed(0, y_in3_i'length); addr0_in3_i <= conv_unsigned(0, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(0, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(0, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(0, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(0, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(0, addr5_in3_i'length); matchvec_in3_i <= "000000"; valid_in_i(3) <= '0'; wait for 10 ns; y_in3_i <= conv_signed(1, y_in3_i'length); addr0_in3_i <= conv_unsigned(1, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(1, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(1, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(1, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(1, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(1, addr5_in3_i'length); matchvec_in3_i <= "011111"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(2, y_in3_i'length); addr0_in3_i <= conv_unsigned(0, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(0, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(0, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(0, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(0, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(0, addr5_in3_i'length); matchvec_in3_i <= "000000"; valid_in_i(3) <= '0'; wait for 10 ns; y_in3_i <= conv_signed(3, y_in3_i'length); wait for 10 ns; y_in3_i <= conv_signed(4, y_in3_i'length); addr0_in3_i <= conv_unsigned(0, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(4, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(1, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(1, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(4, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(0, addr5_in3_i'length); matchvec_in3_i <= "011110"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(5, y_in3_i'length); addr0_in3_i <= conv_unsigned(0, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(5, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(6, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(6, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(5, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(0, addr5_in3_i'length); matchvec_in3_i <= "011110"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(6, y_in3_i'length); addr0_in3_i <= conv_unsigned(6, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(6, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(6, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(6, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(6, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(6, addr5_in3_i'length); matchvec_in3_i <= "011111"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(7, y_in3_i'length); addr0_in3_i <= conv_unsigned(7, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(7, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(6, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(7, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(7, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(7, addr5_in3_i'length); matchvec_in3_i <= "001111"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(8, y_in3_i'length); addr0_in3_i <= conv_unsigned(8, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(8, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(8, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(8, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(8, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(8, addr5_in3_i'length); matchvec_in3_i <= "011011"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(9, y_in3_i'length); addr0_in3_i <= conv_unsigned(0, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(0, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(0, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(0, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(0, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(0, addr5_in3_i'length); matchvec_in3_i <= "000000"; valid_in_i(3) <= '0'; wait for 10 ns; y_in3_i <= conv_signed(10, y_in3_i'length); wait for 10 ns; y_in3_i <= conv_signed(11, y_in3_i'length); addr0_in3_i <= conv_unsigned(11, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(11, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(11, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(11, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(11, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(11, addr5_in3_i'length); matchvec_in3_i <= "011011"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(12, y_in3_i'length); addr0_in3_i <= conv_unsigned(12, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(12, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(12, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(12, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(12, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(13, addr5_in3_i'length); matchvec_in3_i <= "011011"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(13, y_in3_i'length); addr0_in3_i <= conv_unsigned(13, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(13, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(14, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(13, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(13, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(13, addr5_in3_i'length); matchvec_in3_i <= "010111"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(14, y_in3_i'length); addr0_in3_i <= conv_unsigned(14, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(14, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(14, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(14, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(14, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(14, addr5_in3_i'length); matchvec_in3_i <= "111110"; valid_in_i(3) <= '1'; wait for 10 ns; y_in3_i <= conv_signed(15, y_in3_i'length); addr0_in3_i <= conv_unsigned(15, addr0_in3_i'length); addr1_in3_i <= conv_unsigned(15, addr1_in3_i'length); addr2_in3_i <= conv_unsigned(15, addr2_in3_i'length); addr3_in3_i <= conv_unsigned(15, addr3_in3_i'length); addr4_in3_i <= conv_unsigned(15, addr4_in3_i'length); addr5_in3_i <= conv_unsigned(15, addr5_in3_i'length); matchvec_in3_i <= "011011"; valid_in_i(3) <= '1'; wait for 10 ns; valid_in_i(3) <= '0'; ready_in_i(3) <= '1'; wait; end process; -- channel 2 ready_in_i(8 downto 6) <= "111"; valid_in_i(8 downto 6) <= "000"; end default; -------------------------------------------------------------------------------